From: Harsh Prateek Bora <harshpb@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: Aboorva Devarajan <aboorvad@linux.ibm.com>,
Nikhil Kumar Singh <nikhilks@linux.ibm.com>,
Glenn Miles <milesg@linux.ibm.com>,
Amit Machhiwal <amachhiw@linux.ibm.com>,
Chinmay Rath <rathc@linux.ibm.com>,
Aniket Sahu <asahu1x@linux.ibm.com>
Subject: [PULL 09/41] target/ppc: Move vector pack instructions to decodetree
Date: Fri, 28 Aug 2026 11:36:44 +0530 [thread overview]
Message-ID: <20260828060716.91672-10-harshpb@linux.ibm.com> (raw)
In-Reply-To: <20260828060716.91672-1-harshpb@linux.ibm.com>
From: Aboorva Devarajan <aboorvad@linux.ibm.com>
Move below instructions to decodetree specification:
vpkuhum, vpkuwum, vpkuhus, vpkuwus : VX-form (PPC_ALTIVEC)
vpkshus, vpkswus, vpkshss, vpkswss : VX-form (PPC_ALTIVEC)
vpkpx : VX-form (PPC_ALTIVEC)
vpkudum, vpkudus, vpksdus, vpksdss : VX-form (PPC2_ALTIVEC_207)
The legacy GEN_VXFORM_ENV/GEN_VXFORM macros that generated gen_vpk*()
functions reading register fields from ctx->opcode are replaced by new
do_vpk_env()/do_vpk() helpers in vmx-impl.c.inc that use the
pre-extracted decodetree argument fields (a->vrt, a->vra, a->vrb)
directly. The existing gen_helper_vpk*() implementations in
int_helper.c are reused without changes.
The changes were verified by validating that the tcg ops generated by
those instructions remain the same, which were captured with the '-d
in_asm,op' option before and after the patch.
Signed-off-by: Aboorva Devarajan <aboorvad@linux.ibm.com>
Reviewed-by: Nikhil Kumar Singh <nikhilks@linux.ibm.com>
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Tested-by: Aniket Sahu <asahu1x@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-6-rathc@linux.ibm.com
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
---
target/ppc/helper.h | 26 +++++++--------
target/ppc/insn32.decode | 16 +++++++++
target/ppc/int_helper.c | 28 ++++++++--------
target/ppc/translate/vmx-impl.c.inc | 51 +++++++++++++++++++++--------
target/ppc/translate/vmx-ops.c.inc | 13 --------
5 files changed, 81 insertions(+), 53 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 5517d2950f..a0d08d6192 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -249,19 +249,19 @@ DEF_HELPER_FLAGS_4(VMSUMUBM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr)
DEF_HELPER_FLAGS_4(VMSUMMBM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr)
DEF_HELPER_FLAGS_4(VPERM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr)
DEF_HELPER_FLAGS_4(VPERMR, TCG_CALL_NO_RWG, void, avr, avr, avr, avr)
-DEF_HELPER_4(vpkshss, void, env, avr, avr, avr)
-DEF_HELPER_4(vpkshus, void, env, avr, avr, avr)
-DEF_HELPER_4(vpkswss, void, env, avr, avr, avr)
-DEF_HELPER_4(vpkswus, void, env, avr, avr, avr)
-DEF_HELPER_4(vpksdss, void, env, avr, avr, avr)
-DEF_HELPER_4(vpksdus, void, env, avr, avr, avr)
-DEF_HELPER_4(vpkuhus, void, env, avr, avr, avr)
-DEF_HELPER_4(vpkuwus, void, env, avr, avr, avr)
-DEF_HELPER_4(vpkudus, void, env, avr, avr, avr)
-DEF_HELPER_4(vpkuhum, void, env, avr, avr, avr)
-DEF_HELPER_4(vpkuwum, void, env, avr, avr, avr)
-DEF_HELPER_4(vpkudum, void, env, avr, avr, avr)
-DEF_HELPER_FLAGS_3(vpkpx, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_4(VPKSHSS, void, env, avr, avr, avr)
+DEF_HELPER_4(VPKSHUS, void, env, avr, avr, avr)
+DEF_HELPER_4(VPKSWSS, void, env, avr, avr, avr)
+DEF_HELPER_4(VPKSWUS, void, env, avr, avr, avr)
+DEF_HELPER_4(VPKSDSS, void, env, avr, avr, avr)
+DEF_HELPER_4(VPKSDUS, void, env, avr, avr, avr)
+DEF_HELPER_4(VPKUHUS, void, env, avr, avr, avr)
+DEF_HELPER_4(VPKUWUS, void, env, avr, avr, avr)
+DEF_HELPER_4(VPKUDUS, void, env, avr, avr, avr)
+DEF_HELPER_4(VPKUHUM, void, env, avr, avr, avr)
+DEF_HELPER_4(VPKUWUM, void, env, avr, avr, avr)
+DEF_HELPER_4(VPKUDUM, void, env, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VPKPX, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_5(VMHADDSHS, void, env, avr, avr, avr, avr)
DEF_HELPER_5(VMHRADDSHS, void, env, avr, avr, avr, avr)
DEF_HELPER_FLAGS_4(VMSUMUHM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 99f7421e77..d6f1875532 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -1054,6 +1054,22 @@ VSTRIHR 000100 ..... 00011 ..... . 0000001101 @VX_tb_rc
VCLRLB 000100 ..... ..... ..... 00110001101 @VX
VCLRRB 000100 ..... ..... ..... 00111001101 @VX
+## Vector Pack Instructions
+
+VPKUHUM 000100 ..... ..... ..... 0000000111 0 @VX
+VPKUWUM 000100 ..... ..... ..... 0000100111 0 @VX
+VPKUDUM 000100 ..... ..... ..... 1000100111 0 @VX
+VPKUHUS 000100 ..... ..... ..... 0001000111 0 @VX
+VPKUWUS 000100 ..... ..... ..... 0001100111 0 @VX
+VPKUDUS 000100 ..... ..... ..... 1001100111 0 @VX
+VPKSHUS 000100 ..... ..... ..... 0010000111 0 @VX
+VPKSWUS 000100 ..... ..... ..... 0010100111 0 @VX
+VPKSDUS 000100 ..... ..... ..... 1010100111 0 @VX
+VPKSHSS 000100 ..... ..... ..... 0011000111 0 @VX
+VPKSWSS 000100 ..... ..... ..... 0011100111 0 @VX
+VPKSDSS 000100 ..... ..... ..... 1011100111 0 @VX
+VPKPX 000100 ..... ..... ..... 0110000111 0 @VX
+
# VSX Load/Store Instructions
LXSD 111001 ..... ..... .............. 10 @DS
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index a3adf746bd..dc55ccadf7 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1465,7 +1465,7 @@ void helper_VPMSUMD(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
#else
#define PKBIG 0
#endif
-void helper_vpkpx(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+void helper_VPKPX(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
{
int i, j;
ppc_avr_t result;
@@ -1488,7 +1488,7 @@ void helper_vpkpx(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
}
#define VPK(suffix, from, to, cvt, dosat) \
- void helper_vpk##suffix(CPUPPCState *env, ppc_avr_t *r, \
+ void helper_VPK##suffix(CPUPPCState *env, ppc_avr_t *r, \
ppc_avr_t *a, ppc_avr_t *b) \
{ \
int i; \
@@ -1507,18 +1507,18 @@ void helper_vpkpx(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
} \
}
#define I(x, y) (x)
-VPK(shss, s16, s8, cvtshsb, 1)
-VPK(shus, s16, u8, cvtshub, 1)
-VPK(swss, s32, s16, cvtswsh, 1)
-VPK(swus, s32, u16, cvtswuh, 1)
-VPK(sdss, s64, s32, cvtsdsw, 1)
-VPK(sdus, s64, u32, cvtsduw, 1)
-VPK(uhus, u16, u8, cvtuhub, 1)
-VPK(uwus, u32, u16, cvtuwuh, 1)
-VPK(udus, u64, u32, cvtuduw, 1)
-VPK(uhum, u16, u8, I, 0)
-VPK(uwum, u32, u16, I, 0)
-VPK(udum, u64, u32, I, 0)
+VPK(SHSS, s16, s8, cvtshsb, 1)
+VPK(SHUS, s16, u8, cvtshub, 1)
+VPK(SWSS, s32, s16, cvtswsh, 1)
+VPK(SWUS, s32, u16, cvtswuh, 1)
+VPK(SDSS, s64, s32, cvtsdsw, 1)
+VPK(SDUS, s64, u32, cvtsduw, 1)
+VPK(UHUS, u16, u8, cvtuhub, 1)
+VPK(UWUS, u32, u16, cvtuwuh, 1)
+VPK(UDUS, u64, u32, cvtuduw, 1)
+VPK(UHUM, u16, u8, I, 0)
+VPK(UWUM, u32, u16, I, 0)
+VPK(UDUM, u64, u32, I, 0)
#undef I
#undef VPK
#undef PKBIG
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 00b359f031..65230f3461 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1070,19 +1070,44 @@ TRANS(VRLQMI, do_vector_rotl_quad, false, true)
GEN_VXFORM_TRANS(vsl, 2, 7);
GEN_VXFORM_TRANS(vsr, 2, 11);
-GEN_VXFORM_ENV(vpkuhum, 7, 0);
-GEN_VXFORM_ENV(vpkuwum, 7, 1);
-GEN_VXFORM_ENV(vpkudum, 7, 17);
-GEN_VXFORM_ENV(vpkuhus, 7, 2);
-GEN_VXFORM_ENV(vpkuwus, 7, 3);
-GEN_VXFORM_ENV(vpkudus, 7, 19);
-GEN_VXFORM_ENV(vpkshus, 7, 4);
-GEN_VXFORM_ENV(vpkswus, 7, 5);
-GEN_VXFORM_ENV(vpksdus, 7, 21);
-GEN_VXFORM_ENV(vpkshss, 7, 6);
-GEN_VXFORM_ENV(vpkswss, 7, 7);
-GEN_VXFORM_ENV(vpksdss, 7, 23);
-GEN_VXFORM(vpkpx, 7, 12);
+static bool do_vpk_env(DisasContext *ctx, arg_VX *a,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr,
+ TCGv_ptr, TCGv_ptr))
+{
+ TCGv_ptr ra, rb, rd;
+ REQUIRE_VECTOR(ctx);
+ ra = gen_avr_ptr(a->vra);
+ rb = gen_avr_ptr(a->vrb);
+ rd = gen_avr_ptr(a->vrt);
+ gen_helper(tcg_env, rd, ra, rb);
+ return true;
+}
+
+static bool do_vpk(DisasContext *ctx, arg_VX *a,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr))
+{
+ TCGv_ptr ra, rb, rd;
+ REQUIRE_VECTOR(ctx);
+ ra = gen_avr_ptr(a->vra);
+ rb = gen_avr_ptr(a->vrb);
+ rd = gen_avr_ptr(a->vrt);
+ gen_helper(rd, ra, rb);
+ return true;
+}
+
+TRANS_FLAGS(ALTIVEC, VPKUHUM, do_vpk_env, gen_helper_VPKUHUM)
+TRANS_FLAGS(ALTIVEC, VPKUWUM, do_vpk_env, gen_helper_VPKUWUM)
+TRANS_FLAGS2(ALTIVEC_207, VPKUDUM, do_vpk_env, gen_helper_VPKUDUM)
+TRANS_FLAGS(ALTIVEC, VPKUHUS, do_vpk_env, gen_helper_VPKUHUS)
+TRANS_FLAGS(ALTIVEC, VPKUWUS, do_vpk_env, gen_helper_VPKUWUS)
+TRANS_FLAGS2(ALTIVEC_207, VPKUDUS, do_vpk_env, gen_helper_VPKUDUS)
+TRANS_FLAGS(ALTIVEC, VPKSHUS, do_vpk_env, gen_helper_VPKSHUS)
+TRANS_FLAGS(ALTIVEC, VPKSWUS, do_vpk_env, gen_helper_VPKSWUS)
+TRANS_FLAGS2(ALTIVEC_207, VPKSDUS, do_vpk_env, gen_helper_VPKSDUS)
+TRANS_FLAGS(ALTIVEC, VPKSHSS, do_vpk_env, gen_helper_VPKSHSS)
+TRANS_FLAGS(ALTIVEC, VPKSWSS, do_vpk_env, gen_helper_VPKSWSS)
+TRANS_FLAGS2(ALTIVEC_207, VPKSDSS, do_vpk_env, gen_helper_VPKSDSS)
+TRANS_FLAGS(ALTIVEC, VPKPX, do_vpk, gen_helper_VPKPX)
GEN_VXFORM_ENV(vsum4ubs, 4, 24);
GEN_VXFORM_ENV(vsum4sbs, 4, 28);
GEN_VXFORM_ENV(vsum4shs, 4, 25);
diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc
index b8f77d3d2c..2820976c0f 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -59,19 +59,6 @@ GEN_VXFORM_300(bcdtrunc, 0, 20),
GEN_VXFORM_300(bcdutrunc, 0, 21),
GEN_VXFORM(vsl, 2, 7),
GEN_VXFORM(vsr, 2, 11),
-GEN_VXFORM(vpkuhum, 7, 0),
-GEN_VXFORM(vpkuwum, 7, 1),
-GEN_VXFORM_207(vpkudum, 7, 17),
-GEN_VXFORM(vpkuhus, 7, 2),
-GEN_VXFORM(vpkuwus, 7, 3),
-GEN_VXFORM_207(vpkudus, 7, 19),
-GEN_VXFORM(vpkshus, 7, 4),
-GEN_VXFORM(vpkswus, 7, 5),
-GEN_VXFORM_207(vpksdus, 7, 21),
-GEN_VXFORM(vpkshss, 7, 6),
-GEN_VXFORM(vpkswss, 7, 7),
-GEN_VXFORM_207(vpksdss, 7, 23),
-GEN_VXFORM(vpkpx, 7, 12),
GEN_VXFORM(vsum4ubs, 4, 24),
GEN_VXFORM(vsum4sbs, 4, 28),
GEN_VXFORM(vsum4shs, 4, 25),
--
2.52.0
next prev parent reply other threads:[~2026-08-28 6:09 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-28 6:06 [PULL 00/41] ppc-for-11.2 queue Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 01/41] linux-headers: Update to include KVM_CAP_PPC_COMPAT_CAPS Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 02/41] target/ppc/kvm: Add support for querying host compatibility mode Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 03/41] target/ppc/kvm: Use host compatibility mode for nested guests Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 04/41] ppc/xive: Trigger the pending interrupt for a guest after migration Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 05/41] target/ppc: Migrate extswsli to decodetree Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 06/41] target/ppc: Migrate atomic loads " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 07/41] target/ppc: Convert cache instructions " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 08/41] target/ppc: Move vector merge " Harsh Prateek Bora
2026-08-28 6:06 ` Harsh Prateek Bora [this message]
2026-08-28 6:06 ` [PULL 10/41] target/ppc: Move st{b, h, w, d, q}cx " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 11/41] target/ppc: convert slw, srw instruction via decode spec Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 12/41] target/ppc: convert sraw[i] " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 13/41] target/ppc: Convert mcrf to decode tree Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 14/41] target/ppc: Move fixed-point Shift insns to decodetree Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 15/41] target/ppc: Move fixed-point byte-reversal store " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 16/41] target/ppc: Move GPR atomic load/store instructions " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 17/41] target/ppc: Move isync instruction " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 18/41] target/ppc: Convert b{a, l, la} to decode tree Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 19/41] target/ppc: move various conditional branch insns to decodetree Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 20/41] target/ppc: Fix TRANS* macro variadic arguments handling Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 21/41] target/ppc: Move wait instruction to decodetree Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 22/41] target/ppc: Move sleep & friends " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 23/41] target/ppc: Refactor sleep and its variants to use a common helper Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 24/41] target/ppc: Move Condition Register access instructions to decodetree Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 25/41] target/ppc: Move Condition Register logical " Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 26/41] target/ppc: make do_ea_calc_ra available for 32 bit builds Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 27/41] target/ppc: Move Fixed-Point Load/Store String instructions to decodetree Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 28/41] target/ppc: Move VMX integer arithmetic and BCD " Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 29/41] target/ppc: Move rlwimi, rlwinm " Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 30/41] target/ppc: Move lmw, stmw " Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 31/41] target/ppc: Move mfmsr, mtmsr[d] " Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 32/41] target/ppc: Move byte-reverse " Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 33/41] target/ppc: Move system call and rfi " Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 34/41] target/ppc: Replace PPC2_VSX207 flag with PPC2_ISA207 Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 35/41] target/ppc: Use PPC2_ISA207 instead of PPC2_BCTAR_ISA207 Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 36/41] target/ppc: Use PPC2_ISA207 instead of PPC2_LSQ_ISA207 Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 37/41] target/ppc: Use PPC2_ISA207 instead of PPC2_ALTIVEC_207 Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 38/41] target/ppc: Use PPC2_ISA207 instead of PPC2_ISA207S Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 39/41] target/ppc: Reorder PPC2 flags Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 40/41] target/ppc: Add ICBT support for ISA version 2.07 Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 41/41] target/ppc: Add self as maintainer for PowerPC TCG CPUs Harsh Prateek Bora
2026-08-28 23:34 ` [PULL 00/41] ppc-for-11.2 queue Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260828060716.91672-10-harshpb@linux.ibm.com \
--to=harshpb@linux.ibm.com \
--cc=aboorvad@linux.ibm.com \
--cc=amachhiw@linux.ibm.com \
--cc=asahu1x@linux.ibm.com \
--cc=milesg@linux.ibm.com \
--cc=nikhilks@linux.ibm.com \
--cc=qemu-devel@nongnu.org \
--cc=rathc@linux.ibm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.