From: Harsh Prateek Bora <harshpb@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: Ojaswin Mujoo <ojaswin@linux.ibm.com>,
Glenn Miles <milesg@linux.ibm.com>,
Amit Machhiwal <amachhiw@linux.ibm.com>,
Chinmay Rath <rathc@linux.ibm.com>,
Aniket Sahu <asahu1x@linux.ibm.com>
Subject: [PULL 22/41] target/ppc: Move sleep & friends to decodetree
Date: Fri, 28 Aug 2026 11:36:57 +0530 [thread overview]
Message-ID: <20260828060716.91672-23-harshpb@linux.ibm.com> (raw)
In-Reply-To: <20260828060716.91672-1-harshpb@linux.ibm.com>
From: Ojaswin Mujoo <ojaswin@linux.ibm.com>
Convert the following instructions to decode tree specification:
doze
nap
sleep
rvwinkle
stop
The functionality was tested by comparing the qemu -D log -d op,in_asm
output as well as single stepping gdb to confirm behavior was not
changed for ISA3.x (stop) as well as ISA206 (doze, nap, sleep,
rvwinkle).
Signed-off-by: Ojaswin Mujoo <ojaswin@linux.ibm.com>
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Tested-by: Aniket Sahu <asahu1x@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-19-rathc@linux.ibm.com
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
---
target/ppc/insn32.decode | 8 ++
target/ppc/translate.c | 85 ---------------
.../ppc/translate/processor-ctrl-impl.c.inc | 100 ++++++++++++++++++
3 files changed, 108 insertions(+), 85 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index da32ac1d28..b833244932 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -913,6 +913,14 @@ VPERMR 000100 ..... ..... ..... ..... 111011 @VA
VSEL 000100 ..... ..... ..... ..... 101010 @VA
+## Power Management Instructions
+
+DOZE 010011 ----- ----- ----- 0110010010 -
+NAP 010011 ----- ----- ----- 0110110010 -
+SLEEP 010011 ----- ----- ----- 0111010010 -
+RVWINKLE 010011 ----- ----- ----- 0111110010 -
+STOP 010011 ----- ----- ----- 0101110010 -
+
## Vector Integer Shift Instruction
VSLB 000100 ..... ..... ..... 00100000100 @VX
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index e5ed4d2cc4..9d9823f92d 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2728,86 +2728,6 @@ static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
#endif
#if defined(TARGET_PPC64)
-static void gen_doze(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV(ctx);
-#else
- TCGv_i32 t;
-
- CHK_HV(ctx);
- translator_io_start(&ctx->base);
- t = tcg_constant_i32(PPC_PM_DOZE);
- gen_helper_pminsn(tcg_env, t);
- /* Stop translation, as the CPU is supposed to sleep from now */
- gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
-static void gen_nap(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV(ctx);
-#else
- TCGv_i32 t;
-
- CHK_HV(ctx);
- translator_io_start(&ctx->base);
- t = tcg_constant_i32(PPC_PM_NAP);
- gen_helper_pminsn(tcg_env, t);
- /* Stop translation, as the CPU is supposed to sleep from now */
- gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
-static void gen_stop(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV(ctx);
-#else
- TCGv_i32 t;
-
- CHK_HV(ctx);
- translator_io_start(&ctx->base);
- t = tcg_constant_i32(PPC_PM_STOP);
- gen_helper_pminsn(tcg_env, t);
- /* Stop translation, as the CPU is supposed to sleep from now */
- gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
-static void gen_sleep(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV(ctx);
-#else
- TCGv_i32 t;
-
- CHK_HV(ctx);
- translator_io_start(&ctx->base);
- t = tcg_constant_i32(PPC_PM_SLEEP);
- gen_helper_pminsn(tcg_env, t);
- /* Stop translation, as the CPU is supposed to sleep from now */
- gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
-static void gen_rvwinkle(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV(ctx);
-#else
- TCGv_i32 t;
-
- CHK_HV(ctx);
- translator_io_start(&ctx->base);
- t = tcg_constant_i32(PPC_PM_RVWINKLE);
- gen_helper_pminsn(tcg_env, t);
- /* Stop translation, as the CPU is supposed to sleep from now */
- gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
static inline TCGv gen_write_bhrb(TCGv_ptr base, TCGv offset, TCGv mask, TCGv value)
{
TCGv_ptr tmp = tcg_temp_new_ptr();
@@ -5104,11 +5024,6 @@ GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300),
#endif
-GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
-GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
-GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
-GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
#endif
/* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
diff --git a/target/ppc/translate/processor-ctrl-impl.c.inc b/target/ppc/translate/processor-ctrl-impl.c.inc
index 8abbb89630..a96c9c87ce 100644
--- a/target/ppc/translate/processor-ctrl-impl.c.inc
+++ b/target/ppc/translate/processor-ctrl-impl.c.inc
@@ -103,3 +103,103 @@ static bool trans_MSGSYNC(DisasContext *ctx, arg_MSGSYNC *a)
/* interpreted as no-op */
return true;
}
+
+static bool do_doze(DisasContext *ctx, arg_DOZE *a)
+{
+ REQUIRE_64BIT(ctx);
+
+#if defined(CONFIG_USER_ONLY)
+ gen_priv_opc(ctx);
+#else
+ TCGv_i32 t;
+
+ REQUIRE_HV(ctx);
+ translator_io_start(&ctx->base);
+ t = tcg_constant_i32(PPC_PM_DOZE);
+ gen_helper_pminsn(tcg_env, t);
+ /* Stop translation, as the CPU is supposed to sleep from now */
+ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
+#endif /* defined(CONFIG_USER_ONLY) */
+ return true;
+}
+TRANS_FLAGS2(PM_ISA206, DOZE, do_doze);
+
+static bool do_nap(DisasContext *ctx, arg_NAP *a)
+{
+ REQUIRE_64BIT(ctx);
+
+#if defined(CONFIG_USER_ONLY)
+ gen_priv_opc(ctx);
+#else
+ TCGv_i32 t;
+
+ REQUIRE_HV(ctx);
+ translator_io_start(&ctx->base);
+ t = tcg_constant_i32(PPC_PM_NAP);
+ gen_helper_pminsn(tcg_env, t);
+ /* Stop translation, as the CPU is supposed to sleep from now */
+ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
+#endif /* defined(CONFIG_USER_ONLY) */
+ return true;
+}
+TRANS_FLAGS2(PM_ISA206, NAP, do_nap);
+
+static bool do_sleep(DisasContext *ctx, arg_SLEEP *a)
+{
+ REQUIRE_64BIT(ctx);
+
+#if defined(CONFIG_USER_ONLY)
+ gen_priv_opc(ctx);
+#else
+ TCGv_i32 t;
+
+ REQUIRE_HV(ctx);
+ translator_io_start(&ctx->base);
+ t = tcg_constant_i32(PPC_PM_SLEEP);
+ gen_helper_pminsn(tcg_env, t);
+ /* Stop translation, as the CPU is supposed to sleep from now */
+ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
+#endif /* defined(CONFIG_USER_ONLY) */
+ return true;
+}
+TRANS_FLAGS2(PM_ISA206, SLEEP, do_sleep);
+
+static bool do_rvwinkle(DisasContext *ctx, arg_RVWINKLE *a)
+{
+ REQUIRE_64BIT(ctx);
+
+#if defined(CONFIG_USER_ONLY)
+ gen_priv_opc(ctx);
+#else
+ TCGv_i32 t;
+
+ REQUIRE_HV(ctx);
+ translator_io_start(&ctx->base);
+ t = tcg_constant_i32(PPC_PM_RVWINKLE);
+ gen_helper_pminsn(tcg_env, t);
+ /* Stop translation, as the CPU is supposed to sleep from now */
+ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
+#endif /* defined(CONFIG_USER_ONLY) */
+ return true;
+}
+TRANS_FLAGS2(PM_ISA206, RVWINKLE, do_rvwinkle);
+
+static bool do_stop(DisasContext *ctx, arg_STOP *a)
+{
+ REQUIRE_64BIT(ctx);
+
+#if defined(CONFIG_USER_ONLY)
+ gen_priv_opc(ctx);
+#else
+ TCGv_i32 t;
+
+ REQUIRE_HV(ctx);
+ translator_io_start(&ctx->base);
+ t = tcg_constant_i32(PPC_PM_STOP);
+ gen_helper_pminsn(tcg_env, t);
+ /* Stop translation, as the CPU is supposed to sleep from now */
+ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
+#endif /* defined(CONFIG_USER_ONLY) */
+ return true;
+}
+TRANS_FLAGS2(ISA300, STOP, do_stop);
--
2.52.0
next prev parent reply other threads:[~2026-08-28 6:09 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-28 6:06 [PULL 00/41] ppc-for-11.2 queue Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 01/41] linux-headers: Update to include KVM_CAP_PPC_COMPAT_CAPS Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 02/41] target/ppc/kvm: Add support for querying host compatibility mode Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 03/41] target/ppc/kvm: Use host compatibility mode for nested guests Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 04/41] ppc/xive: Trigger the pending interrupt for a guest after migration Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 05/41] target/ppc: Migrate extswsli to decodetree Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 06/41] target/ppc: Migrate atomic loads " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 07/41] target/ppc: Convert cache instructions " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 08/41] target/ppc: Move vector merge " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 09/41] target/ppc: Move vector pack " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 10/41] target/ppc: Move st{b, h, w, d, q}cx " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 11/41] target/ppc: convert slw, srw instruction via decode spec Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 12/41] target/ppc: convert sraw[i] " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 13/41] target/ppc: Convert mcrf to decode tree Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 14/41] target/ppc: Move fixed-point Shift insns to decodetree Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 15/41] target/ppc: Move fixed-point byte-reversal store " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 16/41] target/ppc: Move GPR atomic load/store instructions " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 17/41] target/ppc: Move isync instruction " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 18/41] target/ppc: Convert b{a, l, la} to decode tree Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 19/41] target/ppc: move various conditional branch insns to decodetree Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 20/41] target/ppc: Fix TRANS* macro variadic arguments handling Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 21/41] target/ppc: Move wait instruction to decodetree Harsh Prateek Bora
2026-08-28 6:06 ` Harsh Prateek Bora [this message]
2026-08-28 6:06 ` [PULL 23/41] target/ppc: Refactor sleep and its variants to use a common helper Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 24/41] target/ppc: Move Condition Register access instructions to decodetree Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 25/41] target/ppc: Move Condition Register logical " Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 26/41] target/ppc: make do_ea_calc_ra available for 32 bit builds Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 27/41] target/ppc: Move Fixed-Point Load/Store String instructions to decodetree Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 28/41] target/ppc: Move VMX integer arithmetic and BCD " Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 29/41] target/ppc: Move rlwimi, rlwinm " Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 30/41] target/ppc: Move lmw, stmw " Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 31/41] target/ppc: Move mfmsr, mtmsr[d] " Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 32/41] target/ppc: Move byte-reverse " Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 33/41] target/ppc: Move system call and rfi " Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 34/41] target/ppc: Replace PPC2_VSX207 flag with PPC2_ISA207 Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 35/41] target/ppc: Use PPC2_ISA207 instead of PPC2_BCTAR_ISA207 Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 36/41] target/ppc: Use PPC2_ISA207 instead of PPC2_LSQ_ISA207 Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 37/41] target/ppc: Use PPC2_ISA207 instead of PPC2_ALTIVEC_207 Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 38/41] target/ppc: Use PPC2_ISA207 instead of PPC2_ISA207S Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 39/41] target/ppc: Reorder PPC2 flags Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 40/41] target/ppc: Add ICBT support for ISA version 2.07 Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 41/41] target/ppc: Add self as maintainer for PowerPC TCG CPUs Harsh Prateek Bora
2026-08-28 23:34 ` [PULL 00/41] ppc-for-11.2 queue Richard Henderson
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