From: Harsh Prateek Bora <harshpb@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: Chinmay Rath <rathc@linux.ibm.com>,
Glenn Miles <milesg@linux.ibm.com>,
Richard Henderson <richard.henderson@linaro.org>,
Amit Machhiwal <amachhiw@linux.ibm.com>,
Aniket Sahu <asahu1x@linux.ibm.com>
Subject: [PULL 34/41] target/ppc: Replace PPC2_VSX207 flag with PPC2_ISA207
Date: Fri, 28 Aug 2026 11:37:09 +0530 [thread overview]
Message-ID: <20260828060716.91672-35-harshpb@linux.ibm.com> (raw)
In-Reply-To: <20260828060716.91672-1-harshpb@linux.ibm.com>
From: Chinmay Rath <rathc@linux.ibm.com>
There are several flags for Power ISA 2.07 currently in use, namely :
PPC2_VSX207, PPC2_BCTAR_ISA207, PPC2_LSQ_ISA207, etc, but most of them
are used together without any individual use.
Create a generic ISA 2.07 flag and switch usage of PPC2_VSX207 to it
instead. Next commits would consolidate the remaining flags.
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Tested-by: Aniket Sahu <asahu1x@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-31-rathc@linux.ibm.com
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
---
target/ppc/cpu.h | 6 ++--
target/ppc/cpu_init.h | 2 +-
target/ppc/cpu_init.c | 2 +-
target/ppc/translate/fp-impl.c.inc | 4 +--
target/ppc/translate/vsx-impl.c.inc | 56 ++++++++++++++---------------
target/ppc/translate/vsx-ops.c.inc | 24 ++++++-------
6 files changed, 47 insertions(+), 47 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index cbd5964b1a..91ef34cb21 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2565,8 +2565,8 @@ enum {
PPC2_DBRX = 0x0000000000000010ULL,
/* Book I 2.05 PowerPC specification */
PPC2_ISA205 = 0x0000000000000020ULL,
- /* VSX additions in ISA 2.07 */
- PPC2_VSX207 = 0x0000000000000040ULL,
+ /* POWER ISA 2.07 */
+ PPC2_ISA207 = 0x0000000000000040ULL,
/* ISA 2.06B bpermd */
PPC2_PERM_ISA206 = 0x0000000000000080ULL,
/* ISA 2.06B divide extended variants */
@@ -2607,7 +2607,7 @@ enum {
PPC2_PPE42XM = 0x0000000002000000ULL,
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
- PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
+ PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \
PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h
index f8fd6ff5cd..1c41c0d349 100644
--- a/target/ppc/cpu_init.h
+++ b/target/ppc/cpu_init.h
@@ -15,7 +15,7 @@
#define PPC_INSNS_FLAGS_POWER11 PPC_INSNS_FLAGS_POWER10
#define PPC_INSNS_FLAGS2_POWER_COMMON \
- (PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | \
+ (PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | \
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | \
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | \
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index e2533481d8..b913edd243 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6346,7 +6346,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *data)
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD |
PPC_CILDST;
- pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
+ pcc->insns_flags2 = PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX |
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index 464fb1d90f..e0d9fa2e24 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -342,7 +342,7 @@ static bool trans_FCPSGN(DisasContext *ctx, arg_FCPSGN *a)
static bool trans_FMRGEW(DisasContext *ctx, arg_FMRGEW *a)
{
TCGv_i64 t0, t1, t2;
- REQUIRE_INSNS_FLAGS2(ctx, VSX207);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA207);
REQUIRE_FPU(ctx);
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
@@ -358,7 +358,7 @@ static bool trans_FMRGEW(DisasContext *ctx, arg_FMRGEW *a)
static bool trans_FMRGOW(DisasContext *ctx, arg_FMRGOW *a)
{
TCGv_i64 t0, t1, t2;
- REQUIRE_INSNS_FLAGS2(ctx, VSX207);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA207);
REQUIRE_FPU(ctx);
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 00ad57c628..78311dcba9 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -50,11 +50,11 @@ static bool do_lxs(DisasContext *ctx, arg_X *a,
}
TRANS_FLAGS2(VSX, LXSDX, do_lxs, gen_qemu_ld64_i64);
-TRANS_FLAGS2(VSX207, LXSIWAX, do_lxs, gen_qemu_ld32s_i64);
+TRANS_FLAGS2(ISA207, LXSIWAX, do_lxs, gen_qemu_ld32s_i64);
TRANS_FLAGS2(ISA300, LXSIBZX, do_lxs, gen_qemu_ld8u_i64);
TRANS_FLAGS2(ISA300, LXSIHZX, do_lxs, gen_qemu_ld16u_i64);
-TRANS_FLAGS2(VSX207, LXSIWZX, do_lxs, gen_qemu_ld32u_i64);
-TRANS_FLAGS2(VSX207, LXSSPX, do_lxs, gen_qemu_ld32fs);
+TRANS_FLAGS2(ISA207, LXSIWZX, do_lxs, gen_qemu_ld32u_i64);
+TRANS_FLAGS2(ISA207, LXSSPX, do_lxs, gen_qemu_ld32fs);
static bool trans_LXVD2X(DisasContext *ctx, arg_LXVD2X *a)
{
@@ -304,8 +304,8 @@ static bool do_stxs(DisasContext *ctx, arg_X *a,
TRANS_FLAGS2(VSX, STXSDX, do_stxs, gen_qemu_st64_i64);
TRANS_FLAGS2(ISA300, STXSIBX, do_stxs, gen_qemu_st8_i64);
TRANS_FLAGS2(ISA300, STXSIHX, do_stxs, gen_qemu_st16_i64);
-TRANS_FLAGS2(VSX207, STXSIWX, do_stxs, gen_qemu_st32_i64);
-TRANS_FLAGS2(VSX207, STXSSPX, do_stxs, gen_qemu_st32fs);
+TRANS_FLAGS2(ISA207, STXSIWX, do_stxs, gen_qemu_st32_i64);
+TRANS_FLAGS2(ISA207, STXSSPX, do_stxs, gen_qemu_st32fs);
static bool trans_STXVD2X(DisasContext *ctx, arg_STXVD2X *a)
{
@@ -988,7 +988,7 @@ GEN_VSX_HELPER_R2_AB(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
GEN_VSX_HELPER_R2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
-GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
+GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_ISA207)
GEN_VSX_HELPER_R2(xscvqpsdz, 0x04, 0x1A, 0x19, PPC2_ISA300)
GEN_VSX_HELPER_R2(xscvqpswz, 0x04, 0x1A, 0x09, PPC2_ISA300)
GEN_VSX_HELPER_R2(xscvqpudz, 0x04, 0x1A, 0x11, PPC2_ISA300)
@@ -1185,7 +1185,7 @@ bool trans_XSCVSPDPN(DisasContext *ctx, arg_XX2 *a)
{
TCGv_i64 tmp;
- REQUIRE_INSNS_FLAGS2(ctx, VSX207);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA207);
REQUIRE_VSX(ctx);
tmp = tcg_temp_new_i64();
@@ -1210,16 +1210,16 @@ GEN_VSX_HELPER_X2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
GEN_VSX_HELPER_X2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
GEN_VSX_HELPER_X2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
GEN_VSX_HELPER_X2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
-GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
+GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_ISA207)
GEN_VSX_HELPER_R2(xsrqpi, 0x05, 0x00, 0, PPC2_ISA300)
GEN_VSX_HELPER_R2(xsrqpxp, 0x05, 0x01, 0, PPC2_ISA300)
GEN_VSX_HELPER_R2(xssqrtqp, 0x04, 0x19, 0x1B, PPC2_ISA300)
GEN_VSX_HELPER_R3(xssubqp, 0x04, 0x10, 0, PPC2_ISA300)
-GEN_VSX_HELPER_X2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
-GEN_VSX_HELPER_X2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
-GEN_VSX_HELPER_X2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
-GEN_VSX_HELPER_X2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
-GEN_VSX_HELPER_X2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
+GEN_VSX_HELPER_X2(xsresp, 0x14, 0x01, 0, PPC2_ISA207)
+GEN_VSX_HELPER_X2(xssqrtsp, 0x16, 0x00, 0, PPC2_ISA207)
+GEN_VSX_HELPER_X2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_ISA207)
+GEN_VSX_HELPER_X2(xscvsxdsp, 0x10, 0x13, 0, PPC2_ISA207)
+GEN_VSX_HELPER_X2(xscvuxdsp, 0x10, 0x12, 0, PPC2_ISA207)
GEN_VSX_HELPER_X2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
GEN_VSX_HELPER_X2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
@@ -1409,14 +1409,14 @@ TRANS_FLAGS2(VSX, XSNMADDADP, do_xsmadd_XX3, true, gen_helper_XSNMADDDP)
TRANS_FLAGS2(VSX, XSNMADDMDP, do_xsmadd_XX3, false, gen_helper_XSNMADDDP)
TRANS_FLAGS2(VSX, XSNMSUBADP, do_xsmadd_XX3, true, gen_helper_XSNMSUBDP)
TRANS_FLAGS2(VSX, XSNMSUBMDP, do_xsmadd_XX3, false, gen_helper_XSNMSUBDP)
-TRANS_FLAGS2(VSX207, XSMADDASP, do_xsmadd_XX3, true, gen_helper_XSMADDSP)
-TRANS_FLAGS2(VSX207, XSMADDMSP, do_xsmadd_XX3, false, gen_helper_XSMADDSP)
-TRANS_FLAGS2(VSX207, XSMSUBASP, do_xsmadd_XX3, true, gen_helper_XSMSUBSP)
-TRANS_FLAGS2(VSX207, XSMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSMSUBSP)
-TRANS_FLAGS2(VSX207, XSNMADDASP, do_xsmadd_XX3, true, gen_helper_XSNMADDSP)
-TRANS_FLAGS2(VSX207, XSNMADDMSP, do_xsmadd_XX3, false, gen_helper_XSNMADDSP)
-TRANS_FLAGS2(VSX207, XSNMSUBASP, do_xsmadd_XX3, true, gen_helper_XSNMSUBSP)
-TRANS_FLAGS2(VSX207, XSNMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSNMSUBSP)
+TRANS_FLAGS2(ISA207, XSMADDASP, do_xsmadd_XX3, true, gen_helper_XSMADDSP)
+TRANS_FLAGS2(ISA207, XSMADDMSP, do_xsmadd_XX3, false, gen_helper_XSMADDSP)
+TRANS_FLAGS2(ISA207, XSMSUBASP, do_xsmadd_XX3, true, gen_helper_XSMSUBSP)
+TRANS_FLAGS2(ISA207, XSMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSMSUBSP)
+TRANS_FLAGS2(ISA207, XSNMADDASP, do_xsmadd_XX3, true, gen_helper_XSNMADDSP)
+TRANS_FLAGS2(ISA207, XSNMADDMSP, do_xsmadd_XX3, false, gen_helper_XSNMADDSP)
+TRANS_FLAGS2(ISA207, XSNMSUBASP, do_xsmadd_XX3, true, gen_helper_XSNMSUBSP)
+TRANS_FLAGS2(ISA207, XSNMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSNMSUBSP)
static bool do_xsmadd_X(DisasContext *ctx, arg_X_rc *a,
void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr),
@@ -1590,9 +1590,9 @@ TRANS_FLAGS2(VSX, XXLANDC, do_logical_op, MO_64, tcg_gen_gvec_andc);
TRANS_FLAGS2(VSX, XXLOR, do_logical_op, MO_64, tcg_gen_gvec_or);
TRANS_FLAGS2(VSX, XXLXOR, do_logical_op, MO_64, tcg_gen_gvec_xor);
TRANS_FLAGS2(VSX, XXLNOR, do_logical_op, MO_64, tcg_gen_gvec_nor);
-TRANS_FLAGS2(VSX207, XXLEQV, do_logical_op, MO_64, tcg_gen_gvec_eqv);
-TRANS_FLAGS2(VSX207, XXLNAND, do_logical_op, MO_64, tcg_gen_gvec_nand);
-TRANS_FLAGS2(VSX207, XXLORC, do_logical_op, MO_64, tcg_gen_gvec_orc);
+TRANS_FLAGS2(ISA207, XXLEQV, do_logical_op, MO_64, tcg_gen_gvec_eqv);
+TRANS_FLAGS2(ISA207, XXLNAND, do_logical_op, MO_64, tcg_gen_gvec_nand);
+TRANS_FLAGS2(ISA207, XXLORC, do_logical_op, MO_64, tcg_gen_gvec_orc);
#define VSX_XXMRG(name, high) \
static void glue(gen_, name)(DisasContext *ctx) \
@@ -2682,10 +2682,10 @@ TRANS_FLAGS2(ISA300, XSMINCDP, do_helper_XX3, gen_helper_XSMINCDP)
TRANS_FLAGS2(ISA300, XSMAXJDP, do_helper_XX3, gen_helper_XSMAXJDP)
TRANS_FLAGS2(ISA300, XSMINJDP, do_helper_XX3, gen_helper_XSMINJDP)
-TRANS_FLAGS2(VSX207, XSADDSP, do_helper_XX3, gen_helper_XSADDSP)
-TRANS_FLAGS2(VSX207, XSSUBSP, do_helper_XX3, gen_helper_XSSUBSP)
-TRANS_FLAGS2(VSX207, XSMULSP, do_helper_XX3, gen_helper_XSMULSP)
-TRANS_FLAGS2(VSX207, XSDIVSP, do_helper_XX3, gen_helper_XSDIVSP)
+TRANS_FLAGS2(ISA207, XSADDSP, do_helper_XX3, gen_helper_XSADDSP)
+TRANS_FLAGS2(ISA207, XSSUBSP, do_helper_XX3, gen_helper_XSSUBSP)
+TRANS_FLAGS2(ISA207, XSMULSP, do_helper_XX3, gen_helper_XSMULSP)
+TRANS_FLAGS2(ISA207, XSDIVSP, do_helper_XX3, gen_helper_XSDIVSP)
TRANS_FLAGS2(VSX, XSADDDP, do_helper_XX3, gen_helper_XSADDDP)
TRANS_FLAGS2(VSX, XSSUBDP, do_helper_XX3, gen_helper_XSSUBDP)
diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
index e553b5b8fa..ae3df2c13d 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -1,9 +1,9 @@
-GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
-GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
-GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_ISA207),
+GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_ISA207),
+GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_ISA207),
#if defined(TARGET_PPC64)
-GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
-GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_ISA207),
+GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_ISA207),
GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(mtvsrws, 0x1F, 0x13, 0x0C, 0x0000F800, PPC_NONE, PPC2_ISA300),
@@ -127,7 +127,7 @@ GEN_VSX_XFORM_300(xscmpoqp, 0x04, 0x04, 0x00600001),
GEN_VSX_XFORM_300(xscmpuqp, 0x04, 0x14, 0x00600001),
GEN_XX2FORM_EO(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300),
GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
-GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
+GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_ISA207),
GEN_XX2FORM_EO(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300),
GEN_VSX_XFORM_300_EO(xscvsdqp, 0x04, 0x1A, 0x0A, 0x00000001),
GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
@@ -145,12 +145,12 @@ GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
GEN_VSX_XFORM_300(xsdivqp, 0x04, 0x11, 0x0),
-GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
-GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
-GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
-GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
-GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
-GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
+GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_ISA207),
+GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_ISA207),
+GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_ISA207),
+GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_ISA207),
+GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_ISA207),
+GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_ISA207),
GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
--
2.52.0
next prev parent reply other threads:[~2026-08-28 6:12 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-28 6:06 [PULL 00/41] ppc-for-11.2 queue Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 01/41] linux-headers: Update to include KVM_CAP_PPC_COMPAT_CAPS Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 02/41] target/ppc/kvm: Add support for querying host compatibility mode Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 03/41] target/ppc/kvm: Use host compatibility mode for nested guests Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 04/41] ppc/xive: Trigger the pending interrupt for a guest after migration Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 05/41] target/ppc: Migrate extswsli to decodetree Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 06/41] target/ppc: Migrate atomic loads " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 07/41] target/ppc: Convert cache instructions " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 08/41] target/ppc: Move vector merge " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 09/41] target/ppc: Move vector pack " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 10/41] target/ppc: Move st{b, h, w, d, q}cx " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 11/41] target/ppc: convert slw, srw instruction via decode spec Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 12/41] target/ppc: convert sraw[i] " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 13/41] target/ppc: Convert mcrf to decode tree Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 14/41] target/ppc: Move fixed-point Shift insns to decodetree Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 15/41] target/ppc: Move fixed-point byte-reversal store " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 16/41] target/ppc: Move GPR atomic load/store instructions " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 17/41] target/ppc: Move isync instruction " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 18/41] target/ppc: Convert b{a, l, la} to decode tree Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 19/41] target/ppc: move various conditional branch insns to decodetree Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 20/41] target/ppc: Fix TRANS* macro variadic arguments handling Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 21/41] target/ppc: Move wait instruction to decodetree Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 22/41] target/ppc: Move sleep & friends " Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 23/41] target/ppc: Refactor sleep and its variants to use a common helper Harsh Prateek Bora
2026-08-28 6:06 ` [PULL 24/41] target/ppc: Move Condition Register access instructions to decodetree Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 25/41] target/ppc: Move Condition Register logical " Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 26/41] target/ppc: make do_ea_calc_ra available for 32 bit builds Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 27/41] target/ppc: Move Fixed-Point Load/Store String instructions to decodetree Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 28/41] target/ppc: Move VMX integer arithmetic and BCD " Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 29/41] target/ppc: Move rlwimi, rlwinm " Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 30/41] target/ppc: Move lmw, stmw " Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 31/41] target/ppc: Move mfmsr, mtmsr[d] " Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 32/41] target/ppc: Move byte-reverse " Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 33/41] target/ppc: Move system call and rfi " Harsh Prateek Bora
2026-08-28 6:07 ` Harsh Prateek Bora [this message]
2026-08-28 6:07 ` [PULL 35/41] target/ppc: Use PPC2_ISA207 instead of PPC2_BCTAR_ISA207 Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 36/41] target/ppc: Use PPC2_ISA207 instead of PPC2_LSQ_ISA207 Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 37/41] target/ppc: Use PPC2_ISA207 instead of PPC2_ALTIVEC_207 Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 38/41] target/ppc: Use PPC2_ISA207 instead of PPC2_ISA207S Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 39/41] target/ppc: Reorder PPC2 flags Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 40/41] target/ppc: Add ICBT support for ISA version 2.07 Harsh Prateek Bora
2026-08-28 6:07 ` [PULL 41/41] target/ppc: Add self as maintainer for PowerPC TCG CPUs Harsh Prateek Bora
2026-08-28 23:34 ` [PULL 00/41] ppc-for-11.2 queue Richard Henderson
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