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From: Harsh Prateek Bora <harshpb@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: Ojaswin Mujoo <ojaswin@linux.ibm.com>,
	Glenn Miles <milesg@linux.ibm.com>,
	 Amit Machhiwal <amachhiw@linux.ibm.com>,
	Chinmay Rath <rathc@linux.ibm.com>,
	Aniket Sahu <asahu1x@linux.ibm.com>
Subject: [PULL 23/41] target/ppc: Refactor sleep and its variants to use a common helper
Date: Fri, 28 Aug 2026 11:36:58 +0530	[thread overview]
Message-ID: <20260828060716.91672-24-harshpb@linux.ibm.com> (raw)
In-Reply-To: <20260828060716.91672-1-harshpb@linux.ibm.com>

From: Ojaswin Mujoo <ojaswin@linux.ibm.com>

With sleep, doze, nap, rvwinkle and stop instructions moved to
decodetree, the helper these instructions used : gen_helper_pminsn,
should now be renamed to gen_helper_PMINSN, abiding by the decodetree
standards. Do the same.
Also refactor their translation routine to use a common do_sleep routine
since they share majority of the code.

Signed-off-by: Ojaswin Mujoo <ojaswin@linux.ibm.com>
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Tested-by: Aniket Sahu <asahu1x@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-20-rathc@linux.ibm.com
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
---
 target/ppc/helper.h                           |  2 +-
 target/ppc/tcg-excp_helper.c                  |  2 +-
 .../ppc/translate/processor-ctrl-impl.c.inc   | 99 +++----------------
 3 files changed, 17 insertions(+), 86 deletions(-)

diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index e7bf43bf4b..6e14f02598 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -18,7 +18,7 @@ DEF_HELPER_1(rfdi, void, env)
 DEF_HELPER_1(rfmci, void, env)
 #if defined(TARGET_PPC64)
 DEF_HELPER_2(scv, noreturn, env, i32)
-DEF_HELPER_2(pminsn, void, env, i32)
+DEF_HELPER_2(PMINSN, void, env, i32)
 DEF_HELPER_1(rfid, void, env)
 DEF_HELPER_1(rfscv, void, env)
 DEF_HELPER_1(hrfid, void, env)
diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c
index b04f07a637..c4ffa2dfbb 100644
--- a/target/ppc/tcg-excp_helper.c
+++ b/target/ppc/tcg-excp_helper.c
@@ -459,7 +459,7 @@ void helper_scv(CPUPPCState *env, uint32_t lev)
     }
 }
 
-void helper_pminsn(CPUPPCState *env, uint32_t insn)
+void helper_PMINSN(CPUPPCState *env, uint32_t insn)
 {
     CPUState *cs = env_cpu(env);
 
diff --git a/target/ppc/translate/processor-ctrl-impl.c.inc b/target/ppc/translate/processor-ctrl-impl.c.inc
index a96c9c87ce..cfcca28267 100644
--- a/target/ppc/translate/processor-ctrl-impl.c.inc
+++ b/target/ppc/translate/processor-ctrl-impl.c.inc
@@ -104,102 +104,33 @@ static bool trans_MSGSYNC(DisasContext *ctx, arg_MSGSYNC *a)
     return true;
 }
 
-static bool do_doze(DisasContext *ctx, arg_DOZE *a)
-{
-    REQUIRE_64BIT(ctx);
-
-#if defined(CONFIG_USER_ONLY)
-    gen_priv_opc(ctx);
-#else
-    TCGv_i32 t;
-
-    REQUIRE_HV(ctx);
-    translator_io_start(&ctx->base);
-    t = tcg_constant_i32(PPC_PM_DOZE);
-    gen_helper_pminsn(tcg_env, t);
-    /* Stop translation, as the CPU is supposed to sleep from now */
-    gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
-#endif /* defined(CONFIG_USER_ONLY) */
-    return true;
-}
-TRANS_FLAGS2(PM_ISA206, DOZE, do_doze);
-
-static bool do_nap(DisasContext *ctx, arg_NAP *a)
+/*
+ * Helper to handle DOZE, NAP, SLEEP, RVWINKLE & STOP. Since none of them use
+ * any arguments just use a placeholder arg_SLEEP.
+ */
+static bool do_sleep(DisasContext *ctx, arg_SLEEP *a, powerpc_pm_insn_t type)
 {
     REQUIRE_64BIT(ctx);
 
 #if defined(CONFIG_USER_ONLY)
     gen_priv_opc(ctx);
-#else
+#elif defined(TARGET_PPC64)
     TCGv_i32 t;
 
     REQUIRE_HV(ctx);
     translator_io_start(&ctx->base);
-    t = tcg_constant_i32(PPC_PM_NAP);
-    gen_helper_pminsn(tcg_env, t);
+    t = tcg_constant_i32(type);
+    gen_helper_PMINSN(tcg_env, t);
     /* Stop translation, as the CPU is supposed to sleep from now */
     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
-#endif /* defined(CONFIG_USER_ONLY) */
-    return true;
-}
-TRANS_FLAGS2(PM_ISA206, NAP, do_nap);
-
-static bool do_sleep(DisasContext *ctx, arg_SLEEP *a)
-{
-    REQUIRE_64BIT(ctx);
-
-#if defined(CONFIG_USER_ONLY)
-    gen_priv_opc(ctx);
 #else
-    TCGv_i32 t;
-
-    REQUIRE_HV(ctx);
-    translator_io_start(&ctx->base);
-    t = tcg_constant_i32(PPC_PM_SLEEP);
-    gen_helper_pminsn(tcg_env, t);
-    /* Stop translation, as the CPU is supposed to sleep from now */
-    gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
-#endif /* defined(CONFIG_USER_ONLY) */
-    return true;
-}
-TRANS_FLAGS2(PM_ISA206, SLEEP, do_sleep);
-
-static bool do_rvwinkle(DisasContext *ctx, arg_RVWINKLE *a)
-{
-    REQUIRE_64BIT(ctx);
-
-#if defined(CONFIG_USER_ONLY)
-    gen_priv_opc(ctx);
-#else
-    TCGv_i32 t;
-
-    REQUIRE_HV(ctx);
-    translator_io_start(&ctx->base);
-    t = tcg_constant_i32(PPC_PM_RVWINKLE);
-    gen_helper_pminsn(tcg_env, t);
-    /* Stop translation, as the CPU is supposed to sleep from now */
-    gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
-#endif /* defined(CONFIG_USER_ONLY) */
+    qemu_build_not_reached();
+#endif
     return true;
 }
-TRANS_FLAGS2(PM_ISA206, RVWINKLE, do_rvwinkle);
-
-static bool do_stop(DisasContext *ctx, arg_STOP *a)
-{
-    REQUIRE_64BIT(ctx);
 
-#if defined(CONFIG_USER_ONLY)
-    gen_priv_opc(ctx);
-#else
-    TCGv_i32 t;
-
-    REQUIRE_HV(ctx);
-    translator_io_start(&ctx->base);
-    t = tcg_constant_i32(PPC_PM_STOP);
-    gen_helper_pminsn(tcg_env, t);
-    /* Stop translation, as the CPU is supposed to sleep from now */
-    gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
-#endif /* defined(CONFIG_USER_ONLY) */
-    return true;
-}
-TRANS_FLAGS2(ISA300, STOP, do_stop);
+TRANS_FLAGS2(PM_ISA206, DOZE, do_sleep, PPC_PM_DOZE);
+TRANS_FLAGS2(PM_ISA206, NAP, do_sleep, PPC_PM_NAP);
+TRANS_FLAGS2(PM_ISA206, SLEEP, do_sleep, PPC_PM_SLEEP);
+TRANS_FLAGS2(PM_ISA206, RVWINKLE, do_sleep, PPC_PM_RVWINKLE);
+TRANS_FLAGS2(ISA300, STOP, do_sleep, PPC_PM_STOP);
-- 
2.52.0



  parent reply	other threads:[~2026-08-28  6:12 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-28  6:06 [PULL 00/41] ppc-for-11.2 queue Harsh Prateek Bora
2026-08-28  6:06 ` [PULL 01/41] linux-headers: Update to include KVM_CAP_PPC_COMPAT_CAPS Harsh Prateek Bora
2026-08-28  6:06 ` [PULL 02/41] target/ppc/kvm: Add support for querying host compatibility mode Harsh Prateek Bora
2026-08-28  6:06 ` [PULL 03/41] target/ppc/kvm: Use host compatibility mode for nested guests Harsh Prateek Bora
2026-08-28  6:06 ` [PULL 04/41] ppc/xive: Trigger the pending interrupt for a guest after migration Harsh Prateek Bora
2026-08-28  6:06 ` [PULL 05/41] target/ppc: Migrate extswsli to decodetree Harsh Prateek Bora
2026-08-28  6:06 ` [PULL 06/41] target/ppc: Migrate atomic loads " Harsh Prateek Bora
2026-08-28  6:06 ` [PULL 07/41] target/ppc: Convert cache instructions " Harsh Prateek Bora
2026-08-28  6:06 ` [PULL 08/41] target/ppc: Move vector merge " Harsh Prateek Bora
2026-08-28  6:06 ` [PULL 09/41] target/ppc: Move vector pack " Harsh Prateek Bora
2026-08-28  6:06 ` [PULL 10/41] target/ppc: Move st{b, h, w, d, q}cx " Harsh Prateek Bora
2026-08-28  6:06 ` [PULL 11/41] target/ppc: convert slw, srw instruction via decode spec Harsh Prateek Bora
2026-08-28  6:06 ` [PULL 12/41] target/ppc: convert sraw[i] " Harsh Prateek Bora
2026-08-28  6:06 ` [PULL 13/41] target/ppc: Convert mcrf to decode tree Harsh Prateek Bora
2026-08-28  6:06 ` [PULL 14/41] target/ppc: Move fixed-point Shift insns to decodetree Harsh Prateek Bora
2026-08-28  6:06 ` [PULL 15/41] target/ppc: Move fixed-point byte-reversal store " Harsh Prateek Bora
2026-08-28  6:06 ` [PULL 16/41] target/ppc: Move GPR atomic load/store instructions " Harsh Prateek Bora
2026-08-28  6:06 ` [PULL 17/41] target/ppc: Move isync instruction " Harsh Prateek Bora
2026-08-28  6:06 ` [PULL 18/41] target/ppc: Convert b{a, l, la} to decode tree Harsh Prateek Bora
2026-08-28  6:06 ` [PULL 19/41] target/ppc: move various conditional branch insns to decodetree Harsh Prateek Bora
2026-08-28  6:06 ` [PULL 20/41] target/ppc: Fix TRANS* macro variadic arguments handling Harsh Prateek Bora
2026-08-28  6:06 ` [PULL 21/41] target/ppc: Move wait instruction to decodetree Harsh Prateek Bora
2026-08-28  6:06 ` [PULL 22/41] target/ppc: Move sleep & friends " Harsh Prateek Bora
2026-08-28  6:06 ` Harsh Prateek Bora [this message]
2026-08-28  6:06 ` [PULL 24/41] target/ppc: Move Condition Register access instructions " Harsh Prateek Bora
2026-08-28  6:07 ` [PULL 25/41] target/ppc: Move Condition Register logical " Harsh Prateek Bora
2026-08-28  6:07 ` [PULL 26/41] target/ppc: make do_ea_calc_ra available for 32 bit builds Harsh Prateek Bora
2026-08-28  6:07 ` [PULL 27/41] target/ppc: Move Fixed-Point Load/Store String instructions to decodetree Harsh Prateek Bora
2026-08-28  6:07 ` [PULL 28/41] target/ppc: Move VMX integer arithmetic and BCD " Harsh Prateek Bora
2026-08-28  6:07 ` [PULL 29/41] target/ppc: Move rlwimi, rlwinm " Harsh Prateek Bora
2026-08-28  6:07 ` [PULL 30/41] target/ppc: Move lmw, stmw " Harsh Prateek Bora
2026-08-28  6:07 ` [PULL 31/41] target/ppc: Move mfmsr, mtmsr[d] " Harsh Prateek Bora
2026-08-28  6:07 ` [PULL 32/41] target/ppc: Move byte-reverse " Harsh Prateek Bora
2026-08-28  6:07 ` [PULL 33/41] target/ppc: Move system call and rfi " Harsh Prateek Bora
2026-08-28  6:07 ` [PULL 34/41] target/ppc: Replace PPC2_VSX207 flag with PPC2_ISA207 Harsh Prateek Bora
2026-08-28  6:07 ` [PULL 35/41] target/ppc: Use PPC2_ISA207 instead of PPC2_BCTAR_ISA207 Harsh Prateek Bora
2026-08-28  6:07 ` [PULL 36/41] target/ppc: Use PPC2_ISA207 instead of PPC2_LSQ_ISA207 Harsh Prateek Bora
2026-08-28  6:07 ` [PULL 37/41] target/ppc: Use PPC2_ISA207 instead of PPC2_ALTIVEC_207 Harsh Prateek Bora
2026-08-28  6:07 ` [PULL 38/41] target/ppc: Use PPC2_ISA207 instead of PPC2_ISA207S Harsh Prateek Bora
2026-08-28  6:07 ` [PULL 39/41] target/ppc: Reorder PPC2 flags Harsh Prateek Bora
2026-08-28  6:07 ` [PULL 40/41] target/ppc: Add ICBT support for ISA version 2.07 Harsh Prateek Bora
2026-08-28  6:07 ` [PULL 41/41] target/ppc: Add self as maintainer for PowerPC TCG CPUs Harsh Prateek Bora
2026-08-28 23:34 ` [PULL 00/41] ppc-for-11.2 queue Richard Henderson

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