[PATCH 0/2] hw/pci-bridge: Add x-speed and x-width properties to xio3130 ports

[PATCH 0/2] hw/pci-bridge: Add x-speed and x-width properties to xio3130 ports

[Cédric Le Goater]

Hello,

The xio3130-downstream and x3130-upstream devices lacks x-speed and
x-width device properties, making it impossible to configure PCIe link
speed/width when building PIX switch topologies for GPU/NIC passthrough.

Fix that and preserve migration compatibility with a 2.5GT/s x1 default.

Thanks,

C. 

Cédric Le Goater (2):
  hw/pci-bridge: Add x-speed and x-width properties to
    xio3130-downstream
  hw/pci-bridge: Add x-speed and x-width properties to x3130-upstream

 hw/core/machine.c                  |  4 ++++
 hw/pci-bridge/xio3130_downstream.c |  5 +++++
 hw/pci-bridge/xio3130_upstream.c   | 28 +++++++++++++++++++++++++++-
 3 files changed, 36 insertions(+), 1 deletion(-)

-- 
2.55.0

[PATCH 1/2] hw/pci-bridge: Add x-speed and x-width properties to xio3130-downstream

[Cédric Le Goater]

Default to 16GT/s x32 for new machine types and add compat entries
for <= 11.1 to preserve the old 2.5GT/s x1 behavior.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/4409
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 hw/core/machine.c                  | 2 ++
 hw/pci-bridge/xio3130_downstream.c | 5 +++++
 2 files changed, 7 insertions(+)

diff --git a/hw/core/machine.c b/hw/core/machine.c
index 8939ae16666c2d9454d93eccc5ca44e231b1ef6d..b702a61f7335a30841164279e73432bc238ee5e5 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -43,6 +43,8 @@
 GlobalProperty hw_compat_11_1[] = {
     { "sysbus-ehci-usb", "x-migrate-fetch-addr-64bit", "off" },
     { "pci-ehci-usb", "x-migrate-fetch-addr-64bit", "off" },
+    { "xio3130-downstream", "x-speed", "2_5" },
+    { "xio3130-downstream", "x-width", "1" },
 };
 const size_t hw_compat_11_1_len = G_N_ELEMENTS(hw_compat_11_1);
 
diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c
index 0c3fed3053b0e2b2ee2cf703c5f9e1f33ec1ff5b..0669223159a43f334d7ed46bec347de1bb8420ca 100644
--- a/hw/pci-bridge/xio3130_downstream.c
+++ b/hw/pci-bridge/xio3130_downstream.c
@@ -25,6 +25,7 @@
 #include "hw/pci/pcie.h"
 #include "hw/pci/pcie_port.h"
 #include "hw/core/qdev-properties.h"
+#include "hw/core/qdev-properties-system.h"
 #include "migration/vmstate.h"
 #include "qapi/error.h"
 #include "qemu/module.h"
@@ -137,6 +138,10 @@ static void xio3130_downstream_exitfn(PCIDevice *d)
 static const Property xio3130_downstream_props[] = {
     DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
                     QEMU_PCIE_SLTCAP_PCP_BITNR, true),
+    DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot,
+                                speed, PCIE_LINK_SPEED_16),
+    DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
+                                width, PCIE_LINK_WIDTH_32),
 };
 
 static const VMStateDescription vmstate_xio3130_downstream = {
-- 
2.55.0

[PATCH 2/2] hw/pci-bridge: Add x-speed and x-width properties to x3130-upstream

[Cédric Le Goater]

The x3130 upstream port is stuck at the 2.5GT/s x1 default. Following
the CXL upstream port pattern, introduce an XIO3130Upstream struct
wrapping PCIEPort with speed and width fields to be able to set them.

Default to 16GT/s x32 for new machine types and add compat entries
for <= 11.1 to preserve the old 2.5GT/s x1 behavior.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/4409
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 hw/core/machine.c                |  2 ++
 hw/pci-bridge/xio3130_upstream.c | 28 +++++++++++++++++++++++++++-
 2 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/hw/core/machine.c b/hw/core/machine.c
index b702a61f7335a30841164279e73432bc238ee5e5..3c98d62860d5ce058c4fbfdb86d2661f20e22b8f 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -45,6 +45,8 @@ GlobalProperty hw_compat_11_1[] = {
     { "pci-ehci-usb", "x-migrate-fetch-addr-64bit", "off" },
     { "xio3130-downstream", "x-speed", "2_5" },
     { "xio3130-downstream", "x-width", "1" },
+    { "x3130-upstream", "x-speed", "2_5" },
+    { "x3130-upstream", "x-width", "1" },
 };
 const size_t hw_compat_11_1_len = G_N_ELEMENTS(hw_compat_11_1);
 
diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c
index 40057b749bfd01bbd548b025607ef041b9feccc5..247994772c30373b7f3c6f9e72237dbed529ed98 100644
--- a/hw/pci-bridge/xio3130_upstream.c
+++ b/hw/pci-bridge/xio3130_upstream.c
@@ -24,9 +24,24 @@
 #include "hw/pci/msi.h"
 #include "hw/pci/pcie.h"
 #include "hw/pci/pcie_port.h"
+#include "hw/core/qdev-properties.h"
+#include "hw/core/qdev-properties-system.h"
 #include "migration/vmstate.h"
 #include "qemu/module.h"
 
+#define TYPE_XIO3130_UPSTREAM "x3130-upstream"
+
+OBJECT_DECLARE_SIMPLE_TYPE(XIO3130Upstream, XIO3130_UPSTREAM)
+
+struct XIO3130Upstream {
+    /*< private >*/
+    PCIEPort parent_obj;
+
+    /*< public >*/
+    PCIExpLinkSpeed speed;
+    PCIExpLinkWidth width;
+};
+
 #define PCI_DEVICE_ID_TI_XIO3130U       0x8232  /* upstream port */
 #define XIO3130_REVISION                0x2
 #define XIO3130_MSI_OFFSET              0x70
@@ -49,9 +64,11 @@ static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address,
 static void xio3130_upstream_reset(DeviceState *qdev)
 {
     PCIDevice *d = PCI_DEVICE(qdev);
+    XIO3130Upstream *u = XIO3130_UPSTREAM(qdev);
 
     pci_bridge_reset(qdev);
     pcie_cap_deverr_reset(d);
+    pcie_cap_fill_link_ep_usp(d, u->width, u->speed, false);
 }
 
 static void xio3130_upstream_realize(PCIDevice *d, Error **errp)
@@ -110,6 +127,13 @@ static void xio3130_upstream_exitfn(PCIDevice *d)
     pci_bridge_exitfn(d);
 }
 
+static const Property xio3130_upstream_props[] = {
+    DEFINE_PROP_PCIE_LINK_SPEED("x-speed", XIO3130Upstream,
+                                speed, PCIE_LINK_SPEED_16),
+    DEFINE_PROP_PCIE_LINK_WIDTH("x-width", XIO3130Upstream,
+                                width, PCIE_LINK_WIDTH_32),
+};
+
 static const VMStateDescription vmstate_xio3130_upstream = {
     .name = "xio3130-express-upstream-port",
     .priority = MIG_PRI_PCI_BUS,
@@ -138,11 +162,13 @@ static void xio3130_upstream_class_init(ObjectClass *klass, const void *data)
     dc->desc = "TI X3130 Upstream Port of PCI Express Switch";
     device_class_set_legacy_reset(dc, xio3130_upstream_reset);
     dc->vmsd = &vmstate_xio3130_upstream;
+    device_class_set_props(dc, xio3130_upstream_props);
 }
 
 static const TypeInfo xio3130_upstream_info = {
-    .name          = "x3130-upstream",
+    .name          = TYPE_XIO3130_UPSTREAM,
     .parent        = TYPE_PCIE_PORT,
+    .instance_size = sizeof(XIO3130Upstream),
     .class_init    = xio3130_upstream_class_init,
     .interfaces = (const InterfaceInfo[]) {
         { INTERFACE_PCIE_DEVICE },
-- 
2.55.0

Re: [PATCH 0/2] hw/pci-bridge: Add x-speed and x-width properties to xio3130 ports

[Cédric Le Goater]

On 9/15/26 09:25, Cédric Le Goater wrote:
> Hello,
> 
> The xio3130-downstream and x3130-upstream devices lacks x-speed and
> x-width device properties, making it impossible to configure PCIe link
> speed/width when building PIX switch topologies for GPU/NIC passthrough.
> 
> Fix that and preserve migration compatibility with a 2.5GT/s x1 default.
> 
> Thanks,
> 
> C.
> 
> Cédric Le Goater (2):
>    hw/pci-bridge: Add x-speed and x-width properties to
>      xio3130-downstream
>    hw/pci-bridge: Add x-speed and x-width properties to x3130-upstream
> 
>   hw/core/machine.c                  |  4 ++++
>   hw/pci-bridge/xio3130_downstream.c |  5 +++++
>   hw/pci-bridge/xio3130_upstream.c   | 28 +++++++++++++++++++++++++++-
>   3 files changed, 36 insertions(+), 1 deletion(-)


Reported-by: Boaz Ben Shabat <bbenshab@redhat.com>

Thanks,

C.

Re: [PATCH 0/2] hw/pci-bridge: Add x-speed and x-width properties to xio3130 ports

[Michael S. Tsirkin]

On Tue, Sep 15, 2026 at 09:25:05AM +0200, Cédric Le Goater wrote:
> Hello,
> 
> The xio3130-downstream and x3130-upstream devices lacks x-speed and
> x-width device properties, making it impossible to configure PCIe link
> speed/width when building PIX switch topologies for GPU/NIC passthrough.
> 
> Fix that and preserve migration compatibility with a 2.5GT/s x1 default.
> 
> Thanks,
> 
> C. 

Given they are clearly intended for users, time to rename to width/speed
everywhere?

> Cédric Le Goater (2):
>   hw/pci-bridge: Add x-speed and x-width properties to
>     xio3130-downstream
>   hw/pci-bridge: Add x-speed and x-width properties to x3130-upstream
> 
>  hw/core/machine.c                  |  4 ++++
>  hw/pci-bridge/xio3130_downstream.c |  5 +++++
>  hw/pci-bridge/xio3130_upstream.c   | 28 +++++++++++++++++++++++++++-
>  3 files changed, 36 insertions(+), 1 deletion(-)
> 
> -- 
> 2.55.0

Re: [PATCH 0/2] hw/pci-bridge: Add x-speed and x-width properties to xio3130 ports

[David Vrabel]

On 15/09/2026 11:01, Michael S. Tsirkin wrote:
> 
> On Tue, Sep 15, 2026 at 09:25:05AM +0200, Cédric Le Goater wrote:
>> Hello,
>>
>> The xio3130-downstream and x3130-upstream devices lacks x-speed and
>> x-width device properties, making it impossible to configure PCIe link
>> speed/width when building PIX switch topologies for GPU/NIC passthrough.
>>
>> Fix that and preserve migration compatibility with a 2.5GT/s x1 default.
>>
>> Thanks,
>>
>> C.
> 
> Given they are clearly intended for users, time to rename to width/speed
> everywhere?

A more comprehensive series (hw/pci-bridge: Configurable apparent 
bandwidth for the PCIe topology) is here:

https://patchew.org/QEMU/20260908155223.164787-1-david.vrabel@nutanix.com/

This adds new upstream and switch port devices with configurable 
speed/width and renames the options so they are non-experimental (but do 
not the open question about the usability of the speed option with the 
need to set 2.5 GT/s as the string "2_5").

I did consider adding options to the XIO3130 device but since the real 
hardware is Gen 1 only and does not support speeds/widths other 
2.5GT/s/1x I didn't consider it appropriate to claim these emulated 
ports are more capable than the real hardware.

David

Re: [PATCH 0/2] hw/pci-bridge: Add x-speed and x-width properties to xio3130 ports

[Michael S. Tsirkin]

On Tue, Sep 15, 2026 at 12:17:31PM +0100, David Vrabel wrote:
> On 15/09/2026 11:01, Michael S. Tsirkin wrote:
> > 
> > On Tue, Sep 15, 2026 at 09:25:05AM +0200, Cédric Le Goater wrote:
> > > Hello,
> > > 
> > > The xio3130-downstream and x3130-upstream devices lacks x-speed and
> > > x-width device properties, making it impossible to configure PCIe link
> > > speed/width when building PIX switch topologies for GPU/NIC passthrough.
> > > 
> > > Fix that and preserve migration compatibility with a 2.5GT/s x1 default.
> > > 
> > > Thanks,
> > > 
> > > C.
> > 
> > Given they are clearly intended for users, time to rename to width/speed
> > everywhere?
> 
> A more comprehensive series (hw/pci-bridge: Configurable apparent bandwidth
> for the PCIe topology) is here:
> 
> https://patchew.org/QEMU/20260908155223.164787-1-david.vrabel@nutanix.com/
> 
> This adds new upstream and switch port devices with configurable speed/width
> and renames the options so they are non-experimental (but do not the open
> question about the usability of the speed option with the need to set 2.5
> GT/s as the string "2_5").
> 
> I did consider adding options to the XIO3130 device but since the real
> hardware is Gen 1 only and does not support speeds/widths other 2.5GT/s/1x I
> didn't consider it appropriate to claim these emulated ports are more
> capable than the real hardware.
> 
> David

Right that makes more sense to me.  Cédric what do you think?

-- 
MST

Re: [PATCH 0/2] hw/pci-bridge: Add x-speed and x-width properties to xio3130 ports

[Cédric Le Goater]

On 9/15/26 16:22, Michael S. Tsirkin wrote:
> On Tue, Sep 15, 2026 at 12:17:31PM +0100, David Vrabel wrote:
>> On 15/09/2026 11:01, Michael S. Tsirkin wrote:
>>>
>>> On Tue, Sep 15, 2026 at 09:25:05AM +0200, Cédric Le Goater wrote:
>>>> Hello,
>>>>
>>>> The xio3130-downstream and x3130-upstream devices lacks x-speed and
>>>> x-width device properties, making it impossible to configure PCIe link
>>>> speed/width when building PIX switch topologies for GPU/NIC passthrough.
>>>>
>>>> Fix that and preserve migration compatibility with a 2.5GT/s x1 default.
>>>>
>>>> Thanks,
>>>>
>>>> C.
>>>
>>> Given they are clearly intended for users, time to rename to width/speed
>>> everywhere?
>>
>> A more comprehensive series (hw/pci-bridge: Configurable apparent bandwidth
>> for the PCIe topology) is here:
>>
>> https://patchew.org/QEMU/20260908155223.164787-1-david.vrabel@nutanix.com/
>>
>> This adds new upstream and switch port devices with configurable speed/width
>> and renames the options so they are non-experimental (but do not the open
>> question about the usability of the speed option with the need to set 2.5
>> GT/s as the string "2_5").
>>
>> I did consider adding options to the XIO3130 device but since the real
>> hardware is Gen 1 only and does not support speeds/widths other 2.5GT/s/1x I
>> didn't consider it appropriate to claim these emulated ports are more
>> capable than the real hardware.
>>
>> David
> 
> Right that makes more sense to me.  Cédric what do you think?

I didn't know about it.

Regarding HW accuracy, I agree XIO3130 being Gen 1, the new speed
and link are inaccurate and this could confuse some tools checking
vendor/device ID.

Regarding the code size, user facing changes, existing topology,
migration, etc, boosting XIO3130 capabilities is safer. What is
worrisome is the downstream impact. backports will be a problem.
That said I didn't check.

David's proposal is preferable, as the device doesn't pretend
to be real HW and should be pursued for upstream. Mine would be
more a fallback solution for downstream. Hopefully not,

Cheers,

C.

Re: [PATCH 0/2] hw/pci-bridge: Add x-speed and x-width properties to xio3130 ports

[Michael S. Tsirkin]

On Tue, Sep 15, 2026 at 05:36:16PM +0200, Cédric Le Goater wrote:
> On 9/15/26 16:22, Michael S. Tsirkin wrote:
> > On Tue, Sep 15, 2026 at 12:17:31PM +0100, David Vrabel wrote:
> > > On 15/09/2026 11:01, Michael S. Tsirkin wrote:
> > > > 
> > > > On Tue, Sep 15, 2026 at 09:25:05AM +0200, Cédric Le Goater wrote:
> > > > > Hello,
> > > > > 
> > > > > The xio3130-downstream and x3130-upstream devices lacks x-speed and
> > > > > x-width device properties, making it impossible to configure PCIe link
> > > > > speed/width when building PIX switch topologies for GPU/NIC passthrough.
> > > > > 
> > > > > Fix that and preserve migration compatibility with a 2.5GT/s x1 default.
> > > > > 
> > > > > Thanks,
> > > > > 
> > > > > C.
> > > > 
> > > > Given they are clearly intended for users, time to rename to width/speed
> > > > everywhere?
> > > 
> > > A more comprehensive series (hw/pci-bridge: Configurable apparent bandwidth
> > > for the PCIe topology) is here:
> > > 
> > > https://patchew.org/QEMU/20260908155223.164787-1-david.vrabel@nutanix.com/
> > > 
> > > This adds new upstream and switch port devices with configurable speed/width
> > > and renames the options so they are non-experimental (but do not the open
> > > question about the usability of the speed option with the need to set 2.5
> > > GT/s as the string "2_5").
> > > 
> > > I did consider adding options to the XIO3130 device but since the real
> > > hardware is Gen 1 only and does not support speeds/widths other 2.5GT/s/1x I
> > > didn't consider it appropriate to claim these emulated ports are more
> > > capable than the real hardware.
> > > 
> > > David
> > 
> > Right that makes more sense to me.  Cédric what do you think?
> 
> I didn't know about it.
> 
> Regarding HW accuracy, I agree XIO3130 being Gen 1, the new speed
> and link are inaccurate and this could confuse some tools checking
> vendor/device ID.
> 
> Regarding the code size, user facing changes, existing topology,
> migration, etc, boosting XIO3130 capabilities is safer. What is
> worrisome is the downstream impact. backports will be a problem.
> That said I didn't check.
> 
> David's proposal is preferable, as the device doesn't pretend
> to be real HW and should be pursued for upstream. Mine would be
> more a fallback solution for downstream. Hopefully not,
> 
> Cheers,
> 
> C.

I don't know what the big deal is. new hardware is easy to add to
libvirt. I just coded it up quickly it's like 30LOC, excluding tests.
Pls check that option.

-- 
MST

Re: [PATCH 0/2] hw/pci-bridge: Add x-speed and x-width properties to xio3130 ports

[David Vrabel]

On 15/09/2026 17:40, Michael S. Tsirkin wrote:
> 
> I don't know what the big deal is. new hardware is easy to add to
> libvirt. I just coded it up quickly it's like 30LOC, excluding tests.
> Pls check that option.
>

I do have a libvirt series as well.

https://patchew.org/Libvirt/20260915134615.2262856-1-david.vrabel@nutanix.com/

David