[PATCH v1 0/9] hw/arm/aspeed: Add AST1080 SoC and EVB support

[PATCH v1 0/9] hw/arm/aspeed: Add AST1080 SoC and EVB support

[Jamin Lin]

This series adds support for the AST1080 Platform Root of Trust SoC
and its evaluation board.

This series depends on:

[v1,00/14] hw/arm/aspeed: Add AST1040 FMC/SPI controllers and unimplemented devices
https://patchwork.kernel.org/project/qemu-devel/cover/20261015055642.106204-1-jamin_lin@aspeedtech.com/

and is based on the aspeed-next branch:
https://github.com/legoater/qemu/commits/aspeed-next

The AST1080 shares most of its design with the AST1040, so the AST1040
init and realize code is first split into common functions. The
AST1080 SoC is then added with its own unimplemented devices (QSPI
filters and I2C filter).

v1
 1. Add common init function for AST1040/AST1080 SoCs
 2. Add common realize function for AST1040/AST1080 SoCs
 3. Add AST1080 SOC and EVB machine
 4. Add AST1080 functional test.
 
Jamin Lin (9):
  hw/arm/aspeed_ast1040: Add common init function for AST1040/AST1080
    SoCs
  hw/arm/aspeed_ast1040: Add common realize function for AST1040/AST1080
    SoCs
  hw/misc/aspeed_scu: Add AST1080 A0 silicon revision definition
  hw/arm/aspeed_ast1040: Add AST1080 SoC support
  hw/arm/aspeed_ast1040: Add AST1080 QSPI filters as unimplemented
    device
  hw/arm/aspeed_ast1040: Add AST1080 I2C filter as an unimplemented
    device
  hw/arm/aspeed_ast1040_evb: Add AST1080 EVB machine support
  tests/functional/arm/aspeed: Add AST1080 test with ASPEED MCU FW Hub
    v01.00
  docs/system/arm/aspeed: Add AST1080 Platform Root of Trust evaluation
    board

 docs/system/arm/aspeed.rst                  |   8 +-
 include/hw/misc/aspeed_scu.h                |   1 +
 hw/arm/aspeed_ast1040.c                     | 154 +++++++++++++++-----
 hw/arm/aspeed_ast1040_evb.c                 |  23 +++
 hw/misc/aspeed_scu.c                        |   1 +
 tests/functional/arm/meson.build            |   1 +
 tests/functional/arm/test_aspeed_ast1080.py |  37 +++++
 7 files changed, 186 insertions(+), 39 deletions(-)
 create mode 100644 tests/functional/arm/test_aspeed_ast1080.py

-- 
2.53.0

[PATCH v1 1/9] hw/arm/aspeed_ast1040: Add common init function for AST1040/AST1080 SoCs

[Jamin Lin]

AST1040 and AST1080 are the next-generation SoCs of AST1030 and AST1060,
respectively.

The AST1030 and AST1060 SoCs share common initialization through
aspeed_soc_ast10x0_init(). Similarly, introduce
aspeed_soc_ast10x0_g2_init() to provide common initialization for the
AST1040 and AST1080 SoCs.

Move the shared AST1040 initialization into the new common function so
that it can be reused when adding AST1080 support. The PECI and eSPI
controllers are only available on the AST1040, so their initialization
is kept in aspeed_soc_ast1040_init().

No functional changes.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/arm/aspeed_ast1040.c | 36 +++++++++++++++++++++++++-----------
 1 file changed, 25 insertions(+), 11 deletions(-)

diff --git a/hw/arm/aspeed_ast1040.c b/hw/arm/aspeed_ast1040.c
index 74a1097bd7..5d2713e8bb 100644
--- a/hw/arm/aspeed_ast1040.c
+++ b/hw/arm/aspeed_ast1040.c
@@ -81,19 +81,23 @@ static const int aspeed_soc_ast1040_irqmap[] = {
     [ASPEED_DEV_PECI]      = 164,
 };
 
-static const UnimplementedDeviceConfig aspeed_soc_ast1040_unimp_devs[] = {
-    { "pwm", "aspeed.pwm", 0x740C0000, 0x10000, -1000 },
-    { "espi", "aspeed.espi", 0x74C05000, 0x1000, -1000 },
-    { "udc", "aspeed.udc", 0x74120000, 0x4000, -1000 },
-    { "jtag[0]", "aspeed.jtag0", 0x74C01000, 0x100, -1000 },
-    { "jtag[1]", "aspeed.jtag1", 0x74C09000, 0x100, -1000 },
+static const UnimplementedDeviceConfig aspeed_soc_ast10x0_g2_unimp_devs[] = {
     { "fmc-filter",  "aspeed.fmc-filter", 0x74000400, 0x1000, -1000 },
     { "spi0-filter", "aspeed.spi0-filter", 0x74010400, 0x1000, -1000 },
     { "spi1-filter", "aspeed.spi1-filter", 0x74020400, 0x1000, -1000 },
+    { "pwm", "aspeed.pwm", 0x740C0000, 0x10000, -1000 },
+    { "udc", "aspeed.udc", 0x74120000, 0x4000, -1000 },
+    { "caliptra", "aspeed.caliptra", 0x74200000, 0x100000, -1000 },
+    { "jtag[0]", "aspeed.jtag0", 0x74C01000, 0x100, -1000 },
     { "otp", "aspeed.otp", 0x74C07000, 0x800, -1000 },
-    { "atc", "aspeed.atc", 0x74C35000, 0x100, -1000 },
+    { "jtag[1]", "aspeed.jtag1", 0x74C09000, 0x100, -1000 },
     { "i3c", "aspeed.i3c", 0x74C20000, 0x8000, -1000 },
-    { "caliptra", "aspeed.caliptra", 0x74200000, 0x100000, -1000 },
+    { "atc", "aspeed.atc", 0x74C35000, 0x100, -1000 },
+    { }
+};
+
+static const UnimplementedDeviceConfig aspeed_soc_ast1040_unimp_devs[] = {
+    { "espi", "aspeed.espi", 0x74C05000, 0x1000, -1000 },
     { }
 };
 
@@ -105,7 +109,7 @@ static qemu_irq aspeed_soc_ast1040_get_irq(AspeedSoCState *s, int dev)
     return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
 }
 
-static void aspeed_soc_ast1040_init(Object *obj)
+static void aspeed_soc_ast10x0_g2_init(Object *obj)
 {
     Aspeed10x0SoCState *a = ASPEED10X0_SOC(obj);
     AspeedSoCState *s = ASPEED_SOC(obj);
@@ -117,7 +121,7 @@ static void aspeed_soc_ast1040_init(Object *obj)
 
     s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
 
-    /* AST1040 uses the AST2700 SCUIO model */
+    /* AST10x0 G2 uses the AST2700 SCUIO model */
     object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCUIO);
     qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
 
@@ -129,7 +133,6 @@ static void aspeed_soc_ast1040_init(Object *obj)
     }
 
     object_initialize_child(obj, "adc", &s->adc, TYPE_ASPEED_2700_ADC);
-    object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
     object_initialize_child(obj, "gpio", &s->gpio, "aspeed.gpio-ast2700");
     for (i = 0; i < sc->sgpio_num; i++) {
         object_initialize_child(obj, "sgpio[*]", &s->sgpiom[i],
@@ -150,6 +153,15 @@ static void aspeed_soc_ast1040_init(Object *obj)
     }
 }
 
+static void aspeed_soc_ast1040_init(Object *obj)
+{
+    AspeedSoCState *s = ASPEED_SOC(obj);
+
+    aspeed_soc_ast10x0_g2_init(obj);
+
+    object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
+}
+
 static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
 {
     Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
@@ -313,6 +325,8 @@ static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
     }
 
     /* Unimplemented devices */
+    create_unimplemented_devices(OBJECT(s), s->memory,
+                                 aspeed_soc_ast10x0_g2_unimp_devs);
     create_unimplemented_devices(OBJECT(s), s->memory, sc->unimp_devs);
 }
 
-- 
2.53.0

[PATCH v1 2/9] hw/arm/aspeed_ast1040: Add common realize function for AST1040/AST1080 SoCs

[Jamin Lin]

AST1040 and AST1080 are the next-generation SoCs of AST1030 and AST1060,
respectively.

The AST1030 and AST1060 SoCs share common realization through
aspeed_soc_ast10x0_realize(). Similarly, introduce
aspeed_soc_ast10x0_g2_realize() to provide common realization for the
AST1040 and AST1080 SoCs.

Move the shared AST1040 realization into the new common function so that
it can be reused when adding AST1080 support. The PECI and eSPI
controllers are only available on the AST1040, so their realization is
kept in aspeed_soc_ast1040_realize().

No functional changes.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/arm/aspeed_ast1040.c | 62 ++++++++++++++++++++++++-----------------
 1 file changed, 37 insertions(+), 25 deletions(-)

diff --git a/hw/arm/aspeed_ast1040.c b/hw/arm/aspeed_ast1040.c
index 5d2713e8bb..28abbe7010 100644
--- a/hw/arm/aspeed_ast1040.c
+++ b/hw/arm/aspeed_ast1040.c
@@ -162,10 +162,9 @@ static void aspeed_soc_ast1040_init(Object *obj)
     object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
 }
 
-static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
+static bool aspeed_soc_ast10x0_g2_realize(Aspeed10x0SoCState *a, Error **errp)
 {
-    Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
-    AspeedSoCState *s = ASPEED_SOC(dev_soc);
+    AspeedSoCState *s = ASPEED_SOC(a);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     g_autofree char *hyperram_name = NULL;
     g_autofree char *sram_name = NULL;
@@ -176,10 +175,10 @@ static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
 
     if (!clock_has_source(s->sysclk)) {
         error_setg(errp, "sysclk clock must be wired up by the board code");
-        return;
+        return false;
     }
 
-    /* AST1040 CPU Core */
+    /* AST10x0 G2 CPU Core */
     armv7m = DEVICE(&a->armv7m);
     qdev_prop_set_uint32(armv7m, "num-irq", 256);
     qdev_prop_set_string(armv7m, "cpu-type",
@@ -196,7 +195,7 @@ static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
                            sc->sram_size[0], &err);
     if (err) {
         error_propagate(errp, err);
-        return;
+        return false;
     }
     memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM0],
                                 &s->sram[0]);
@@ -208,14 +207,14 @@ static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
                            sc->sram_size[1], &err);
     if (err) {
         error_propagate(errp, err);
-        return;
+        return false;
     }
     memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM1],
                                 &s->sram[1]);
 
     /* SCU */
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
-        return;
+        return false;
     }
     aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0,
                     sc->memmap[ASPEED_DEV_SCU]);
@@ -224,7 +223,7 @@ static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
     for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
         if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
                                      sc->memmap[uart], errp)) {
-            return;
+            return false;
         }
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
                            aspeed_soc_ast1040_get_irq(s, uart));
@@ -232,25 +231,16 @@ static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
 
     /* ADC */
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
-        return;
+        return false;
     }
     aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0,
                     sc->memmap[ASPEED_DEV_ADC]);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
                        aspeed_soc_ast1040_get_irq(s, ASPEED_DEV_ADC));
 
-    /* PECI */
-    if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
-        return;
-    }
-    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0,
-                    sc->memmap[ASPEED_DEV_PECI]);
-    sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
-                       aspeed_soc_ast1040_get_irq(s, ASPEED_DEV_PECI));
-
     /* GPIO */
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
-        return;
+        return false;
     }
     aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0,
                     sc->memmap[ASPEED_DEV_GPIO]);
@@ -260,7 +250,7 @@ static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
     /* SGPIO */
     for (i = 0; i < sc->sgpio_num; i++) {
         if (!sysbus_realize(SYS_BUS_DEVICE(&s->sgpiom[i]), errp)) {
-            return;
+            return false;
         }
         aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sgpiom[i]), 0,
                         sc->memmap[ASPEED_DEV_SGPIOM0 + i]);
@@ -272,7 +262,7 @@ static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
     object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(&s->sram[1]),
                              &error_abort);
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
-        return;
+        return false;
     }
     aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i2c), 0,
                     sc->memmap[ASPEED_DEV_I2C]);
@@ -291,7 +281,7 @@ static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
         object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
                                  &error_abort);
         if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
-            return;
+            return false;
         }
         aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
     }
@@ -300,7 +290,7 @@ static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
     object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram[1]),
             &error_abort);
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
-        return;
+        return false;
     }
     aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 0,
                     sc->memmap[ASPEED_DEV_FMC]);
@@ -314,7 +304,7 @@ static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
         object_property_set_link(OBJECT(&s->spi[i]), "dram",
                                  OBJECT(&s->sram[1]), &error_abort);
         if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
-            return;
+            return false;
         }
         aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 0,
                         sc->memmap[ASPEED_DEV_SPI0 + i]);
@@ -328,6 +318,28 @@ static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
     create_unimplemented_devices(OBJECT(s), s->memory,
                                  aspeed_soc_ast10x0_g2_unimp_devs);
     create_unimplemented_devices(OBJECT(s), s->memory, sc->unimp_devs);
+
+    return true;
+}
+
+static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
+{
+    Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
+    AspeedSoCState *s = ASPEED_SOC(a);
+    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+
+    if (!aspeed_soc_ast10x0_g2_realize(a, errp)) {
+        return;
+    }
+
+    /* PECI */
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
+        return;
+    }
+    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0,
+                    sc->memmap[ASPEED_DEV_PECI]);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
+                       aspeed_soc_ast1040_get_irq(s, ASPEED_DEV_PECI));
 }
 
 static void aspeed_soc_ast1040_class_init(ObjectClass *klass, const void *data)
-- 
2.53.0

[PATCH v1 3/9] hw/misc/aspeed_scu: Add AST1080 A0 silicon revision definition

[Jamin Lin]

Add a new silicon revision constant AST1080_A0_SILICON_REV for the
AST1080 SoC. This allows the SCU model and related SoC layers to
identify and handle AST1080 A0 revision properly in the same way as
other Aspeed SoC families.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 include/hw/misc/aspeed_scu.h | 1 +
 hw/misc/aspeed_scu.c         | 1 +
 2 files changed, 2 insertions(+)

diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 6482038f12..a7014e43f2 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -52,6 +52,7 @@ struct Aspeed2700SCUState {
 #define AST1030_A1_SILICON_REV   0x80010000U
 #define AST1060_A2_SILICON_REV   0xA0030000U
 #define AST1040_A0_SILICON_REV   0x80000000U
+#define AST1080_A0_SILICON_REV   0xA0000100U
 #define AST2700_A1_SILICON_REV   0x06010103U
 #define AST2700_A2_SILICON_REV   0x06020103U
 
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 77f9af2ae5..df26dd0ef4 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -572,6 +572,7 @@ static uint32_t aspeed_silicon_revs[] = {
     AST2700_A1_SILICON_REV,
     AST2700_A2_SILICON_REV,
     AST1040_A0_SILICON_REV,
+    AST1080_A0_SILICON_REV,
 };
 
 bool is_supported_silicon_rev(uint32_t silicon_rev)
-- 
2.53.0

[PATCH v1 4/9] hw/arm/aspeed_ast1040: Add AST1080 SoC support

[Jamin Lin]

Add initial support for the Aspeed AST1080 SoC. The AST1080 reuses most
of the AST1040 peripheral device models, as the two SoCs share nearly
the same controllers including WDT, SCU, GPIO, SGPIO, ADC, I2C, FMC,
and SPI.

The common initialization and realization functions,
aspeed_soc_ast10x0_g2_init() and aspeed_soc_ast10x0_g2_realize(),
introduced in the previous patches are reused, so AST1080 can
instantiate the existing AST1040 device models without defining
duplicate device types.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/arm/aspeed_ast1040.c | 47 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/hw/arm/aspeed_ast1040.c b/hw/arm/aspeed_ast1040.c
index 28abbe7010..c641f84fbe 100644
--- a/hw/arm/aspeed_ast1040.c
+++ b/hw/arm/aspeed_ast1040.c
@@ -162,6 +162,11 @@ static void aspeed_soc_ast1040_init(Object *obj)
     object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
 }
 
+static void aspeed_soc_ast1080_init(Object *obj)
+{
+    aspeed_soc_ast10x0_g2_init(obj);
+}
+
 static bool aspeed_soc_ast10x0_g2_realize(Aspeed10x0SoCState *a, Error **errp)
 {
     AspeedSoCState *s = ASPEED_SOC(a);
@@ -342,6 +347,15 @@ static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
                        aspeed_soc_ast1040_get_irq(s, ASPEED_DEV_PECI));
 }
 
+static void aspeed_soc_ast1080_realize(DeviceState *dev_soc, Error **errp)
+{
+    Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
+
+    if (!aspeed_soc_ast10x0_g2_realize(a, errp)) {
+        return;
+    }
+}
+
 static void aspeed_soc_ast1040_class_init(ObjectClass *klass, const void *data)
 {
     static const char * const valid_cpu_types[] = {
@@ -370,12 +384,45 @@ static void aspeed_soc_ast1040_class_init(ObjectClass *klass, const void *data)
     sc->num_cpus        = 1;
 }
 
+static void aspeed_soc_ast1080_class_init(ObjectClass *klass, const void *data)
+{
+    static const char * const valid_cpu_types[] = {
+        ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
+        NULL
+    };
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
+
+    /* Reason: The Aspeed SoC can only be instantiated from a board */
+    dc->user_creatable = false;
+    dc->realize = aspeed_soc_ast1080_realize;
+
+    sc->valid_cpu_types = valid_cpu_types;
+    sc->silicon_rev     = AST1080_A0_SILICON_REV;
+    sc->sram_size[0]    = 128 * KiB;
+    sc->sram_size[1]    = 16 * MiB; /* Hyper RAM */
+    sc->uarts_num       = 13;
+    sc->sgpio_num       = 1;
+    sc->wdts_num        = 8;
+    sc->spis_num        = 2;
+    sc->uarts_base      = ASPEED_DEV_UART0;
+    sc->irqmap          = aspeed_soc_ast1040_irqmap;
+    sc->memmap          = aspeed_soc_ast1040_memmap;
+    sc->num_cpus        = 1;
+}
+
 static const TypeInfo aspeed_soc_ast1040_types[] = {
     {
         .name           = "ast1040-a0",
         .parent         = TYPE_ASPEED10X0_SOC,
         .instance_init  = aspeed_soc_ast1040_init,
         .class_init     = aspeed_soc_ast1040_class_init,
+    },
+    {
+        .name           = "ast1080-a0",
+        .parent         = TYPE_ASPEED10X0_SOC,
+        .instance_init  = aspeed_soc_ast1080_init,
+        .class_init     = aspeed_soc_ast1080_class_init,
     }
 };
 
-- 
2.53.0

[PATCH v1 5/9] hw/arm/aspeed_ast1040: Add AST1080 QSPI filters as unimplemented device

[Jamin Lin]

The AST1080 provides three QSPI Filter Controllers (SPI monitors) at
the following addresses:

  QSPI filter #0: 0x74c15000
  QSPI filter #1: 0x74c16000
  QSPI filter #2: 0x74c17000

These controllers are only available on the AST1080. The AST1040 does
not have them, so they are added to the AST1080 specific init and
realize functions instead of the common AST10x0 G2 ones.

The controllers are not modeled yet. Add the register regions as
unimplemented devices to reflect the AST1080 memory map.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/arm/aspeed_ast1040.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/hw/arm/aspeed_ast1040.c b/hw/arm/aspeed_ast1040.c
index c641f84fbe..e5c8d15dcb 100644
--- a/hw/arm/aspeed_ast1040.c
+++ b/hw/arm/aspeed_ast1040.c
@@ -101,6 +101,13 @@ static const UnimplementedDeviceConfig aspeed_soc_ast1040_unimp_devs[] = {
     { }
 };
 
+static const UnimplementedDeviceConfig aspeed_soc_ast1080_unimp_devs[] = {
+    { "spim0", "aspeed.spim0", 0x74C15000, 0x1000, -1000 },
+    { "spim1", "aspeed.spim1", 0x74C16000, 0x1000, -1000 },
+    { "spim2", "aspeed.spim2", 0x74C17000, 0x1000, -1000 },
+    { }
+};
+
 static qemu_irq aspeed_soc_ast1040_get_irq(AspeedSoCState *s, int dev)
 {
     Aspeed10x0SoCState *a = ASPEED10X0_SOC(s);
@@ -408,6 +415,7 @@ static void aspeed_soc_ast1080_class_init(ObjectClass *klass, const void *data)
     sc->uarts_base      = ASPEED_DEV_UART0;
     sc->irqmap          = aspeed_soc_ast1040_irqmap;
     sc->memmap          = aspeed_soc_ast1040_memmap;
+    sc->unimp_devs      = aspeed_soc_ast1080_unimp_devs;
     sc->num_cpus        = 1;
 }
 
-- 
2.53.0

[PATCH v1 6/9] hw/arm/aspeed_ast1040: Add AST1080 I2C filter as an unimplemented device

[Jamin Lin]

The AST1080 provides an SMBus Filter Controller (I2C filter) at
0x74c14000, but the controller is not modeled yet.

This controller is only available on the AST1080. The AST1040 does not
have it, so it is added to the AST1080 specific init and realize
functions instead of the common AST10x0 G2 ones.

Add the register region as an unimplemented device to reflect the
AST1080 memory map.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/arm/aspeed_ast1040.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/arm/aspeed_ast1040.c b/hw/arm/aspeed_ast1040.c
index e5c8d15dcb..56ef6b1268 100644
--- a/hw/arm/aspeed_ast1040.c
+++ b/hw/arm/aspeed_ast1040.c
@@ -102,6 +102,7 @@ static const UnimplementedDeviceConfig aspeed_soc_ast1040_unimp_devs[] = {
 };
 
 static const UnimplementedDeviceConfig aspeed_soc_ast1080_unimp_devs[] = {
+    { "i2c-filter", "aspeed.i2c-filter", 0x74C14000, 0x1000, -1000 },
     { "spim0", "aspeed.spim0", 0x74C15000, 0x1000, -1000 },
     { "spim1", "aspeed.spim1", 0x74C16000, 0x1000, -1000 },
     { "spim2", "aspeed.spim2", 0x74C17000, 0x1000, -1000 },
-- 
2.53.0

[PATCH v1 7/9] hw/arm/aspeed_ast1040_evb: Add AST1080 EVB machine support

[Jamin Lin]

Add a new machine definition ast1080-evb to support the Aspeed AST1080
evaluation board. The new EVB reuses the same BIC framework used by
AST1040, as both SoCs share the same core peripherals and controller
designs.

The AST1080 EVB machine initializes the ast1080-a0 SoC.
This enables QEMU to boot and emulate firmware images for AST1080-based
platforms.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/arm/aspeed_ast1040_evb.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/hw/arm/aspeed_ast1040_evb.c b/hw/arm/aspeed_ast1040_evb.c
index 486f0f6a1b..9da8021653 100644
--- a/hw/arm/aspeed_ast1040_evb.c
+++ b/hw/arm/aspeed_ast1040_evb.c
@@ -75,11 +75,34 @@ static void aspeed_machine_ast1040_evb_class_init(ObjectClass *oc,
     aspeed_machine_class_init_cpus_defaults(mc);
 }
 
+static void aspeed_machine_ast1080_evb_class_init(ObjectClass *oc,
+                                                  const void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+    AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+    mc->desc = "Aspeed AST1080 Platform Root of Trust (Cortex-M4)";
+    amc->soc_name = "ast1080-a0";
+    amc->hw_strap1 = 0;
+    amc->hw_strap2 = 0;
+    mc->init = aspeed_bic_machine_init;
+    amc->i2c_init = ast1040_evb_i2c_init;
+    mc->default_ram_size = 0;
+    amc->macs_mask = 0;
+    amc->uart_default = ASPEED_DEV_UART12;
+    aspeed_machine_class_init_cpus_defaults(mc);
+}
+
 static const TypeInfo aspeed_ast1040_evb_types[] = {
     {
         .name           = MACHINE_TYPE_NAME("ast1040-evb"),
         .parent         = TYPE_ASPEED_MACHINE,
         .class_init     = aspeed_machine_ast1040_evb_class_init,
+    },
+    {
+        .name           = MACHINE_TYPE_NAME("ast1080-evb"),
+        .parent         = TYPE_ASPEED_MACHINE,
+        .class_init     = aspeed_machine_ast1080_evb_class_init,
     }
 };
 
-- 
2.53.0

[PATCH v1 8/9] tests/functional/arm/aspeed: Add AST1080 test with ASPEED MCU FW Hub v01.00

[Jamin Lin]

Add a functional test for the ASPEED AST1080 EVB using the
Zephyr firmware from ASPEED MCU FW Hub v01.00.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 tests/functional/arm/meson.build            |  1 +
 tests/functional/arm/test_aspeed_ast1080.py | 37 +++++++++++++++++++++
 2 files changed, 38 insertions(+)
 create mode 100644 tests/functional/arm/test_aspeed_ast1080.py

diff --git a/tests/functional/arm/meson.build b/tests/functional/arm/meson.build
index 61b00932db..ca04fd9dc0 100644
--- a/tests/functional/arm/meson.build
+++ b/tests/functional/arm/meson.build
@@ -36,6 +36,7 @@ tests_arm_system_thorough = [
   'aspeed_ast1030',
   'aspeed_ast1040',
   'aspeed_ast1060',
+  'aspeed_ast1080',
   'aspeed_palmetto',
   'aspeed_romulus',
   'aspeed_witherspoon',
diff --git a/tests/functional/arm/test_aspeed_ast1080.py b/tests/functional/arm/test_aspeed_ast1080.py
new file mode 100644
index 0000000000..76f3cc0983
--- /dev/null
+++ b/tests/functional/arm/test_aspeed_ast1080.py
@@ -0,0 +1,37 @@
+#!/usr/bin/env python3
+#
+# Functional test that boots the ASPEED SoCs with firmware
+#
+# Copyright (C) 2026 ASPEED Technology Inc
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+from aspeed import AspeedTest
+from qemu_test import Asset, exec_command_and_wait_for_pattern
+
+
+class AST1080Machine(AspeedTest):
+
+    ASSET_ASPEED_AST1080_EVB_01_00 = Asset(
+        ('https://github.com/AspeedTech-BMC'
+         '/aspeed-mcu-fw-hub/releases/download/v01.00'
+         '/ast1080a0-evb-v01.00.tar.gz'),
+         '7c8a95bc51945d70591b20f1a22f8fffebc2b164e6fda47f73ff67f37bed8d87')
+
+    def test_arm_ast1080_zephyros(self):
+        self.set_machine('ast1080-evb')
+
+        kernel_name = ('ast1080a0-evb-v01.00/ast1080/ast1080a0/evb/'
+                       'zephyr-shell-module.bin')
+        kernel_file = self.archive_extract(
+            self.ASSET_ASPEED_AST1080_EVB_01_00, member=kernel_name)
+
+        self.vm.set_console()
+        self.vm.add_args('-kernel', kernel_file, '-nographic')
+        self.vm.launch()
+        self.wait_for_console_pattern("uart:~$")
+        exec_command_and_wait_for_pattern(self, "help",
+                                          "Available commands")
+
+if __name__ == '__main__':
+    AspeedTest.main()
-- 
2.53.0

[PATCH v1 9/9] docs/system/arm/aspeed: Add AST1080 Platform Root of Trust evaluation board

[Jamin Lin]

Update the Aspeed AST10x0 documentation to include the AST1080
evaluation board.

The documentation now describes:
- AST1080 as a Platform Root of Trust processor
- AST1080 Cortex-M4F CPU frequency running at 400 MHz

Also add the ast1080-evb machine entry to the supported AST10x0 SoC
based machine list.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 docs/system/arm/aspeed.rst | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 2d51ceeb84..be74ee39fa 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -441,8 +441,8 @@ Use ``tio`` or another terminal emulator to connect to the consoles:
    $ tio /dev/pts/57
 
 
-Aspeed Bridge IC and Platform Root of Trust processor family boards (``ast1030-evb``, ``ast1040-evb``, ``ast1060-evb``)
-=======================================================================================================================
+Aspeed Bridge IC and Platform Root of Trust processor family boards (``ast1030-evb``, ``ast1040-evb``, ``ast1060-evb``, ``ast1080-evb``)
+========================================================================================================================================
 
 The QEMU Aspeed machines model Bridge ICs and Platform Root of Trust processors
 of various Aspeed evaluation boards. They are based on different members of
@@ -451,9 +451,10 @@ the Aspeed AST10x0 SoC family:
 - AST1030 : Bridge IC
 - AST1040 : Bridge IC
 - AST1060 : Platform Root of Trust processor
+- AST1080 : Platform Root of Trust processor
 
 The AST1030 and AST1060 integrate an Arm Cortex-M4F CPU running at 200 MHz.
-The AST1040 integrates an Arm Cortex-M4F CPU running at 400 MHz.
+The AST1040 and AST1080 integrate an Arm Cortex-M4F CPU running at 400 MHz.
 
 The SoC comes with SRAM, SPI, I2C, etc.
 
@@ -462,6 +463,7 @@ AST10x0 SoC based machines :
 - ``ast1030-evb``          Aspeed AST1030 Evaluation board (Cortex-M4F)
 - ``ast1040-evb``          Aspeed AST1040 Evaluation board (Cortex-M4F)
 - ``ast1060-evb``          Aspeed AST1060 Evaluation board (Cortex-M4F)
+- ``ast1080-evb``          Aspeed AST1080 Evaluation board (Cortex-M4F)
 
 Supported devices
 -----------------
-- 
2.53.0