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From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: "Pierrick Bouvier" <pierrick.bouvier@oss.qualcomm.com>,
	"Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>,
	"Yoshinori Sato" <yoshinori.sato@nifty.com>
Subject: [PATCH v3 26/33] target/rx: Register CPUClass::exception_name() handler
Date: Thu, 22 Oct 2026 23:51:06 +0200	[thread overview]
Message-ID: <20261022215115.19680-27-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20261022215115.19680-1-philmd@oss.qualcomm.com>

Factor rx_exception_name() out of rx_cpu_do_interrupt()
and register it as the CPUClass::exception_name() handler,
so the common exception logging can resolve RX exception
codes to names.

With '-d int', unlisted codes are now logged as "unknown"
instead of "unknown exception".

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
 target/rx/cpu.h    |  1 +
 target/rx/cpu.c    |  1 +
 target/rx/helper.c | 53 ++++++++++++++++++++++++++++------------------
 3 files changed, 34 insertions(+), 21 deletions(-)

diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 0d9f4898a26..06208380621 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -147,6 +147,7 @@ struct RXCPUClass {
 #define CPU_RESOLVING_TYPE TYPE_RX_CPU
 
 const char *rx_crname(uint8_t cr);
+const char *rx_exception_name(int excp);
 void rx_cpu_do_interrupt(CPUState *cpu);
 bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req);
 hwaddr rx_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 9b8473d71cf..bcaf6659ac5 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -245,6 +245,7 @@ static void rx_cpu_class_init(ObjectClass *klass, const void *data)
                                        &rcc->parent_phases);
 
     cc->class_by_name = rx_cpu_class_by_name;
+    cc->exception_name = rx_exception_name;
     cc->dump_state = rx_cpu_dump_state;
     cc->set_pc = rx_cpu_set_pc;
     cc->get_pc = rx_cpu_get_pc;
diff --git a/target/rx/helper.c b/target/rx/helper.c
index bc76dd28ab3..ed9cadc0bd4 100644
--- a/target/rx/helper.c
+++ b/target/rx/helper.c
@@ -24,6 +24,37 @@
 #include "hw/core/irq.h"
 #include "qemu/plugin.h"
 
+const char *rx_exception_name(int excp)
+{
+    const char *name;
+
+    switch (excp) {
+    case RX_EXCP_PRIVILEGE_VIOLATION:
+        name = "privilege violation";
+        break;
+    case RX_EXCP_ACCESS:
+        name = "access exception";
+        break;
+    case RX_EXCP_ILLEGAL_INSTRUCTION:
+        name = "illegal instruction";
+        break;
+    case RX_EXCP_FPU:
+        name = "fpu exception";
+        break;
+    case RX_EXCP_NMI:
+        name = "non-maskable interrupt";
+        break;
+    case RX_EXCP_TRAP_BASE ... RX_EXCP_TRAP_BASE + RX_EXCP_TRAP_COUNT - 1:
+        name = "unconditional trap";
+        break;
+    default:
+        name = "unknown";
+        break;
+    }
+
+    return name;
+}
+
 void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte)
 {
     if (env->psw_pm == 0) {
@@ -79,7 +110,6 @@ void rx_cpu_do_interrupt(CPUState *cs)
         qemu_log_mask(CPU_LOG_INT, "interrupt 0x%02x raised\n", env->ack_irq);
     } else {
         uint32_t vec = cs->exception_index;
-        const char *expname = "unknown exception";
 
         env->isp -= 4;
         cpu_stl_le_data(env, env->isp, save_psw);
@@ -100,27 +130,8 @@ void rx_cpu_do_interrupt(CPUState *cs)
             qemu_plugin_vcpu_exception_cb(cs, last_pc);
         }
 
-        switch (vec) {
-        case RX_EXCP_PRIVILEGE_VIOLATION:
-            expname = "privilege violation";
-            break;
-        case RX_EXCP_ACCESS:
-            expname = "access exception";
-            break;
-        case RX_EXCP_ILLEGAL_INSTRUCTION:
-            expname = "illegal instruction";
-            break;
-        case RX_EXCP_FPU:
-            expname = "fpu exception";
-            break;
-        case RX_EXCP_NMI:
-            expname = "non-maskable interrupt";
-            break;
-        case RX_EXCP_TRAP_BASE ... RX_EXCP_TRAP_BASE + RX_EXCP_TRAP_COUNT - 1:
-            expname = "unconditional trap";
-        }
         qemu_log_mask(CPU_LOG_INT, "exception 0x%02x [%s] raised\n",
-                      (vec & 0xff), expname);
+                      (vec & 0xff), rx_exception_name(vec));
     }
     env->regs[0] = env->isp;
 }
-- 
2.55.0



  parent reply	other threads:[~2026-10-22 21:55 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-22 21:50 [PATCH v3 00/33] cpus: Add common CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 01/33] qemu/osdep: Document ARRAY_SIZE() macro rejects pointers Philippe Mathieu-Daudé
2026-10-22 22:02   ` Pierrick Bouvier
2026-10-22 21:50 ` [PATCH v3 02/33] util/cutils: Add STR_ARRAY_ELEM_OR_NULL() for string table lookups Philippe Mathieu-Daudé
2026-10-22 22:02   ` Pierrick Bouvier
2026-10-29 13:19   ` Richard Henderson
2026-10-29 17:04     ` Pierrick Bouvier
2026-10-29 22:12       ` Richard Henderson
2026-10-29 22:19         ` Pierrick Bouvier
2026-10-22 21:50 ` [PATCH v3 03/33] cpus: Add helper to log raised exceptions with '-d int' Philippe Mathieu-Daudé
2026-10-29 13:21   ` Richard Henderson
2026-10-22 21:50 ` [PATCH v3 04/33] cpus: Introduce CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-29 13:29   ` Richard Henderson
2026-10-22 21:50 ` [PATCH v3 05/33] target/alpha: Register " Philippe Mathieu-Daudé
2026-10-29 13:25   ` Richard Henderson
2026-10-22 21:50 ` [PATCH v3 06/33] target/alpha: Use a static table in alpha_exception_name() Philippe Mathieu-Daudé
2026-10-29 13:26   ` Richard Henderson
2026-10-22 21:50 ` [PATCH v3 07/33] target/arm: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-29 13:27   ` Richard Henderson
2026-10-22 21:50 ` [PATCH v3 08/33] target/avr: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 09/33] target/hexagon: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 10/33] target/hppa: " Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 11/33] target/i386: Replace magic value by proper EXCP0E_PAGE definition Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 12/33] target/i386: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 13/33] target/loongarch: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 14/33] target/m68k: " Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 15/33] target/m68k: Use a static table in m68k_exception_name() Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 16/33] target/microblaze: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 17/33] target/mips: Remove EXCP_LAST, use ARRAY_SIZE(excp_names) Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 18/33] target/mips: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 19/33] target/or1k: " Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 20/33] target/ppc: Name the EBB exceptions Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 21/33] target/ppc: Use a static table in powerpc_excp_name() Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 22/33] target/ppc: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 23/33] target/riscv: " Philippe Mathieu-Daudé
2026-10-23  1:54   ` Chao Liu via qemu development
2026-10-23  1:54     ` Chao Liu via
2026-10-22 21:51 ` [PATCH v3 24/33] target/rx: Unify BRK and INT trap handling Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 25/33] target/rx: Define exception vector constants Philippe Mathieu-Daudé
2026-10-22 21:51 ` Philippe Mathieu-Daudé [this message]
2026-10-22 21:51 ` [PATCH v3 27/33] target/s390x: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-26 15:07   ` Cornelia Huck
2026-10-22 21:51 ` [PATCH v3 28/33] target/sh4: Define exception vector constants Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 29/33] target/sh4: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 30/33] target/sh4: Use a static table in sh4_exception_name() Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 31/33] target/sparc: Remove always-defined DEBUG_PCALL Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 32/33] target/sparc: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 33/33] target/xtensa: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé

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