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From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: "Pierrick Bouvier" <pierrick.bouvier@oss.qualcomm.com>,
	"Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	qemu-arm@nongnu.org
Subject: [PATCH v3 07/33] target/arm: Register CPUClass::exception_name() handler
Date: Thu, 22 Oct 2026 23:50:47 +0200	[thread overview]
Message-ID: <20261022215115.19680-8-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20261022215115.19680-1-philmd@oss.qualcomm.com>

Factor arm_exception_name() out of arm_log_exception() and
register it as the CPUClass::exception_name() handler, so
the common exception logging can resolve ARM exception codes
to names.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
 target/arm/cpu.h    |  4 ++-
 target/arm/cpu.c    |  1 +
 target/arm/helper.c | 77 ++++++++++++++++++++++-----------------------
 3 files changed, 42 insertions(+), 40 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a0355ba9e1a..add993ef101 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -65,7 +65,9 @@
 #define EXCP_VINMI          27
 #define EXCP_VFNMI          28
 #define EXCP_MON_TRAP       29   /* AArch32 trap to Monitor mode */
-/* NB: add new EXCP_ defines to the array in arm_log_exception() too */
+/* NB: add new EXCP_ defines to the array in arm_exception_name() too */
+
+const char *arm_exception_name(int excp);
 
 #define ARMV7M_EXCP_RESET   1
 #define ARMV7M_EXCP_NMI     2
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 81ec1ce21c6..8efbf673a92 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2647,6 +2647,7 @@ static void arm_cpu_class_init(ObjectClass *oc, const void *data)
                                        &acc->parent_phases);
 
     cc->class_by_name = arm_cpu_class_by_name;
+    cc->exception_name = arm_exception_name;
     cc->dump_state = arm_cpu_dump_state;
     cc->set_pc = arm_cpu_set_pc;
     cc->get_pc = arm_cpu_get_pc;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7ac21108d1c..b540705e638 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8,6 +8,7 @@
 
 #include "qemu/osdep.h"
 #include "qemu/log.h"
+#include "qemu/cutils.h"
 #include "trace.h"
 #include "cpu.h"
 #include "internals.h"
@@ -8841,46 +8842,8 @@ void arm_log_exception(CPUState *cs)
     int idx = cs->exception_index;
 
     if (qemu_loglevel_mask(CPU_LOG_INT)) {
-        const char *exc = NULL;
-        static const char * const excnames[] = {
-            [EXCP_UDEF] = "Undefined Instruction",
-            [EXCP_SWI] = "SVC",
-            [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
-            [EXCP_DATA_ABORT] = "Data Abort",
-            [EXCP_IRQ] = "IRQ",
-            [EXCP_FIQ] = "FIQ",
-            [EXCP_BKPT] = "Breakpoint",
-            [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
-            [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
-            [EXCP_HVC] = "Hypervisor Call",
-            [EXCP_HYP_TRAP] = "Hypervisor Trap",
-            [EXCP_SMC] = "Secure Monitor Call",
-            [EXCP_VIRQ] = "Virtual IRQ",
-            [EXCP_VFIQ] = "Virtual FIQ",
-            [EXCP_SEMIHOST] = "Semihosting call",
-            [EXCP_NOCP] = "v7M NOCP UsageFault",
-            [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
-            [EXCP_STKOF] = "v8M STKOF UsageFault",
-            [EXCP_LAZYFP] = "v7M exception during lazy FP stacking",
-            [EXCP_LSERR] = "v8M LSERR UsageFault",
-            [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
-            [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault",
-            [EXCP_VSERR] = "Virtual SERR",
-            [EXCP_GPC] = "Granule Protection Check",
-            [EXCP_NMI] = "NMI",
-            [EXCP_VINMI] = "Virtual IRQ NMI",
-            [EXCP_VFNMI] = "Virtual FIQ NMI",
-            [EXCP_MON_TRAP] = "Monitor Trap",
-        };
-
-        if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
-            exc = excnames[idx];
-        }
-        if (!exc) {
-            exc = "unknown";
-        }
         qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s] on CPU %d\n",
-                      idx, exc, cs->cpu_index);
+                      idx, arm_exception_name(idx), cs->cpu_index);
     }
 }
 
@@ -9967,6 +9930,42 @@ void arm_cpu_do_interrupt(CPUState *cs)
 }
 #endif /* !CONFIG_USER_ONLY */
 
+const char *arm_exception_name(int excp)
+{
+    static const char * const excnames[] = {
+        [EXCP_UDEF] = "Undefined Instruction",
+        [EXCP_SWI] = "SVC",
+        [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
+        [EXCP_DATA_ABORT] = "Data Abort",
+        [EXCP_IRQ] = "IRQ",
+        [EXCP_FIQ] = "FIQ",
+        [EXCP_BKPT] = "Breakpoint",
+        [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
+        [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
+        [EXCP_HVC] = "Hypervisor Call",
+        [EXCP_HYP_TRAP] = "Hypervisor Trap",
+        [EXCP_SMC] = "Secure Monitor Call",
+        [EXCP_VIRQ] = "Virtual IRQ",
+        [EXCP_VFIQ] = "Virtual FIQ",
+        [EXCP_SEMIHOST] = "Semihosting call",
+        [EXCP_NOCP] = "v7M NOCP UsageFault",
+        [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
+        [EXCP_STKOF] = "v8M STKOF UsageFault",
+        [EXCP_LAZYFP] = "v7M exception during lazy FP stacking",
+        [EXCP_LSERR] = "v8M LSERR UsageFault",
+        [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
+        [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault",
+        [EXCP_VSERR] = "Virtual SERR",
+        [EXCP_GPC] = "Granule Protection Check",
+        [EXCP_NMI] = "NMI",
+        [EXCP_VINMI] = "Virtual IRQ NMI",
+        [EXCP_VFNMI] = "Virtual FIQ NMI",
+        [EXCP_MON_TRAP] = "Monitor Trap",
+    };
+
+    return STR_ARRAY_ELEM_OR_NULL(excnames, excp) ?: "unknown";
+}
+
 uint64_t arm_sctlr(CPUARMState *env, int el)
 {
     /* Only EL0 needs to be adjusted for EL1&0 or EL2&0 or EL3&0 */
-- 
2.55.0



  parent reply	other threads:[~2026-10-22 21:53 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-22 21:50 [PATCH v3 00/33] cpus: Add common CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 01/33] qemu/osdep: Document ARRAY_SIZE() macro rejects pointers Philippe Mathieu-Daudé
2026-10-22 22:02   ` Pierrick Bouvier
2026-10-22 21:50 ` [PATCH v3 02/33] util/cutils: Add STR_ARRAY_ELEM_OR_NULL() for string table lookups Philippe Mathieu-Daudé
2026-10-22 22:02   ` Pierrick Bouvier
2026-10-29 13:19   ` Richard Henderson
2026-10-29 17:04     ` Pierrick Bouvier
2026-10-29 22:12       ` Richard Henderson
2026-10-29 22:19         ` Pierrick Bouvier
2026-10-22 21:50 ` [PATCH v3 03/33] cpus: Add helper to log raised exceptions with '-d int' Philippe Mathieu-Daudé
2026-10-29 13:21   ` Richard Henderson
2026-10-22 21:50 ` [PATCH v3 04/33] cpus: Introduce CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-29 13:29   ` Richard Henderson
2026-10-22 21:50 ` [PATCH v3 05/33] target/alpha: Register " Philippe Mathieu-Daudé
2026-10-29 13:25   ` Richard Henderson
2026-10-22 21:50 ` [PATCH v3 06/33] target/alpha: Use a static table in alpha_exception_name() Philippe Mathieu-Daudé
2026-10-29 13:26   ` Richard Henderson
2026-10-22 21:50 ` Philippe Mathieu-Daudé [this message]
2026-10-29 13:27   ` [PATCH v3 07/33] target/arm: Register CPUClass::exception_name() handler Richard Henderson
2026-10-22 21:50 ` [PATCH v3 08/33] target/avr: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 09/33] target/hexagon: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 10/33] target/hppa: " Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 11/33] target/i386: Replace magic value by proper EXCP0E_PAGE definition Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 12/33] target/i386: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 13/33] target/loongarch: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 14/33] target/m68k: " Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 15/33] target/m68k: Use a static table in m68k_exception_name() Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 16/33] target/microblaze: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 17/33] target/mips: Remove EXCP_LAST, use ARRAY_SIZE(excp_names) Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 18/33] target/mips: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 19/33] target/or1k: " Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 20/33] target/ppc: Name the EBB exceptions Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 21/33] target/ppc: Use a static table in powerpc_excp_name() Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 22/33] target/ppc: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 23/33] target/riscv: " Philippe Mathieu-Daudé
2026-10-23  1:54   ` Chao Liu via qemu development
2026-10-23  1:54     ` Chao Liu via
2026-10-22 21:51 ` [PATCH v3 24/33] target/rx: Unify BRK and INT trap handling Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 25/33] target/rx: Define exception vector constants Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 26/33] target/rx: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 27/33] target/s390x: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-26 15:07   ` Cornelia Huck
2026-10-22 21:51 ` [PATCH v3 28/33] target/sh4: Define exception vector constants Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 29/33] target/sh4: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 30/33] target/sh4: Use a static table in sh4_exception_name() Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 31/33] target/sparc: Remove always-defined DEBUG_PCALL Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 32/33] target/sparc: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 33/33] target/xtensa: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé

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