From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: "Pierrick Bouvier" <pierrick.bouvier@oss.qualcomm.com>,
"Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>,
"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
"Artyom Tarasenko" <atar4qemu@gmail.com>
Subject: [PATCH v3 32/33] target/sparc: Register CPUClass::exception_name() handler
Date: Thu, 22 Oct 2026 23:51:12 +0200 [thread overview]
Message-ID: <20261022215115.19680-33-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20261022215115.19680-1-philmd@oss.qualcomm.com>
For each SPARC / SPARC64 target:
factor sparc_exception_name() out of sparc_cpu_do_interrupt()
and register it as the CPUClass::exception_name() handler, so
the common exception logging can resolve SPARC exception codes
to names.
With '-d int', unlisted codes are now logged as "unknown" instead
of "Unknown". On SPARC, the "Error state" abort message now names
trap instructions (0x80-0xff) instead of calling them "Unknown".
On SPARC64, trap 0x1ff is now named "Hyperprivileged Trap
Instruction"; it was "Unknown" because of an off-by-one in the
former range check.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
target/sparc/cpu.h | 1 +
target/sparc/cpu.c | 1 +
target/sparc/int32_helper.c | 22 ++++++++--------------
target/sparc/int64_helper.c | 36 ++++++++++++++++++------------------
4 files changed, 28 insertions(+), 32 deletions(-)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 31a16c2af03..3c1ba223eb2 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -583,6 +583,7 @@ extern const VMStateDescription vmstate_sparc_cpu;
hwaddr sparc_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);
#endif
+const char *sparc_exception_name(int excp);
void sparc_cpu_do_interrupt(CPUState *cpu);
int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index ae9bdca9df8..1f9a62a8c76 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -1098,6 +1098,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, const void *data)
&scc->parent_phases);
cc->class_by_name = sparc_cpu_class_by_name;
+ cc->exception_name = sparc_exception_name;
cc->list_cpus = sparc_cpu_list,
cc->parse_features = sparc_cpu_parse_features;
cc->dump_state = sparc_cpu_dump_state;
diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c
index d6bb3fa1e54..03ed5dffc9d 100644
--- a/target/sparc/int32_helper.c
+++ b/target/sparc/int32_helper.c
@@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "qemu/main-loop.h"
+#include "qemu/cutils.h"
#include "cpu.h"
#include "trace.h"
#include "accel/tcg/cpu-ldst.h"
@@ -58,12 +59,12 @@ static const char * const excp_names[0x80] = {
[TT_NCP_INSN] = "Coprocessor Disabled",
};
-static const char *excp_name_str(int32_t exception_index)
+const char *sparc_exception_name(int excp)
{
- if (exception_index < 0 || exception_index >= ARRAY_SIZE(excp_names)) {
- return "Unknown";
+ if (excp >= 0x80 && excp < 0x100) {
+ return "Trap Instruction";
}
- return excp_names[exception_index];
+ return STR_ARRAY_ELEM_OR_NULL(excp_names, excp) ?: "unknown";
}
#if !defined(CONFIG_USER_ONLY)
@@ -107,15 +108,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
if (qemu_loglevel_mask(CPU_LOG_INT)) {
static int count;
- const char *name;
-
- if (intno < 0 || intno >= 0x100) {
- name = "Unknown";
- } else if (intno >= 0x80) {
- name = "Trap Instruction";
- } else {
- name = excp_name_str(intno);
- }
+ const char *name = sparc_exception_name(intno);
qemu_log("%6d: %s (v=%02x)\n", count, name, intno);
log_cpu_state(cs, 0);
@@ -129,7 +122,8 @@ void sparc_cpu_do_interrupt(CPUState *cs)
} else {
cpu_abort(cs, "Trap 0x%02x (%s) while interrupts disabled, "
"Error state",
- cs->exception_index, excp_name_str(cs->exception_index));
+ cs->exception_index,
+ sparc_exception_name(cs->exception_index));
}
return;
}
diff --git a/target/sparc/int64_helper.c b/target/sparc/int64_helper.c
index 10341e0c282..849b1a436b2 100644
--- a/target/sparc/int64_helper.c
+++ b/target/sparc/int64_helper.c
@@ -18,6 +18,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/cutils.h"
#include "qemu/main-loop.h"
#include "cpu.h"
#include "exec/cpu-common.h"
@@ -60,6 +61,22 @@ static const char * const excp_names[0x80] = {
[TT_EXTINT | 0xf] = "External Interrupt 15",
};
+const char *sparc_exception_name(int excp)
+{
+ if (excp < 0 || excp >= 0x200) {
+ return "unknown";
+ } else if (excp >= 0x180) {
+ return "Hyperprivileged Trap Instruction";
+ } else if (excp >= 0x100) {
+ return "Trap Instruction";
+ } else if (excp >= 0xc0) {
+ return "Window Fill";
+ } else if (excp >= 0x80) {
+ return "Window Spill";
+ }
+ return STR_ARRAY_ELEM_OR_NULL(excp_names, excp) ?: "unknown";
+}
+
#if !defined(CONFIG_USER_ONLY)
void cpu_check_irqs(CPUSPARCState *env)
{
@@ -136,24 +153,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
if (qemu_loglevel_mask(CPU_LOG_INT)) {
static int count;
- const char *name;
-
- if (intno < 0 || intno >= 0x1ff) {
- name = "Unknown";
- } else if (intno >= 0x180) {
- name = "Hyperprivileged Trap Instruction";
- } else if (intno >= 0x100) {
- name = "Trap Instruction";
- } else if (intno >= 0xc0) {
- name = "Window Fill";
- } else if (intno >= 0x80) {
- name = "Window Spill";
- } else {
- name = excp_names[intno];
- if (!name) {
- name = "Unknown";
- }
- }
+ const char *name = sparc_exception_name(intno);
qemu_log("%6d: %s (v=%04x)\n", count, name, intno);
log_cpu_state(cs, 0);
--
2.55.0
next prev parent reply other threads:[~2026-10-22 21:55 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-22 21:50 [PATCH v3 00/33] cpus: Add common CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 01/33] qemu/osdep: Document ARRAY_SIZE() macro rejects pointers Philippe Mathieu-Daudé
2026-10-22 22:02 ` Pierrick Bouvier
2026-10-22 21:50 ` [PATCH v3 02/33] util/cutils: Add STR_ARRAY_ELEM_OR_NULL() for string table lookups Philippe Mathieu-Daudé
2026-10-22 22:02 ` Pierrick Bouvier
2026-10-29 13:19 ` Richard Henderson
2026-10-29 17:04 ` Pierrick Bouvier
2026-10-29 22:12 ` Richard Henderson
2026-10-29 22:19 ` Pierrick Bouvier
2026-10-22 21:50 ` [PATCH v3 03/33] cpus: Add helper to log raised exceptions with '-d int' Philippe Mathieu-Daudé
2026-10-29 13:21 ` Richard Henderson
2026-10-22 21:50 ` [PATCH v3 04/33] cpus: Introduce CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-29 13:29 ` Richard Henderson
2026-10-22 21:50 ` [PATCH v3 05/33] target/alpha: Register " Philippe Mathieu-Daudé
2026-10-29 13:25 ` Richard Henderson
2026-10-22 21:50 ` [PATCH v3 06/33] target/alpha: Use a static table in alpha_exception_name() Philippe Mathieu-Daudé
2026-10-29 13:26 ` Richard Henderson
2026-10-22 21:50 ` [PATCH v3 07/33] target/arm: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-29 13:27 ` Richard Henderson
2026-10-22 21:50 ` [PATCH v3 08/33] target/avr: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 09/33] target/hexagon: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 10/33] target/hppa: " Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 11/33] target/i386: Replace magic value by proper EXCP0E_PAGE definition Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 12/33] target/i386: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 13/33] target/loongarch: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 14/33] target/m68k: " Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 15/33] target/m68k: Use a static table in m68k_exception_name() Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 16/33] target/microblaze: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 17/33] target/mips: Remove EXCP_LAST, use ARRAY_SIZE(excp_names) Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 18/33] target/mips: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 19/33] target/or1k: " Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 20/33] target/ppc: Name the EBB exceptions Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 21/33] target/ppc: Use a static table in powerpc_excp_name() Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 22/33] target/ppc: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 23/33] target/riscv: " Philippe Mathieu-Daudé
2026-10-23 1:54 ` Chao Liu via qemu development
2026-10-23 1:54 ` Chao Liu via
2026-10-22 21:51 ` [PATCH v3 24/33] target/rx: Unify BRK and INT trap handling Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 25/33] target/rx: Define exception vector constants Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 26/33] target/rx: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 27/33] target/s390x: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-26 15:07 ` Cornelia Huck
2026-10-22 21:51 ` [PATCH v3 28/33] target/sh4: Define exception vector constants Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 29/33] target/sh4: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 30/33] target/sh4: Use a static table in sh4_exception_name() Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 31/33] target/sparc: Remove always-defined DEBUG_PCALL Philippe Mathieu-Daudé
2026-10-22 21:51 ` Philippe Mathieu-Daudé [this message]
2026-10-22 21:51 ` [PATCH v3 33/33] target/xtensa: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
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