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From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: "Pierrick Bouvier" <pierrick.bouvier@oss.qualcomm.com>,
	"Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>,
	"Max Filippov" <jcmvbkbc@gmail.com>
Subject: [PATCH v3 33/33] target/xtensa: Implement and register CPUClass::exception_name()
Date: Thu, 22 Oct 2026 23:51:13 +0200	[thread overview]
Message-ID: <20261022215115.19680-34-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20261022215115.19680-1-philmd@oss.qualcomm.com>

Implement xtensa_exception_name() and register it as the
CPUClass::exception_name() handler, so the common exception
logging can resolve Xtensa exception codes to names.

Use the new helper in xtensa_cpu_do_interrupt().

With '-d int', xtensa_cpu_do_interrupt() now logs the exception
name after its number.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
 target/xtensa/cpu.h        |  2 ++
 target/xtensa/cpu.c        | 24 ++++++++++++++++++++++++
 target/xtensa/exc_helper.c |  3 ++-
 3 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 49d6ad9083d..3440c27862b 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -262,6 +262,8 @@ enum {
     EXC_MAX
 };
 
+const char *xtensa_exception_name(int excp);
+
 enum {
     ILLEGAL_INSTRUCTION_CAUSE = 0,
     SYSCALL_CAUSE,
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 7c25b9ab707..169d6835418 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -29,6 +29,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/cutils.h"
 #include "qapi/error.h"
 #include "exec/cpu-defs.h"
 #include "cpu.h"
@@ -239,6 +240,28 @@ static void xtensa_cpu_disas_set_info(const CPUState *cs,
                                      : BFD_ENDIAN_LITTLE;
 }
 
+const char *xtensa_exception_name(int excp)
+{
+    static const char * const excp_names[] = {
+        [EXC_RESET0]                = "reset",
+        [EXC_RESET1]                = "reset",
+        [EXC_MEMORY_ERROR]          = "memory error",
+        [EXC_WINDOW_OVERFLOW4]      = "window overflow",
+        [EXC_WINDOW_UNDERFLOW4]     = "window underflow",
+        [EXC_WINDOW_OVERFLOW8]      = "window overflow",
+        [EXC_WINDOW_UNDERFLOW8]     = "window underflow",
+        [EXC_WINDOW_OVERFLOW12]     = "window overflow",
+        [EXC_WINDOW_UNDERFLOW12]    = "window underflow",
+        [EXC_IRQ]                   = "interrupt",
+        [EXC_KERNEL]                = "kernel",
+        [EXC_USER]                  = "user",
+        [EXC_DOUBLE]                = "double",
+        [EXC_DEBUG]                 = "debug",
+    };
+
+    return STR_ARRAY_ELEM_OR_NULL(excp_names, excp) ?: "unknown";
+}
+
 static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
 {
     CPUState *cs = CPU(dev);
@@ -348,6 +371,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, const void *data)
                                        &xcc->parent_phases);
 
     cc->class_by_name = xtensa_cpu_class_by_name;
+    cc->exception_name = xtensa_exception_name;
     cc->dump_state = xtensa_cpu_dump_state;
     cc->set_pc = xtensa_cpu_set_pc;
     cc->get_pc = xtensa_cpu_get_pc;
diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c
index 7cb67d179a8..ff71e5d6462 100644
--- a/target/xtensa/exc_helper.c
+++ b/target/xtensa/exc_helper.c
@@ -236,9 +236,10 @@ void xtensa_cpu_do_interrupt(CPUState *cs)
     case EXC_USER:
     case EXC_DOUBLE:
     case EXC_DEBUG:
-        qemu_log_mask(CPU_LOG_INT, "%s(%d) "
+        qemu_log_mask(CPU_LOG_INT, "%s(%d:%s) "
                       "pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
                       __func__, cs->exception_index,
+                      xtensa_exception_name(cs->exception_index),
                       env->pc, env->regs[0], env->sregs[PS],
                       env->sregs[CCOUNT]);
         if (env->config->exception_vector[cs->exception_index]) {
-- 
2.55.0



      parent reply	other threads:[~2026-10-22 21:56 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-22 21:50 [PATCH v3 00/33] cpus: Add common CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 01/33] qemu/osdep: Document ARRAY_SIZE() macro rejects pointers Philippe Mathieu-Daudé
2026-10-22 22:02   ` Pierrick Bouvier
2026-10-22 21:50 ` [PATCH v3 02/33] util/cutils: Add STR_ARRAY_ELEM_OR_NULL() for string table lookups Philippe Mathieu-Daudé
2026-10-22 22:02   ` Pierrick Bouvier
2026-10-29 13:19   ` Richard Henderson
2026-10-29 17:04     ` Pierrick Bouvier
2026-10-29 22:12       ` Richard Henderson
2026-10-29 22:19         ` Pierrick Bouvier
2026-10-22 21:50 ` [PATCH v3 03/33] cpus: Add helper to log raised exceptions with '-d int' Philippe Mathieu-Daudé
2026-10-29 13:21   ` Richard Henderson
2026-10-22 21:50 ` [PATCH v3 04/33] cpus: Introduce CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-29 13:29   ` Richard Henderson
2026-10-22 21:50 ` [PATCH v3 05/33] target/alpha: Register " Philippe Mathieu-Daudé
2026-10-29 13:25   ` Richard Henderson
2026-10-22 21:50 ` [PATCH v3 06/33] target/alpha: Use a static table in alpha_exception_name() Philippe Mathieu-Daudé
2026-10-29 13:26   ` Richard Henderson
2026-10-22 21:50 ` [PATCH v3 07/33] target/arm: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-29 13:27   ` Richard Henderson
2026-10-22 21:50 ` [PATCH v3 08/33] target/avr: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 09/33] target/hexagon: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 10/33] target/hppa: " Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 11/33] target/i386: Replace magic value by proper EXCP0E_PAGE definition Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 12/33] target/i386: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 13/33] target/loongarch: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 14/33] target/m68k: " Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 15/33] target/m68k: Use a static table in m68k_exception_name() Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 16/33] target/microblaze: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 17/33] target/mips: Remove EXCP_LAST, use ARRAY_SIZE(excp_names) Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 18/33] target/mips: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:50 ` [PATCH v3 19/33] target/or1k: " Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 20/33] target/ppc: Name the EBB exceptions Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 21/33] target/ppc: Use a static table in powerpc_excp_name() Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 22/33] target/ppc: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 23/33] target/riscv: " Philippe Mathieu-Daudé
2026-10-23  1:54   ` Chao Liu via qemu development
2026-10-23  1:54     ` Chao Liu via
2026-10-22 21:51 ` [PATCH v3 24/33] target/rx: Unify BRK and INT trap handling Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 25/33] target/rx: Define exception vector constants Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 26/33] target/rx: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 27/33] target/s390x: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-26 15:07   ` Cornelia Huck
2026-10-22 21:51 ` [PATCH v3 28/33] target/sh4: Define exception vector constants Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 29/33] target/sh4: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 30/33] target/sh4: Use a static table in sh4_exception_name() Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 31/33] target/sparc: Remove always-defined DEBUG_PCALL Philippe Mathieu-Daudé
2026-10-22 21:51 ` [PATCH v3 32/33] target/sparc: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-22 21:51 ` Philippe Mathieu-Daudé [this message]

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