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From: fangyu.yu@linux.alibaba.com
To: tomasz.jeznach@linux.dev, joro@8bytes.org, will@kernel.org,
	robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, alex@ghiti.fr, baolu.lu@linux.intel.com,
	jroedel@suse.de, zong.li@sifive.com, andrew.jones@linux.dev,
	anup@brainfault.org, jgg@nvidia.com, jgg@ziepe.ca,
	kevin.tian@intel.com, atish.patra@linux.dev, skhawaja@google.com,
	vasant.hegde@amd.com, joerg.roedel@amd.com,
	tanchi25@mails.ucas.ac.cn, gong.shuai@sanechips.com.cn
Cc: fangyu.yu@linux.alibaba.com, guoren@kernel.org,
	iommu@lists.linux.dev, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org,
	Andrew Jones <andrew.jones@oss.qualcomm.com>,
	Nutty Liu <nutty.liu@hotmail.com>
Subject: [PATCH v6 01/10] iommu/generic_pt: Fix the RISC-V supported feature mask
Date: Sat, 31 Oct 2026 16:30:05 +0800	[thread overview]
Message-ID: <20261031083014.15040-2-fangyu.yu@linux.alibaba.com> (raw)
In-Reply-To: <20261031083014.15040-1-fangyu.yu@linux.alibaba.com>

From: Andrew Jones <andrew.jones@oss.qualcomm.com>

The RISC-V format advertises Svpbmt to its users, but omits the feature
from PT_SUPPORTED_FEATURES. Add it there so configurations which enable
Svpbmt pass generic page-table feature validation.

Fixes: f196a8668797 ("iommu/riscv: Advertise Svpbmt support to generic page table")
Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
Tested-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
---
 drivers/iommu/generic_pt/fmt/iommu_riscv64.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/iommu/generic_pt/fmt/iommu_riscv64.c b/drivers/iommu/generic_pt/fmt/iommu_riscv64.c
index b18fc4d109f5..1bb74114fb02 100644
--- a/drivers/iommu/generic_pt/fmt/iommu_riscv64.c
+++ b/drivers/iommu/generic_pt/fmt/iommu_riscv64.c
@@ -7,7 +7,8 @@
 #define PT_SUPPORTED_FEATURES                                  \
 	(BIT(PT_FEAT_SIGN_EXTEND) | BIT(PT_FEAT_FLUSH_RANGE) | \
 	 BIT(PT_FEAT_RISCV_SVNAPOT_64K) |                      \
-	 BIT(PT_FEAT_DETAILED_GATHER))
+	 BIT(PT_FEAT_DETAILED_GATHER) |                        \
+	 BIT(PT_FEAT_RISCV_SVPBMT))
 #define PT_FORCE_ENABLED_FEATURES BIT(PT_FEAT_DETAILED_GATHER)
 
 #include "iommu_template.h"
-- 
2.50.1


WARNING: multiple messages have this Message-ID (diff)
From: fangyu.yu@linux.alibaba.com
To: tomasz.jeznach@linux.dev, joro@8bytes.org, will@kernel.org,
	robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, alex@ghiti.fr, baolu.lu@linux.intel.com,
	jroedel@suse.de, zong.li@sifive.com, andrew.jones@linux.dev,
	anup@brainfault.org, jgg@nvidia.com, jgg@ziepe.ca,
	kevin.tian@intel.com, atish.patra@linux.dev, skhawaja@google.com,
	vasant.hegde@amd.com, joerg.roedel@amd.com,
	tanchi25@mails.ucas.ac.cn, gong.shuai@sanechips.com.cn
Cc: fangyu.yu@linux.alibaba.com, guoren@kernel.org,
	iommu@lists.linux.dev, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org,
	Andrew Jones <andrew.jones@oss.qualcomm.com>,
	Nutty Liu <nutty.liu@hotmail.com>
Subject: [PATCH v6 01/10] iommu/generic_pt: Fix the RISC-V supported feature mask
Date: Sat, 31 Oct 2026 16:30:05 +0800	[thread overview]
Message-ID: <20261031083014.15040-2-fangyu.yu@linux.alibaba.com> (raw)
In-Reply-To: <20261031083014.15040-1-fangyu.yu@linux.alibaba.com>

From: Andrew Jones <andrew.jones@oss.qualcomm.com>

The RISC-V format advertises Svpbmt to its users, but omits the feature
from PT_SUPPORTED_FEATURES. Add it there so configurations which enable
Svpbmt pass generic page-table feature validation.

Fixes: f196a8668797 ("iommu/riscv: Advertise Svpbmt support to generic page table")
Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
Tested-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
---
 drivers/iommu/generic_pt/fmt/iommu_riscv64.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/iommu/generic_pt/fmt/iommu_riscv64.c b/drivers/iommu/generic_pt/fmt/iommu_riscv64.c
index b18fc4d109f5..1bb74114fb02 100644
--- a/drivers/iommu/generic_pt/fmt/iommu_riscv64.c
+++ b/drivers/iommu/generic_pt/fmt/iommu_riscv64.c
@@ -7,7 +7,8 @@
 #define PT_SUPPORTED_FEATURES                                  \
 	(BIT(PT_FEAT_SIGN_EXTEND) | BIT(PT_FEAT_FLUSH_RANGE) | \
 	 BIT(PT_FEAT_RISCV_SVNAPOT_64K) |                      \
-	 BIT(PT_FEAT_DETAILED_GATHER))
+	 BIT(PT_FEAT_DETAILED_GATHER) |                        \
+	 BIT(PT_FEAT_RISCV_SVPBMT))
 #define PT_FORCE_ENABLED_FEATURES BIT(PT_FEAT_DETAILED_GATHER)
 
 #include "iommu_template.h"
-- 
2.50.1


-- 
kvm-riscv mailing list
kvm-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/kvm-riscv

WARNING: multiple messages have this Message-ID (diff)
From: fangyu.yu@linux.alibaba.com
To: tomasz.jeznach@linux.dev, joro@8bytes.org, will@kernel.org,
	robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, alex@ghiti.fr, baolu.lu@linux.intel.com,
	jroedel@suse.de, zong.li@sifive.com, andrew.jones@linux.dev,
	anup@brainfault.org, jgg@nvidia.com, jgg@ziepe.ca,
	kevin.tian@intel.com, atish.patra@linux.dev, skhawaja@google.com,
	vasant.hegde@amd.com, joerg.roedel@amd.com,
	tanchi25@mails.ucas.ac.cn, gong.shuai@sanechips.com.cn
Cc: fangyu.yu@linux.alibaba.com, guoren@kernel.org,
	iommu@lists.linux.dev, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org,
	Andrew Jones <andrew.jones@oss.qualcomm.com>,
	Nutty Liu <nutty.liu@hotmail.com>
Subject: [PATCH v6 01/10] iommu/generic_pt: Fix the RISC-V supported feature mask
Date: Sat, 31 Oct 2026 16:30:05 +0800	[thread overview]
Message-ID: <20261031083014.15040-2-fangyu.yu@linux.alibaba.com> (raw)
In-Reply-To: <20261031083014.15040-1-fangyu.yu@linux.alibaba.com>

From: Andrew Jones <andrew.jones@oss.qualcomm.com>

The RISC-V format advertises Svpbmt to its users, but omits the feature
from PT_SUPPORTED_FEATURES. Add it there so configurations which enable
Svpbmt pass generic page-table feature validation.

Fixes: f196a8668797 ("iommu/riscv: Advertise Svpbmt support to generic page table")
Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
Tested-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
---
 drivers/iommu/generic_pt/fmt/iommu_riscv64.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/iommu/generic_pt/fmt/iommu_riscv64.c b/drivers/iommu/generic_pt/fmt/iommu_riscv64.c
index b18fc4d109f5..1bb74114fb02 100644
--- a/drivers/iommu/generic_pt/fmt/iommu_riscv64.c
+++ b/drivers/iommu/generic_pt/fmt/iommu_riscv64.c
@@ -7,7 +7,8 @@
 #define PT_SUPPORTED_FEATURES                                  \
 	(BIT(PT_FEAT_SIGN_EXTEND) | BIT(PT_FEAT_FLUSH_RANGE) | \
 	 BIT(PT_FEAT_RISCV_SVNAPOT_64K) |                      \
-	 BIT(PT_FEAT_DETAILED_GATHER))
+	 BIT(PT_FEAT_DETAILED_GATHER) |                        \
+	 BIT(PT_FEAT_RISCV_SVPBMT))
 #define PT_FORCE_ENABLED_FEATURES BIT(PT_FEAT_DETAILED_GATHER)
 
 #include "iommu_template.h"
-- 
2.50.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2026-10-31  8:30 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-31  8:30 [PATCH v6 00/10] iommu/riscv: Add hardware dirty tracking for second-stage domains fangyu.yu
2026-10-31  8:30 ` fangyu.yu
2026-10-31  8:30 ` fangyu.yu
2026-10-31  8:30 ` fangyu.yu [this message]
2026-10-31  8:30   ` [PATCH v6 01/10] iommu/generic_pt: Fix the RISC-V supported feature mask fangyu.yu
2026-10-31  8:30   ` fangyu.yu
2026-10-31  8:30 ` [PATCH v6 02/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support fangyu.yu
2026-10-31  8:30   ` fangyu.yu
2026-10-31  8:30   ` fangyu.yu
2026-10-31  8:30 ` [PATCH v6 03/10] iommupt: Add RISC-V dirty tracking PTE ops fangyu.yu
2026-10-31  8:30   ` fangyu.yu
2026-10-31  8:30   ` fangyu.yu
2026-10-31  8:30 ` [PATCH v6 04/10] iommu/riscv: use data structure instead of individual values fangyu.yu
2026-10-31  8:30   ` fangyu.yu
2026-10-31  8:30   ` fangyu.yu
2026-10-31  8:30 ` [PATCH v6 05/10] iommu/riscv: support GSCID and GVMA invalidation command fangyu.yu
2026-10-31  8:30   ` fangyu.yu
2026-10-31  8:30   ` fangyu.yu
2026-10-31  8:30 ` [PATCH v6 06/10] RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch fangyu.yu
2026-10-31  8:30   ` fangyu.yu
2026-10-31  8:30   ` fangyu.yu
2026-10-31  8:30 ` [PATCH v6 07/10] iommu/riscv: Add domain_alloc_paging_flags for second-stage domain fangyu.yu
2026-10-31  8:30   ` fangyu.yu
2026-10-31  8:30   ` fangyu.yu
2026-10-31  8:30 ` [PATCH v6 08/10] iommu/riscv: Pre-enable GADE for second-stage domains fangyu.yu
2026-10-31  8:30   ` fangyu.yu
2026-10-31  8:30   ` fangyu.yu
2026-10-31  8:30 ` [PATCH v6 09/10] iommu/riscv: Add dirty tracking support " fangyu.yu
2026-10-31  8:30   ` fangyu.yu
2026-10-31  8:30   ` fangyu.yu
2026-11-02  9:18   ` Gong Shuai
2026-11-02  9:18     ` Gong Shuai
2026-11-02  9:18     ` Gong Shuai
2026-11-02 13:13     ` Jason Gunthorpe
2026-11-02 13:13       ` Jason Gunthorpe
2026-11-02 13:13       ` Jason Gunthorpe
2026-11-02 13:21       ` fangyu.yu
2026-11-02 13:21         ` fangyu.yu
2026-11-02 13:21         ` fangyu.yu
2026-10-31  8:30 ` [PATCH v6 10/10] iommu/riscv: Add IOTINVAL.GVMA invalidations fangyu.yu
2026-10-31  8:30   ` fangyu.yu
2026-10-31  8:30   ` fangyu.yu

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