From: fangyu.yu@linux.alibaba.com
To: tomasz.jeznach@linux.dev, joro@8bytes.org, will@kernel.org,
robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, baolu.lu@linux.intel.com,
jroedel@suse.de, zong.li@sifive.com, andrew.jones@linux.dev,
anup@brainfault.org, jgg@nvidia.com, jgg@ziepe.ca,
kevin.tian@intel.com, atish.patra@linux.dev, skhawaja@google.com,
vasant.hegde@amd.com, joerg.roedel@amd.com,
tanchi25@mails.ucas.ac.cn, gong.shuai@sanechips.com.cn
Cc: fangyu.yu@linux.alibaba.com, guoren@kernel.org,
iommu@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org
Subject: [PATCH v6 03/10] iommupt: Add RISC-V dirty tracking PTE ops
Date: Sat, 31 Oct 2026 16:30:07 +0800 [thread overview]
Message-ID: <20261031083014.15040-4-fangyu.yu@linux.alibaba.com> (raw)
In-Reply-To: <20261031083014.15040-1-fangyu.yu@linux.alibaba.com>
From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Implement the three dirty-tracking hooks required by the generic page
table framework for the RISC-V format:
pt_entry_is_write_dirty():
Check the D bit (bit 7) in the PTE.
pt_entry_make_write_clean():
Clear the D bit across the full contiguous range.
pt_entry_make_write_dirty():
Atomically set D via try_cmpxchg64() on a single PTE.
Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
---
drivers/iommu/generic_pt/fmt/riscv.h | 49 ++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/drivers/iommu/generic_pt/fmt/riscv.h b/drivers/iommu/generic_pt/fmt/riscv.h
index d4445e463fa9..2f4838eb44af 100644
--- a/drivers/iommu/generic_pt/fmt/riscv.h
+++ b/drivers/iommu/generic_pt/fmt/riscv.h
@@ -223,6 +223,55 @@ static inline void riscvpt_attr_from_entry(const struct pt_state *pts,
}
#define pt_attr_from_entry riscvpt_attr_from_entry
+/*
+ * Dirty tracking: RISC-V PTEs use D (bit 7) as the hardware dirty bit.
+ * When Svnapot 64K is active a leaf entry spans 16 consecutive PTEs; we
+ * must check / clear all of them so that no dirty indication is lost.
+ */
+static inline bool riscvpt_entry_is_write_dirty(const struct pt_state *pts)
+{
+ unsigned int num_contig_lg2 = riscvpt_entry_num_contig_lg2(pts);
+ const pt_riscv_entry_t *tablep =
+ pt_cur_table(pts, pt_riscv_entry_t) +
+ log2_set_mod(pts->index, 0, num_contig_lg2);
+ const pt_riscv_entry_t *end = tablep + log2_to_int(num_contig_lg2);
+
+ for (; tablep != end; tablep++)
+ if (READ_ONCE(*tablep) & RISCVPT_D)
+ return true;
+ return false;
+}
+#define pt_entry_is_write_dirty riscvpt_entry_is_write_dirty
+
+static inline void riscvpt_entry_make_write_clean(struct pt_state *pts)
+{
+ unsigned int num_contig_lg2 = riscvpt_entry_num_contig_lg2(pts);
+ pt_riscv_entry_t *tablep =
+ pt_cur_table(pts, pt_riscv_entry_t) +
+ log2_set_mod(pts->index, 0, num_contig_lg2);
+ pt_riscv_entry_t *end = tablep + log2_to_int(num_contig_lg2);
+
+ for (; tablep != end; tablep++)
+ WRITE_ONCE(*tablep, READ_ONCE(*tablep) & ~(pt_riscv_entry_t)RISCVPT_D);
+}
+#define pt_entry_make_write_clean riscvpt_entry_make_write_clean
+
+static inline bool riscvpt_entry_make_write_dirty(struct pt_state *pts)
+{
+ pt_riscv_entry_t *tablep =
+ pt_cur_table(pts, pt_riscv_entry_t) + pts->index;
+ pt_riscv_entry_t new = pts->entry | RISCVPT_D;
+
+ return try_cmpxchg64(tablep, &pts->entry, new);
+}
+#define pt_entry_make_write_dirty riscvpt_entry_make_write_dirty
+
+static inline bool riscvpt_dirty_supported(struct pt_common *common)
+{
+ return pt_feature(common, PT_FEAT_RISCV_S2);
+}
+#define pt_dirty_supported riscvpt_dirty_supported
+
/* --- iommu */
#include <linux/generic_pt/iommu.h>
#include <linux/iommu.h>
--
2.50.1
--
kvm-riscv mailing list
kvm-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/kvm-riscv
WARNING: multiple messages have this Message-ID (diff)
From: fangyu.yu@linux.alibaba.com
To: tomasz.jeznach@linux.dev, joro@8bytes.org, will@kernel.org,
robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, baolu.lu@linux.intel.com,
jroedel@suse.de, zong.li@sifive.com, andrew.jones@linux.dev,
anup@brainfault.org, jgg@nvidia.com, jgg@ziepe.ca,
kevin.tian@intel.com, atish.patra@linux.dev, skhawaja@google.com,
vasant.hegde@amd.com, joerg.roedel@amd.com,
tanchi25@mails.ucas.ac.cn, gong.shuai@sanechips.com.cn
Cc: fangyu.yu@linux.alibaba.com, guoren@kernel.org,
iommu@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org
Subject: [PATCH v6 03/10] iommupt: Add RISC-V dirty tracking PTE ops
Date: Sat, 31 Oct 2026 16:30:07 +0800 [thread overview]
Message-ID: <20261031083014.15040-4-fangyu.yu@linux.alibaba.com> (raw)
In-Reply-To: <20261031083014.15040-1-fangyu.yu@linux.alibaba.com>
From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Implement the three dirty-tracking hooks required by the generic page
table framework for the RISC-V format:
pt_entry_is_write_dirty():
Check the D bit (bit 7) in the PTE.
pt_entry_make_write_clean():
Clear the D bit across the full contiguous range.
pt_entry_make_write_dirty():
Atomically set D via try_cmpxchg64() on a single PTE.
Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
---
drivers/iommu/generic_pt/fmt/riscv.h | 49 ++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/drivers/iommu/generic_pt/fmt/riscv.h b/drivers/iommu/generic_pt/fmt/riscv.h
index d4445e463fa9..2f4838eb44af 100644
--- a/drivers/iommu/generic_pt/fmt/riscv.h
+++ b/drivers/iommu/generic_pt/fmt/riscv.h
@@ -223,6 +223,55 @@ static inline void riscvpt_attr_from_entry(const struct pt_state *pts,
}
#define pt_attr_from_entry riscvpt_attr_from_entry
+/*
+ * Dirty tracking: RISC-V PTEs use D (bit 7) as the hardware dirty bit.
+ * When Svnapot 64K is active a leaf entry spans 16 consecutive PTEs; we
+ * must check / clear all of them so that no dirty indication is lost.
+ */
+static inline bool riscvpt_entry_is_write_dirty(const struct pt_state *pts)
+{
+ unsigned int num_contig_lg2 = riscvpt_entry_num_contig_lg2(pts);
+ const pt_riscv_entry_t *tablep =
+ pt_cur_table(pts, pt_riscv_entry_t) +
+ log2_set_mod(pts->index, 0, num_contig_lg2);
+ const pt_riscv_entry_t *end = tablep + log2_to_int(num_contig_lg2);
+
+ for (; tablep != end; tablep++)
+ if (READ_ONCE(*tablep) & RISCVPT_D)
+ return true;
+ return false;
+}
+#define pt_entry_is_write_dirty riscvpt_entry_is_write_dirty
+
+static inline void riscvpt_entry_make_write_clean(struct pt_state *pts)
+{
+ unsigned int num_contig_lg2 = riscvpt_entry_num_contig_lg2(pts);
+ pt_riscv_entry_t *tablep =
+ pt_cur_table(pts, pt_riscv_entry_t) +
+ log2_set_mod(pts->index, 0, num_contig_lg2);
+ pt_riscv_entry_t *end = tablep + log2_to_int(num_contig_lg2);
+
+ for (; tablep != end; tablep++)
+ WRITE_ONCE(*tablep, READ_ONCE(*tablep) & ~(pt_riscv_entry_t)RISCVPT_D);
+}
+#define pt_entry_make_write_clean riscvpt_entry_make_write_clean
+
+static inline bool riscvpt_entry_make_write_dirty(struct pt_state *pts)
+{
+ pt_riscv_entry_t *tablep =
+ pt_cur_table(pts, pt_riscv_entry_t) + pts->index;
+ pt_riscv_entry_t new = pts->entry | RISCVPT_D;
+
+ return try_cmpxchg64(tablep, &pts->entry, new);
+}
+#define pt_entry_make_write_dirty riscvpt_entry_make_write_dirty
+
+static inline bool riscvpt_dirty_supported(struct pt_common *common)
+{
+ return pt_feature(common, PT_FEAT_RISCV_S2);
+}
+#define pt_dirty_supported riscvpt_dirty_supported
+
/* --- iommu */
#include <linux/generic_pt/iommu.h>
#include <linux/iommu.h>
--
2.50.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: fangyu.yu@linux.alibaba.com
To: tomasz.jeznach@linux.dev, joro@8bytes.org, will@kernel.org,
robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, baolu.lu@linux.intel.com,
jroedel@suse.de, zong.li@sifive.com, andrew.jones@linux.dev,
anup@brainfault.org, jgg@nvidia.com, jgg@ziepe.ca,
kevin.tian@intel.com, atish.patra@linux.dev, skhawaja@google.com,
vasant.hegde@amd.com, joerg.roedel@amd.com,
tanchi25@mails.ucas.ac.cn, gong.shuai@sanechips.com.cn
Cc: fangyu.yu@linux.alibaba.com, guoren@kernel.org,
iommu@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org
Subject: [PATCH v6 03/10] iommupt: Add RISC-V dirty tracking PTE ops
Date: Sat, 31 Oct 2026 16:30:07 +0800 [thread overview]
Message-ID: <20261031083014.15040-4-fangyu.yu@linux.alibaba.com> (raw)
In-Reply-To: <20261031083014.15040-1-fangyu.yu@linux.alibaba.com>
From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Implement the three dirty-tracking hooks required by the generic page
table framework for the RISC-V format:
pt_entry_is_write_dirty():
Check the D bit (bit 7) in the PTE.
pt_entry_make_write_clean():
Clear the D bit across the full contiguous range.
pt_entry_make_write_dirty():
Atomically set D via try_cmpxchg64() on a single PTE.
Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
---
drivers/iommu/generic_pt/fmt/riscv.h | 49 ++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/drivers/iommu/generic_pt/fmt/riscv.h b/drivers/iommu/generic_pt/fmt/riscv.h
index d4445e463fa9..2f4838eb44af 100644
--- a/drivers/iommu/generic_pt/fmt/riscv.h
+++ b/drivers/iommu/generic_pt/fmt/riscv.h
@@ -223,6 +223,55 @@ static inline void riscvpt_attr_from_entry(const struct pt_state *pts,
}
#define pt_attr_from_entry riscvpt_attr_from_entry
+/*
+ * Dirty tracking: RISC-V PTEs use D (bit 7) as the hardware dirty bit.
+ * When Svnapot 64K is active a leaf entry spans 16 consecutive PTEs; we
+ * must check / clear all of them so that no dirty indication is lost.
+ */
+static inline bool riscvpt_entry_is_write_dirty(const struct pt_state *pts)
+{
+ unsigned int num_contig_lg2 = riscvpt_entry_num_contig_lg2(pts);
+ const pt_riscv_entry_t *tablep =
+ pt_cur_table(pts, pt_riscv_entry_t) +
+ log2_set_mod(pts->index, 0, num_contig_lg2);
+ const pt_riscv_entry_t *end = tablep + log2_to_int(num_contig_lg2);
+
+ for (; tablep != end; tablep++)
+ if (READ_ONCE(*tablep) & RISCVPT_D)
+ return true;
+ return false;
+}
+#define pt_entry_is_write_dirty riscvpt_entry_is_write_dirty
+
+static inline void riscvpt_entry_make_write_clean(struct pt_state *pts)
+{
+ unsigned int num_contig_lg2 = riscvpt_entry_num_contig_lg2(pts);
+ pt_riscv_entry_t *tablep =
+ pt_cur_table(pts, pt_riscv_entry_t) +
+ log2_set_mod(pts->index, 0, num_contig_lg2);
+ pt_riscv_entry_t *end = tablep + log2_to_int(num_contig_lg2);
+
+ for (; tablep != end; tablep++)
+ WRITE_ONCE(*tablep, READ_ONCE(*tablep) & ~(pt_riscv_entry_t)RISCVPT_D);
+}
+#define pt_entry_make_write_clean riscvpt_entry_make_write_clean
+
+static inline bool riscvpt_entry_make_write_dirty(struct pt_state *pts)
+{
+ pt_riscv_entry_t *tablep =
+ pt_cur_table(pts, pt_riscv_entry_t) + pts->index;
+ pt_riscv_entry_t new = pts->entry | RISCVPT_D;
+
+ return try_cmpxchg64(tablep, &pts->entry, new);
+}
+#define pt_entry_make_write_dirty riscvpt_entry_make_write_dirty
+
+static inline bool riscvpt_dirty_supported(struct pt_common *common)
+{
+ return pt_feature(common, PT_FEAT_RISCV_S2);
+}
+#define pt_dirty_supported riscvpt_dirty_supported
+
/* --- iommu */
#include <linux/generic_pt/iommu.h>
#include <linux/iommu.h>
--
2.50.1
next prev parent reply other threads:[~2026-10-31 8:30 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-31 8:30 [PATCH v6 00/10] iommu/riscv: Add hardware dirty tracking for second-stage domains fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` [PATCH v6 01/10] iommu/generic_pt: Fix the RISC-V supported feature mask fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` [PATCH v6 02/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` fangyu.yu [this message]
2026-10-31 8:30 ` [PATCH v6 03/10] iommupt: Add RISC-V dirty tracking PTE ops fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` [PATCH v6 04/10] iommu/riscv: use data structure instead of individual values fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` [PATCH v6 05/10] iommu/riscv: support GSCID and GVMA invalidation command fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` [PATCH v6 06/10] RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` [PATCH v6 07/10] iommu/riscv: Add domain_alloc_paging_flags for second-stage domain fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` [PATCH v6 08/10] iommu/riscv: Pre-enable GADE for second-stage domains fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` [PATCH v6 09/10] iommu/riscv: Add dirty tracking support " fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-11-02 9:18 ` Gong Shuai
2026-11-02 9:18 ` Gong Shuai
2026-11-02 9:18 ` Gong Shuai
2026-11-02 13:13 ` Jason Gunthorpe
2026-11-02 13:13 ` Jason Gunthorpe
2026-11-02 13:13 ` Jason Gunthorpe
2026-11-02 13:21 ` fangyu.yu
2026-11-02 13:21 ` fangyu.yu
2026-11-02 13:21 ` fangyu.yu
2026-10-31 8:30 ` [PATCH v6 10/10] iommu/riscv: Add IOTINVAL.GVMA invalidations fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` fangyu.yu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20261031083014.15040-4-fangyu.yu@linux.alibaba.com \
--to=fangyu.yu@linux.alibaba.com \
--cc=alex@ghiti.fr \
--cc=andrew.jones@linux.dev \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=atish.patra@linux.dev \
--cc=baolu.lu@linux.intel.com \
--cc=gong.shuai@sanechips.com.cn \
--cc=guoren@kernel.org \
--cc=iommu@lists.linux.dev \
--cc=jgg@nvidia.com \
--cc=jgg@ziepe.ca \
--cc=joerg.roedel@amd.com \
--cc=joro@8bytes.org \
--cc=jroedel@suse.de \
--cc=kevin.tian@intel.com \
--cc=kvm-riscv@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=pjw@kernel.org \
--cc=robin.murphy@arm.com \
--cc=skhawaja@google.com \
--cc=tanchi25@mails.ucas.ac.cn \
--cc=tomasz.jeznach@linux.dev \
--cc=vasant.hegde@amd.com \
--cc=will@kernel.org \
--cc=zong.li@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.