From: Jason Gunthorpe <jgg@ziepe.ca>
To: Gong Shuai <gong.shuai@sanechips.com.cn>
Cc: fangyu.yu@linux.alibaba.com, alex@ghiti.fr,
andrew.jones@linux.dev, anup@brainfault.org,
aou@eecs.berkeley.edu, atish.patra@linux.dev,
baolu.lu@linux.intel.com, guoren@kernel.org,
iommu@lists.linux.dev, joerg.roedel@amd.com, joro@8bytes.org,
jroedel@suse.de, kevin.tian@intel.com,
kvm-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, nutty.liu@hotmail.com,
palmer@dabbelt.com, pjw@kernel.org, robin.murphy@arm.com,
skhawaja@google.com, tanchi25@mails.ucas.ac.cn,
tomasz.jeznach@linux.dev, vasant.hegde@amd.com, will@kernel.org,
zong.li@sifive.com
Subject: Re: [PATCH v6 09/10] iommu/riscv: Add dirty tracking support for second-stage domains
Date: Mon, 2 Nov 2026 09:13:56 -0400 [thread overview]
Message-ID: <20261102131356.GA274202@nvidia.com> (raw)
In-Reply-To: <20261102091823.54287-1-gong.shuai@sanechips.com.cn>
On Mon, Nov 02, 2026 at 05:18:23PM +0800, Gong Shuai wrote:
> >@@ -1439,6 +1454,9 @@ static int riscv_iommu_init_domain_s2(struct device *dev,
> > if (domain->gscid < 0)
> > return -ENOMEM;
> >
> >+ if (iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD)
> >+ domain->domain.dirty_ops = &riscv_iommu_dirty_ops;
>
> This sets dirty_ops based on whether the allocating device's IOMMU
> supports AMO_HWAD. As I understand it, the domain/HWPT is not tied
> to that IOMMU instance. A later attach may target a device behind
> another instance without AMO_HWAD, and the attach can still succeed
> with GADE disabled, potentially causing guest page faults.
>
> Shouldn't we therefore revalidate AMO_HWAD cap for domains with
> dirty_ops and reject this combination?
>
> FYI, both AMD and Intel have attach-time dirty-tracking checks. See
> drivers/iommu/intel/iommu.c:3195 and drivers/iommu/amd/iommu.c:3221.
Right, need to check on every domain attach that the domain is
compatible with the iommu instance.
Jason
WARNING: multiple messages have this Message-ID (diff)
From: Jason Gunthorpe <jgg@ziepe.ca>
To: Gong Shuai <gong.shuai@sanechips.com.cn>
Cc: fangyu.yu@linux.alibaba.com, alex@ghiti.fr,
andrew.jones@linux.dev, anup@brainfault.org,
aou@eecs.berkeley.edu, atish.patra@linux.dev,
baolu.lu@linux.intel.com, guoren@kernel.org,
iommu@lists.linux.dev, joerg.roedel@amd.com, joro@8bytes.org,
jroedel@suse.de, kevin.tian@intel.com,
kvm-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, nutty.liu@hotmail.com,
palmer@dabbelt.com, pjw@kernel.org, robin.murphy@arm.com,
skhawaja@google.com, tanchi25@mails.ucas.ac.cn,
tomasz.jeznach@linux.dev, vasant.hegde@amd.com, will@kernel.org,
zong.li@sifive.com
Subject: Re: [PATCH v6 09/10] iommu/riscv: Add dirty tracking support for second-stage domains
Date: Mon, 2 Nov 2026 09:13:56 -0400 [thread overview]
Message-ID: <20261102131356.GA274202@nvidia.com> (raw)
In-Reply-To: <20261102091823.54287-1-gong.shuai@sanechips.com.cn>
On Mon, Nov 02, 2026 at 05:18:23PM +0800, Gong Shuai wrote:
> >@@ -1439,6 +1454,9 @@ static int riscv_iommu_init_domain_s2(struct device *dev,
> > if (domain->gscid < 0)
> > return -ENOMEM;
> >
> >+ if (iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD)
> >+ domain->domain.dirty_ops = &riscv_iommu_dirty_ops;
>
> This sets dirty_ops based on whether the allocating device's IOMMU
> supports AMO_HWAD. As I understand it, the domain/HWPT is not tied
> to that IOMMU instance. A later attach may target a device behind
> another instance without AMO_HWAD, and the attach can still succeed
> with GADE disabled, potentially causing guest page faults.
>
> Shouldn't we therefore revalidate AMO_HWAD cap for domains with
> dirty_ops and reject this combination?
>
> FYI, both AMD and Intel have attach-time dirty-tracking checks. See
> drivers/iommu/intel/iommu.c:3195 and drivers/iommu/amd/iommu.c:3221.
Right, need to check on every domain attach that the domain is
compatible with the iommu instance.
Jason
--
kvm-riscv mailing list
kvm-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/kvm-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Jason Gunthorpe <jgg@ziepe.ca>
To: Gong Shuai <gong.shuai@sanechips.com.cn>
Cc: fangyu.yu@linux.alibaba.com, alex@ghiti.fr,
andrew.jones@linux.dev, anup@brainfault.org,
aou@eecs.berkeley.edu, atish.patra@linux.dev,
baolu.lu@linux.intel.com, guoren@kernel.org,
iommu@lists.linux.dev, joerg.roedel@amd.com, joro@8bytes.org,
jroedel@suse.de, kevin.tian@intel.com,
kvm-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, nutty.liu@hotmail.com,
palmer@dabbelt.com, pjw@kernel.org, robin.murphy@arm.com,
skhawaja@google.com, tanchi25@mails.ucas.ac.cn,
tomasz.jeznach@linux.dev, vasant.hegde@amd.com, will@kernel.org,
zong.li@sifive.com
Subject: Re: [PATCH v6 09/10] iommu/riscv: Add dirty tracking support for second-stage domains
Date: Mon, 2 Nov 2026 09:13:56 -0400 [thread overview]
Message-ID: <20261102131356.GA274202@nvidia.com> (raw)
In-Reply-To: <20261102091823.54287-1-gong.shuai@sanechips.com.cn>
On Mon, Nov 02, 2026 at 05:18:23PM +0800, Gong Shuai wrote:
> >@@ -1439,6 +1454,9 @@ static int riscv_iommu_init_domain_s2(struct device *dev,
> > if (domain->gscid < 0)
> > return -ENOMEM;
> >
> >+ if (iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD)
> >+ domain->domain.dirty_ops = &riscv_iommu_dirty_ops;
>
> This sets dirty_ops based on whether the allocating device's IOMMU
> supports AMO_HWAD. As I understand it, the domain/HWPT is not tied
> to that IOMMU instance. A later attach may target a device behind
> another instance without AMO_HWAD, and the attach can still succeed
> with GADE disabled, potentially causing guest page faults.
>
> Shouldn't we therefore revalidate AMO_HWAD cap for domains with
> dirty_ops and reject this combination?
>
> FYI, both AMD and Intel have attach-time dirty-tracking checks. See
> drivers/iommu/intel/iommu.c:3195 and drivers/iommu/amd/iommu.c:3221.
Right, need to check on every domain attach that the domain is
compatible with the iommu instance.
Jason
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2026-11-02 13:14 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-31 8:30 [PATCH v6 00/10] iommu/riscv: Add hardware dirty tracking for second-stage domains fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` [PATCH v6 01/10] iommu/generic_pt: Fix the RISC-V supported feature mask fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` [PATCH v6 02/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` [PATCH v6 03/10] iommupt: Add RISC-V dirty tracking PTE ops fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` [PATCH v6 04/10] iommu/riscv: use data structure instead of individual values fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` [PATCH v6 05/10] iommu/riscv: support GSCID and GVMA invalidation command fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` [PATCH v6 06/10] RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` [PATCH v6 07/10] iommu/riscv: Add domain_alloc_paging_flags for second-stage domain fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` [PATCH v6 08/10] iommu/riscv: Pre-enable GADE for second-stage domains fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` [PATCH v6 09/10] iommu/riscv: Add dirty tracking support " fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-11-02 9:18 ` Gong Shuai
2026-11-02 9:18 ` Gong Shuai
2026-11-02 9:18 ` Gong Shuai
2026-11-02 13:13 ` Jason Gunthorpe [this message]
2026-11-02 13:13 ` Jason Gunthorpe
2026-11-02 13:13 ` Jason Gunthorpe
2026-11-02 13:21 ` fangyu.yu
2026-11-02 13:21 ` fangyu.yu
2026-11-02 13:21 ` fangyu.yu
2026-10-31 8:30 ` [PATCH v6 10/10] iommu/riscv: Add IOTINVAL.GVMA invalidations fangyu.yu
2026-10-31 8:30 ` fangyu.yu
2026-10-31 8:30 ` fangyu.yu
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