[PATCH 17/74] drm/amd/display: Resolve clk_mgr DPP DTO targets when the sequence is built

[Wayne Lin <Wayne.Lin@amd.com>]

From: Piotr Maziarz <piotr.maziarz@amd.com>

[WHY]
The DCN401 and DCN60 clk_mgr block sequences keep a dc_state pointer
in the DPPCLK DTO step and walk res_ctx, dc->res_pool and the pipe's DPP
when the step executes. The step therefore depends on state outside its
parameters, and on that state still being valid when the sequence runs.

[HOW]
Add clk_mgr_build_dpp_dto_targets(), which records each pipe's DPP instance
and DPP clock while the sequence is built, and clk_mgr_program_dpp_dto(),
which programs them. The step carries the targets instead of the dc_state.
The reference clock stays a pointer into clk_mgr's own clocks, because an
earlier step in the same sequence stores the PMFW-granted DPPCLK there.

Cc: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
---
 .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c  | 46 ++++++++++++++++
 .../dc/clk_mgr/dcn401/dcn401_clk_mgr.c        | 54 ++++---------------
 .../dc/clk_mgr/dcn401/dcn401_clk_mgr.h        |  4 +-
 .../display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c  | 54 ++++---------------
 .../display/dc/clk_mgr/dcn60/dcn60_clk_mgr.h  |  4 +-
 .../amd/display/dc/inc/hw/clk_mgr_internal.h  | 22 ++++++++
 6 files changed, 90 insertions(+), 94 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index bdc755be7bf6..cf1f1c8761c6 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -98,6 +98,52 @@ int clk_mgr_helper_get_active_plane_cnt(
 	return total_plane_count;
 }
 
+void clk_mgr_build_dpp_dto_targets(
+		const struct dc *dc,
+		const struct dc_state *context,
+		bool safe_to_lower,
+		struct clk_mgr_dpp_dto_targets *targets)
+{
+	unsigned int i;
+
+	targets->safe_to_lower = safe_to_lower;
+	targets->count = 0;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		int dppclk_khz = pipe->plane_res.bw.dppclk_khz;
+
+		if (!pipe->plane_res.dpp) {
+			/* A harvested pipe has neither a DPP nor a DPP clock. */
+			ASSERT(dppclk_khz == 0);
+			continue;
+		}
+
+		targets->pipes[targets->count].pipe_idx = i;
+		targets->pipes[targets->count].dpp_inst = pipe->plane_res.dpp->inst;
+		targets->pipes[targets->count].dppclk_khz = dppclk_khz;
+		targets->count++;
+	}
+}
+
+void clk_mgr_program_dpp_dto(
+		struct dccg *dccg,
+		int ref_dppclk_khz,
+		const struct clk_mgr_dpp_dto_targets *targets)
+{
+	unsigned int i;
+
+	dccg->ref_dppclk = ref_dppclk_khz;
+	for (i = 0; i < targets->count; i++) {
+		int dppclk_khz = targets->pipes[i].dppclk_khz;
+
+		/* Unless lowering is safe, only raise over what DCCG last programmed. */
+		if (targets->safe_to_lower ||
+				dccg->pipe_dppclk_khz[targets->pipes[i].pipe_idx] < dppclk_khz)
+			dccg->funcs->update_dpp_dto(dccg, targets->pipes[i].dpp_inst, dppclk_khz);
+	}
+}
+
 void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)
 {
 	struct dc_link *edp_links[MAX_NUM_EDP];
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
index 03aec7f4df7b..d609f77d5298 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -560,40 +560,6 @@ static void dcn401_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr
 	}
 }
 
-static void dcn401_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
-		struct dc_state *context, bool safe_to_lower, int ref_dppclk_khz)
-{
-	uint32_t i;
-
-	clk_mgr->dccg->ref_dppclk = ref_dppclk_khz;
-	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
-		int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;
-
-		dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
-
-		if (context->res_ctx.pipe_ctx[i].plane_res.dpp)
-			dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
-		else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {
-			/* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.
-			 * In this case just continue in loop
-			 */
-			continue;
-		} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {
-			/* The software state is not valid if dpp resource is NULL and
-			 * dppclk_khz > 0.
-			 */
-			ASSERT(false);
-			continue;
-		}
-
-		prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
-
-		if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
-			clk_mgr->dccg->funcs->update_dpp_dto(
-							clk_mgr->dccg, dpp_inst, dppclk_khz);
-	}
-}
-
 static int dcn401_set_hard_min_by_freq_optimized(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, int requested_clk_khz)
 {
 	if (!clk_mgr->smu_present || !dcn401_is_ppclk_dpm_enabled(clk_mgr, clk))
@@ -739,11 +705,9 @@ static void dcn401_execute_block_sequence(struct clk_mgr *clk_mgr_base, unsigned
 					params->indicate_drr_status_params.mod_drr_for_pstate);
 			break;
 		case CLK_MGR401_UPDATE_DPPCLK_DTO:
-			dcn401_update_clocks_update_dpp_dto(
-					clk_mgr_internal,
-					params->update_dppclk_dto_params.context,
-					params->update_dppclk_dto_params.safe_to_lower,
-					*params->update_dppclk_dto_params.ref_dppclk_khz);
+			clk_mgr_program_dpp_dto(clk_mgr_internal->dccg,
+					*params->update_dppclk_dto_params.ref_dppclk_khz,
+					&params->update_dppclk_dto_params.targets);
 			break;
 		case CLK_MGR401_UPDATE_DTBCLK_DTO:
 			dcn401_update_clocks_update_dtb_dto(
@@ -1186,9 +1150,9 @@ static unsigned int dcn401_build_update_display_clocks_sequence(
 	if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
 		if (dppclk_lowered) {
 			/* if clock is being lowered, increase DTO before lowering refclk */
-			block_sequence[num_steps].params.update_dppclk_dto_params.context = context;
 			block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.dppclk_khz;
-			block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;
+			clk_mgr_build_dpp_dto_targets(dc, context, safe_to_lower,
+					&block_sequence[num_steps].params.update_dppclk_dto_params.targets);
 			block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;
 			num_steps++;
 
@@ -1203,9 +1167,9 @@ static unsigned int dcn401_build_update_display_clocks_sequence(
 				block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED;
 				num_steps++;
 
-				block_sequence[num_steps].params.update_dppclk_dto_params.context = context;
 				block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.actual_dppclk_khz;
-				block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;
+				clk_mgr_build_dpp_dto_targets(dc, context, safe_to_lower,
+						&block_sequence[num_steps].params.update_dppclk_dto_params.targets);
 				block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;
 				num_steps++;
 			}
@@ -1225,9 +1189,9 @@ static unsigned int dcn401_build_update_display_clocks_sequence(
 				num_steps++;
 			}
 
-			block_sequence[num_steps].params.update_dppclk_dto_params.context = context;
 			block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.actual_dppclk_khz;
-			block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;
+			clk_mgr_build_dpp_dto_targets(dc, context, safe_to_lower,
+					&block_sequence[num_steps].params.update_dppclk_dto_params.targets);
 			block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;
 			num_steps++;
 		}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
index d4cd69a5a8dd..7f03a30546a2 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
@@ -53,9 +53,9 @@ union dcn401_clk_mgr_block_sequence_params {
 	} indicate_drr_status_params;
 	struct {
 		/* inputs */
-		struct dc_state *context;
+		/* clk_mgr's own clocks; an earlier step may store the PMFW-granted DPPCLK there. */
 		int *ref_dppclk_khz;
-		bool safe_to_lower;
+		struct clk_mgr_dpp_dto_targets targets;
 	} update_dppclk_dto_params;
 	struct {
 		/* inputs */
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
index 4242a4b5c902..6f16bc33b6af 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
@@ -183,40 +183,6 @@ static bool dcn60_check_native_scaling(struct pipe_ctx *pipe)
 	return is_native_scaling;
 }
 
-static void dcn60_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
-	struct dc_state *context, bool safe_to_lower, int ref_dppclk_khz)
-{
-	uint32_t i;
-
-	clk_mgr->dccg->ref_dppclk = ref_dppclk_khz;
-	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
-		int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;
-
-		dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
-
-		if (context->res_ctx.pipe_ctx[i].plane_res.dpp)
-			dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
-		else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {
-			/* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.
-			 * In this case just continue in loop
-			 */
-			continue;
-		} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {
-			/* The software state is not valid if dpp resource is NULL and
-			 * dppclk_khz > 0.
-			 */
-			ASSERT(false);
-			continue;
-		}
-
-		prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
-
-		if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
-			clk_mgr->dccg->funcs->update_dpp_dto(
-				clk_mgr->dccg, dpp_inst, dppclk_khz);
-	}
-}
-
 static int dcn60_set_clock_freq_optimized(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, int requested_clk_khz)
 {
 	if (!clk_mgr->smu_present || !dcn60_is_ppclk_dpm_enabled(clk_mgr, clk))
@@ -383,9 +349,9 @@ static unsigned int dcn60_build_update_display_clocks_sequence(
 	if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
 		if (dppclk_lowered) {
 			/* if clock is being lowered, increase DTO before lowering refclk */
-			block_sequence[num_steps].params.update_dppclk_dto_params.context = context;
 			block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.dppclk_khz;
-			block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;
+			clk_mgr_build_dpp_dto_targets(dc, context, safe_to_lower,
+					&block_sequence[num_steps].params.update_dppclk_dto_params.targets);
 			block_sequence[num_steps].func = CLK_MGR60_UPDATE_DPPCLK_DTO;
 			num_steps++;
 
@@ -396,9 +362,9 @@ static unsigned int dcn60_build_update_display_clocks_sequence(
 				block_sequence[num_steps].func = CLK_MGR60_SET_PPCLK_OPTIMIZED;
 				num_steps++;
 
-				block_sequence[num_steps].params.update_dppclk_dto_params.context = context;
 				block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.actual_dppclk_khz;
-				block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;
+				clk_mgr_build_dpp_dto_targets(dc, context, safe_to_lower,
+						&block_sequence[num_steps].params.update_dppclk_dto_params.targets);
 				block_sequence[num_steps].func = CLK_MGR60_UPDATE_DPPCLK_DTO;
 				num_steps++;
 			}
@@ -412,9 +378,9 @@ static unsigned int dcn60_build_update_display_clocks_sequence(
 				num_steps++;
 			}
 
-			block_sequence[num_steps].params.update_dppclk_dto_params.context = context;
 			block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.actual_dppclk_khz;
-			block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;
+			clk_mgr_build_dpp_dto_targets(dc, context, safe_to_lower,
+					&block_sequence[num_steps].params.update_dppclk_dto_params.targets);
 			block_sequence[num_steps].func = CLK_MGR60_UPDATE_DPPCLK_DTO;
 			num_steps++;
 		}
@@ -1225,11 +1191,9 @@ static void dcn60_execute_block_sequence(struct clk_mgr *clk_mgr_base, unsigned
 					params->indicate_pstate_status_params.alt_ch_enable);
 			break;
 		case CLK_MGR60_UPDATE_DPPCLK_DTO:
-			dcn60_update_clocks_update_dpp_dto(
-					clk_mgr_internal,
-					params->update_dppclk_dto_params.context,
-					params->update_dppclk_dto_params.safe_to_lower,
-					*params->update_dppclk_dto_params.ref_dppclk_khz);
+			clk_mgr_program_dpp_dto(clk_mgr_internal->dccg,
+					*params->update_dppclk_dto_params.ref_dppclk_khz,
+					&params->update_dppclk_dto_params.targets);
 			break;
 		case CLK_MGR60_UPDATE_DTBCLK_DTO:
 			dcn60_update_clocks_update_dtb_dto(
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.h
index 0625f060e8c6..6d96ec8440a2 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.h
@@ -45,9 +45,9 @@ union dcn60_clk_mgr_block_sequence_params {
 	} indicate_pstate_status_params;
 	struct {
 		/* inputs */
-		struct dc_state *context;
+		/* clk_mgr's own clocks; an earlier step may store the PMFW-granted DPPCLK there. */
 		int *ref_dppclk_khz;
-		bool safe_to_lower;
+		struct clk_mgr_dpp_dto_targets targets;
 	} update_dppclk_dto_params;
 	struct {
 		/* inputs */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index 68fd92258e8c..c6c087197f82 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -602,6 +602,28 @@ int clk_mgr_helper_get_active_plane_cnt(
 		struct dc *dc,
 		struct dc_state *context);
 
+/* Per-pipe DPP DTO programming resolved from dc_state when a clock update is built. */
+struct clk_mgr_dpp_dto_targets {
+	bool safe_to_lower;
+	unsigned int count;
+	struct {
+		unsigned int pipe_idx;
+		int dpp_inst;
+		int dppclk_khz;
+	} pipes[MAX_PIPES];
+};
+
+void clk_mgr_build_dpp_dto_targets(
+		const struct dc *dc,
+		const struct dc_state *context,
+		bool safe_to_lower,
+		struct clk_mgr_dpp_dto_targets *targets);
+
+void clk_mgr_program_dpp_dto(
+		struct dccg *dccg,
+		int ref_dppclk_khz,
+		const struct clk_mgr_dpp_dto_targets *targets);
+
 
 
 #endif //__DAL_CLK_MGR_INTERNAL_H__
-- 
2.43.0