[PATCH 49/74] drm/amd/display: Use expanded DMUB-provided SoC BB and IP caps

[Wayne Lin <Wayne.Lin@amd.com>]

From: Ivan Lipski <ivan.lipski@amd.com>

[Why]
Some SoC bounding box and IP capability values must be provided by
VBIOS through DMUB for the display to light up.

[How]
- Pass dml2_configuration_options to get_ip_caps so translators can
  read the DMUB bounding box, and update all implementations.
- Take the urgent bandwidth targets, max outstanding requests, return
  bus width and alternate DRAM carveout size from DMUB when provided.
- Override each IP cap with its DMUB value when provided (non-zero);
  otherwise keep the default.

Cc: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
---
 .../dml21_wrapper/dml21_translation_helper.c  |  2 +-
 .../display/dc/inc/soc_and_ip_translator.h    |  4 +-
 .../dcn401/dcn401_soc_and_ip_translator.c     |  4 +-
 .../dcn42/dcn42_soc_and_ip_translator.c       |  4 +-
 .../dcn42b/dcn42b_soc_and_ip_translator.c     |  4 +-
 .../dcn60/dcn60_soc_and_ip_translator.c       | 96 ++++++++++++++++++-
 6 files changed, 108 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_translation_helper.c
index 2e3ad7152f3f..a7d6ff59870a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_translation_helper.c
@@ -79,7 +79,7 @@ void dml21_populate_dml_init_params(struct dml2_initialize_instance_in_out *dml_
 
 	if (config->use_native_soc_bb_construction) {
 		in_dc->soc_and_ip_translator->translator_funcs->get_soc_bb(&dml_init->soc_bb, in_dc, config);
-		in_dc->soc_and_ip_translator->translator_funcs->get_ip_caps(&dml_init->ip_caps);
+		in_dc->soc_and_ip_translator->translator_funcs->get_ip_caps(&dml_init->ip_caps, config);
 	} else {
 		dml_init->soc_bb = config->external_socbb_ip_params->soc_bb;
 		dml_init->ip_caps = config->external_socbb_ip_params->ip_params;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h b/drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h
index 5dcb9f8f4daf..13d59cc082f0 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h
@@ -13,7 +13,9 @@ struct soc_and_ip_translator_funcs {
 			struct dml2_soc_bb *soc_bb,
 			const struct dc *dc,
 			const struct dml2_configuration_options *config);
-	void (*get_ip_caps)(struct dml2_ip_capabilities *dml_ip_caps);
+	void (*get_ip_caps)(
+			struct dml2_ip_capabilities *dml_ip_caps,
+			const struct dml2_configuration_options *config);
 };
 
 struct soc_and_ip_translator {
diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c
index c3dfcf2a73e3..a0181bbb2865 100644
--- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c
+++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c
@@ -307,8 +307,10 @@ void dcn401_get_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc, const st
 	apply_soc_bb_updates(soc_bb, dc, config);
 }
 
-static void dcn401_get_ip_caps(struct dml2_ip_capabilities *ip_caps)
+static void dcn401_get_ip_caps(struct dml2_ip_capabilities *ip_caps,
+		const struct dml2_configuration_options *config)
 {
+	(void)config;
 	*ip_caps = dml2_dcn401_max_ip_caps;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c
index c6c1b19b7370..0e9fd4d177d3 100644
--- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c
+++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c
@@ -180,8 +180,10 @@ void dcn42_get_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc, const str
 	dcn42_apply_soc_bb_updates(soc_bb, dc, config);
 }
 
-static void dcn42_get_ip_caps(struct dml2_ip_capabilities *ip_caps)
+static void dcn42_get_ip_caps(struct dml2_ip_capabilities *ip_caps,
+		const struct dml2_configuration_options *config)
 {
+	(void)config;
 	*ip_caps = dml2_dcn42_max_ip_caps;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42b/dcn42b_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42b/dcn42b_soc_and_ip_translator.c
index 50669f458e23..e7efca1f0ab1 100644
--- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42b/dcn42b_soc_and_ip_translator.c
+++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42b/dcn42b_soc_and_ip_translator.c
@@ -26,8 +26,10 @@ void dcn42b_get_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc, const st
 	dcn42_apply_soc_bb_updates(soc_bb, dc, config);
 }
 
-static void dcn42b_get_ip_caps(struct dml2_ip_capabilities *ip_caps)
+static void dcn42b_get_ip_caps(struct dml2_ip_capabilities *ip_caps,
+		const struct dml2_configuration_options *config)
 {
+	(void)config;
 	*ip_caps = dml2_dcn42b_max_ip_caps;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn60/dcn60_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn60/dcn60_soc_and_ip_translator.c
index aef527c7584b..f33e818d1b1e 100644
--- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn60/dcn60_soc_and_ip_translator.c
+++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn60/dcn60_soc_and_ip_translator.c
@@ -65,6 +65,19 @@ static void dcn60_update_soc_bb_with_values_from_dmub(struct dml2_soc_bb *soc_bb
 	if (dmub_bb_params->g7_temperature_read_blackout_ns > 0)
 		soc_bb->power_management_parameters.g7_temperature_read_blackout_us =
 				(double) dmub_bb_params->g7_temperature_read_blackout_ns / 1000.0;
+	if (dmub_bb_params->fraction_of_urgent_bandwidth_nominal_target > 0)
+		soc_bb->fraction_of_urgent_bandwidth_nominal_target =
+				(double) dmub_bb_params->fraction_of_urgent_bandwidth_nominal_target / 1000.0;
+	if (dmub_bb_params->fraction_of_urgent_bandwidth_flip_target > 0)
+		soc_bb->fraction_of_urgent_bandwidth_flip_target =
+				(double) dmub_bb_params->fraction_of_urgent_bandwidth_flip_target / 1000.0;
+	if (dmub_bb_params->max_outstanding_reqs > 0)
+		soc_bb->max_outstanding_reqs = dmub_bb_params->max_outstanding_reqs;
+	if (dmub_bb_params->return_bus_width_bytes > 0)
+		soc_bb->return_bus_width_bytes = dmub_bb_params->return_bus_width_bytes;
+	if (dmub_bb_params->alternate_dram_carveout_size_mb > 0)
+		soc_bb->power_management_parameters.alternate_dram_carveout_size_mb =
+				dmub_bb_params->alternate_dram_carveout_size_mb;
 
 	/* populate alt-channel info */
 	for (i = 0; i < 2; i++) {
@@ -141,9 +154,90 @@ static void dcn60_get_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc, co
 
 }
 
-static void dcn60_get_ip_caps(struct dml2_ip_capabilities *ip_caps)
+static void dcn60_update_ip_caps_with_values_from_dmub(struct dml2_ip_capabilities *ip_caps,
+		const struct dml2_configuration_options *config)
+{
+	const struct dmub_soc_bb_params *dmub_ip =
+			(const struct dmub_soc_bb_params *)config->bb_from_dmub;
+
+	if (dmub_ip == NULL)
+		return;
+
+	//only update if value is provided
+	if (dmub_ip->pipe_count > 0)
+		ip_caps->pipe_count = dmub_ip->pipe_count;
+	if (dmub_ip->otg_count > 0)
+		ip_caps->otg_count = dmub_ip->otg_count;
+	if (dmub_ip->num_dsc > 0)
+		ip_caps->num_dsc = dmub_ip->num_dsc;
+	if (dmub_ip->TDLUT_33cube_count > 0)
+		ip_caps->TDLUT_33cube_count = dmub_ip->TDLUT_33cube_count;
+	if (dmub_ip->max_num_dp2p0_streams > 0)
+		ip_caps->max_num_dp2p0_streams = dmub_ip->max_num_dp2p0_streams;
+	if (dmub_ip->max_num_hdmi_frl_outputs > 0)
+		ip_caps->max_num_hdmi_frl_outputs = dmub_ip->max_num_hdmi_frl_outputs;
+	if (dmub_ip->max_num_dp2p0_outputs > 0)
+		ip_caps->max_num_dp2p0_outputs = dmub_ip->max_num_dp2p0_outputs;
+	if (dmub_ip->rob_buffer_size_kbytes > 0)
+		ip_caps->rob_buffer_size_kbytes = dmub_ip->rob_buffer_size_kbytes;
+	if (dmub_ip->config_return_buffer_size_in_kbytes > 0)
+		ip_caps->config_return_buffer_size_in_kbytes =
+				dmub_ip->config_return_buffer_size_in_kbytes;
+	if (dmub_ip->config_return_buffer_segment_size_in_kbytes > 0)
+		ip_caps->config_return_buffer_segment_size_in_kbytes =
+				dmub_ip->config_return_buffer_segment_size_in_kbytes;
+	if (dmub_ip->meta_fifo_size_in_kentries > 0)
+		ip_caps->meta_fifo_size_in_kentries = dmub_ip->meta_fifo_size_in_kentries;
+	if (dmub_ip->compressed_buffer_segment_size_in_kbytes > 0)
+		ip_caps->compressed_buffer_segment_size_in_kbytes =
+				dmub_ip->compressed_buffer_segment_size_in_kbytes;
+	if (dmub_ip->cursor_buffer_size > 0)
+		ip_caps->cursor_buffer_size = dmub_ip->cursor_buffer_size;
+	if (dmub_ip->max_flip_time_us > 0)
+		ip_caps->max_flip_time_us = dmub_ip->max_flip_time_us;
+	if (dmub_ip->max_flip_time_lines > 0)
+		ip_caps->max_flip_time_lines = dmub_ip->max_flip_time_lines;
+	/* 0 is a valid hostvm_mode */
+	ip_caps->hostvm_mode = dmub_ip->hostvm_mode;
+	if (dmub_ip->max_vactive_det_fill_delay_us > 0)
+		ip_caps->max_vactive_det_fill_delay_us = dmub_ip->max_vactive_det_fill_delay_us;
+	if (dmub_ip->ppt_max_allow_delay_us > 0)
+		ip_caps->ppt_max_allow_delay_us = dmub_ip->ppt_max_allow_delay_us;
+	if (dmub_ip->temp_read_max_allow_delay_us > 0)
+		ip_caps->temp_read_max_allow_delay_us = dmub_ip->temp_read_max_allow_delay_us;
+	if (dmub_ip->vblank_nom_default_us > 0)
+		ip_caps->vblank_nom_default_us = dmub_ip->vblank_nom_default_us;
+
+	if (dmub_ip->fams2_max_allow_delay_us > 0)
+		ip_caps->fams2.max_allow_delay_us = dmub_ip->fams2_max_allow_delay_us;
+	if (dmub_ip->fams2_scheduling_delay_us > 0)
+		ip_caps->fams2.scheduling_delay_us = dmub_ip->fams2_scheduling_delay_us;
+	if (dmub_ip->fams2_vertical_interrupt_ack_delay_us > 0)
+		ip_caps->fams2.vertical_interrupt_ack_delay_us =
+				dmub_ip->fams2_vertical_interrupt_ack_delay_us;
+	if (dmub_ip->fams2_allow_programming_delay_us > 0)
+		ip_caps->fams2.allow_programming_delay_us = dmub_ip->fams2_allow_programming_delay_us;
+	if (dmub_ip->fams2_min_allow_width_us > 0)
+		ip_caps->fams2.min_allow_width_us = dmub_ip->fams2_min_allow_width_us;
+	if (dmub_ip->fams2_subvp_df_throttle_delay_us > 0)
+		ip_caps->fams2.subvp_df_throttle_delay_us = dmub_ip->fams2_subvp_df_throttle_delay_us;
+	if (dmub_ip->fams2_subvp_programming_delay_us > 0)
+		ip_caps->fams2.subvp_programming_delay_us = dmub_ip->fams2_subvp_programming_delay_us;
+	if (dmub_ip->fams2_drr_programming_delay_us > 0)
+		ip_caps->fams2.drr_programming_delay_us = dmub_ip->fams2_drr_programming_delay_us;
+	if (dmub_ip->fams2_lock_timeout_us > 0)
+		ip_caps->fams2.lock_timeout_us = dmub_ip->fams2_lock_timeout_us;
+	if (dmub_ip->fams2_recovery_timeout_us > 0)
+		ip_caps->fams2.recovery_timeout_us = dmub_ip->fams2_recovery_timeout_us;
+	if (dmub_ip->fams2_flip_programming_delay_us > 0)
+		ip_caps->fams2.flip_programming_delay_us = dmub_ip->fams2_flip_programming_delay_us;
+}
+
+static void dcn60_get_ip_caps(struct dml2_ip_capabilities *ip_caps,
+		const struct dml2_configuration_options *config)
 {
 	dcn6_test_initialize_ip_caps(ip_caps);
+	dcn60_update_ip_caps_with_values_from_dmub(ip_caps, config);
 }
 
 static struct soc_and_ip_translator_funcs dcn60_translator_funcs = {
-- 
2.43.0