[PATCH 43/74] drm/amd/display: Promote DC to 3.2.406

[Wayne Lin <Wayne.Lin@amd.com>]

From: Taimur Hassan <Syed.Hassan@amd.com>

This version brings along the following updates:
 - Build DCN401 virtual commits and seamless plane updates in DC2, and
   dispatch the hardware span of a commit through dc2_funcs.
 - Add the leaf block-sequence entries a virtual commit needs, and read
   the accelerated-mode bit through a query builder.
 - Resolve watermark policy and the DPP, DTBCLK and DCN401 DENTIST
   targets when the sequence is built.
 - Fix DSC teardown gating in the post-unlock sequence.
 - Move HDMI FRL status polling outside dc_lock and stop it on fini.
 - Relax stutter constraints for DRR streams, including ramless idle,
   track static-screen idle, and enable the relaxation on DCN42. Raise
   the DCN42 DDR5 stutter latency.
 - Let DC_PSR_MASK enable PSR without a DMUB PSR cap.
 - Enable HDCP on DCN6 and the DF C-state vote on DCN42B.
 - Enable SST PCON FRL DSC passthrough and program the correct DP HPO
   APG instance.
 - Exit IPS before checking flip pending, and keep the HPD IRQ reset
   path from taking dc_lock.
 - Skip UPSP programming when the registers are absent, and skip
   visual confirm color programming when firmware owns it.
 - Align DCN42B with DCN42 and extend the IOMMU mismatch workaround to
   DCN42B. Restore the missing DCN6 vtotal cap and vstartup assignment.
 - Update the DMUB interface to 0.1.83.0 with an extended SoC bounding
   box, RAMLESS_LOBF commands, and a seamless-boot eDP request.
 - Initialize the DMUB LSDMA ring, accept a 1932-byte PSP footer, and
   update the default VCO frequency.
 - Fix the FFE link-rate change path and the p-state enable sequence.
   Commit the validated target when a minimal transition cannot be
   built.
 - Various cleanups.

Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 916fa87d0dbc..2dff1b271416 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -69,7 +69,7 @@ struct dcn_dsc_reg_state;
 struct dcn_optc_reg_state;
 struct dcn_dccg_reg_state;
 
-#define DC_VER "3.2.405"
+#define DC_VER "3.2.406"
 
 /**
  * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC
-- 
2.43.0