[PATCH 42/74] drm/amd/display: [FW Promotion] Release 0.1.83.0

[Wayne Lin <Wayne.Lin@amd.com>]

From: Taimur Hassan <Syed.Hassan@amd.com>

Updated DMUB interface
- Extend the SoC bounding box with urgent bandwidth targets, pipe and
  output counts, return-buffer sizes, and FAMS2 delay and timeout values
- Add RAMLESS_LOBF commands to copy static settings and to enable,
  disable, or wake the feature
- Carry a seamless-boot eDP request in the DCN init command

Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
---
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 203 +++++++++++++++++-
 1 file changed, 197 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 8684b1398d4e..c3aa0d0a74be 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -408,6 +408,42 @@ struct dmub_soc_bb_params {
 	uint32_t vmin_limit_dispclk_khz;
 	uint32_t vmin_limit_dcfclk_khz;
 	uint32_t g7_temperature_read_blackout_ns;
+	uint32_t fraction_of_urgent_bandwidth_nominal_target;
+	uint32_t fraction_of_urgent_bandwidth_flip_target;
+	uint32_t max_outstanding_reqs;
+	uint32_t return_bus_width_bytes;
+	uint32_t alternate_dram_carveout_size_mb;
+	uint32_t pipe_count;
+	uint32_t otg_count;
+	uint32_t num_dsc;
+	uint32_t TDLUT_33cube_count;
+	uint32_t max_num_dp2p0_streams;
+	uint32_t max_num_hdmi_frl_outputs;
+	uint32_t max_num_dp2p0_outputs;
+	uint32_t rob_buffer_size_kbytes;
+	uint32_t config_return_buffer_size_in_kbytes;
+	uint32_t config_return_buffer_segment_size_in_kbytes;
+	uint32_t meta_fifo_size_in_kentries;
+	uint32_t compressed_buffer_segment_size_in_kbytes;
+	uint32_t cursor_buffer_size;
+	uint32_t max_flip_time_us;
+	uint32_t max_flip_time_lines;
+	uint32_t hostvm_mode;
+	uint32_t max_vactive_det_fill_delay_us;
+	uint32_t ppt_max_allow_delay_us;
+	uint32_t temp_read_max_allow_delay_us;
+	uint32_t vblank_nom_default_us;
+	uint32_t fams2_max_allow_delay_us;
+	uint32_t fams2_scheduling_delay_us;
+	uint32_t fams2_vertical_interrupt_ack_delay_us;
+	uint32_t fams2_allow_programming_delay_us;
+	uint32_t fams2_min_allow_width_us;
+	uint32_t fams2_subvp_df_throttle_delay_us;
+	uint32_t fams2_subvp_programming_delay_us;
+	uint32_t fams2_drr_programming_delay_us;
+	uint32_t fams2_lock_timeout_us;
+	uint32_t fams2_recovery_timeout_us;
+	uint32_t fams2_flip_programming_delay_us;
 };
 #pragma pack(pop)
 
@@ -1193,7 +1229,7 @@ enum dmub_dc_bls_command_type {
 	 */
 	DMUB_CMD__DC_BLS_DCHVM_INIT = 0,
 	/**
-	 * Runs the fixed DCN hardware init sequence.
+	 * Initializes the DCN hardware.
 	 */
 	DMUB_CMD__DC_BLS_DCN_INIT = 1,
 };
@@ -2071,6 +2107,11 @@ enum dmub_cmd_type {
 	 */
 	DMUB_CMD__NBIF_AZ_PME_RESTORE = 99,
 
+	/**
+	 * Command type use for all RAMLESS_LOBF commands.
+	 */
+	DMUB_CMD__RAMLESS_LOBF = 100,
+
 	/**
 	 * Command type use for VBIOS shared commands.
 	 */
@@ -7732,15 +7773,157 @@ struct dmub_rb_cmd_boot_time_crc_init {
 	struct dmub_cmd_boot_time_crc_init_data data;
 };
 
+enum ramless_lobf_enable_cmd {
+	LOBF_DISABLE            = 0, /**< Disable Ramless LOBF */
+	LOBF_ENABLE             = 1, /**< Enable Ramless LOBF */
+	LOBF_IMMEDIATE_WAKE     = 2, /**< Immediate wake (program_manual_trigger) */
+	LOBF_ENTER_IDLE_SCREEN  = 3, /**< Enter idle screen */
+	LOBF_EXIT_IDLE_SCREEN   = 4, /**< Exit idle screen */
+};
+
+/**
+ * enum ramless_lobf_phy_mode - PHY power-state mode for Ramless LOBF.
+ */
+enum ramless_lobf_phy_mode {
+	LOBF_PHY_MODE_P0_ON     = 0, /**< PHY P0: lanes and PLL fully powered (normal operation) */
+	LOBF_PHY_MODE_P2_PLL_ON = 1, /**< PHY P2: lanes off, PLL still running (shallow sleep) */
+	LOBF_PHY_MODE_P3_PG     = 2, /**< PHY P3: lanes and PLL power-gated (deep sleep) */
+};
+
+/**
+ * enum dmub_cmd_ramless_lobf_type - Sub-command types for DMUB_CMD__RAMLESS_LOBF.
+ */
+enum dmub_cmd_ramless_lobf_type {
+	DMUB_CMD__RAMLESS_LOBF_COPY_SETTINGS = 0, /**< Copy static settings from driver to FW */
+	DMUB_CMD__RAMLESS_LOBF_ENABLE        = 1, /**< Enable or disable Ramless LOBF */
+};
+
+/**
+ * Data passed from driver to FW in a DMUB_CMD__RAMLESS_LOBF_ENABLE command.
+ */
+struct dmub_cmd_ramless_lobf_enable_data {
+	/**
+	 * @enable: 1 to enable LOBF, 0 to disable, 2 to force immediate wake (program_manual_trigger).
+	 */
+	uint8_t enable_command;
+	/**
+	 * @panel_inst: Panel instance index.
+	 */
+	uint8_t panel_inst;
+	/**
+	 * @pad: Align structure to 4-byte boundary.
+	 */
+	uint8_t pad[2];
+
+	uint32_t wake_source;
+};
+
+/**
+ * Definition of a DMUB_CMD__RAMLESS_LOBF_ENABLE command.
+ */
+struct dmub_rb_cmd_ramless_lobf_enable {
+	/**
+	 * Command header.
+	 */
+	struct dmub_cmd_header header;
+	/**
+	 * Data for enable/disable.
+	 */
+	struct dmub_cmd_ramless_lobf_enable_data data;
+};
+
+/**
+ * Data passed from driver to FW in a DMUB_CMD__RAMLESS_LOBF_COPY_SETTINGS command.
+ */
+struct dmub_cmd_ramless_lobf_copy_settings_data {
+	/**
+	 * @panel_inst: Panel instance index.
+	 */
+	uint8_t panel_inst;
+	/**
+	 * @otg_inst: OTG hardware instance.
+	 */
+	uint8_t otg_inst;
+	/**
+	 * @digfe_inst: DIG front-end hardware instance.
+	 */
+	uint8_t digfe_inst;
+	/**
+	 * @digbe_inst: DIG back-end hardware instance.
+	 */
+	uint8_t digbe_inst;
+	/**
+	 * @dpphy_inst: DP PHY hardware instance.
+	 */
+	uint8_t dpphy_inst;
+	/**
+	 * @aux_inst: AUX hardware instance.
+	 */
+	uint8_t aux_inst;
+	/**
+	 * @phy_mode: PHY power-state mode. Use values from enum ramless_lobf_phy_mode.
+	 */
+	uint8_t phy_mode;
+	/**
+	 * @enable_scenarios: Bitmask of enabled scenarios for Ramless LOBF.
+	 */
+	uint8_t enable_scenarios;
+	/**
+	 * @line_time_in_ns: Total length of one horizontal line (active + blanking) in
+	 * nanoseconds.  Used to calculate wake up timer IRQ.
+	 */
+	uint32_t line_time_in_ns;
+	/**
+	 * @vactive: Number of active video lines in the display mode.
+	 */
+	uint32_t vactive;
+
+	uint16_t reserved_0;
+	uint16_t lobf_min_sleep_time_us; /* if < min, then we don't want LOBF to sleep */
+	uint8_t debug_options;
+	uint8_t vmin_force_default_frames;
+	uint8_t visual_confirm;
+	uint8_t reserved[1];
+	/**
+	 * Use for AUX-less ALPM LFPS wake operation
+	 */
+	struct dmub_alpm_auxless_data auxless_alpm_data;
+};
+
+/**
+ * Definition of a DMUB_CMD__RAMLESS_LOBF_COPY_SETTINGS command.
+ */
+struct dmub_rb_cmd_ramless_lobf_copy_settings {
+	/**
+	 * Command header.
+	 */
+	struct dmub_cmd_header header;
+	/**
+	 * Data passed from driver to FW.
+	 */
+	struct dmub_cmd_ramless_lobf_copy_settings_data data;
+};
+
+/**
+ * Data passed from driver to FW in a DMUB_CMD__DC_BLS_DCN_INIT command.
+ */
+struct dmub_cmd_dc_bls_dcn_init_data {
+	/** 1 to keep the boot eDP stream for seamless boot. */
+	uint8_t seamless_boot_edp_requested : 1;
+	/** Reserved. Must be zero. */
+	uint8_t reserved_bits : 7;
+	/** Reserved. Must be zero. */
+	uint8_t reserved[3];
+};
+
 /**
  * Definition of a DMUB_CMD__DC_BLS_DCN_INIT command.
- *
- * Runs a fixed DCN hardware init sequence after the pre-OS to post-OS
- * transition. Carries no payload; anything driver-configurable is
- * programmed by the driver after this command completes.
  */
 struct dmub_rb_cmd_dc_bls_dcn_init {
-	struct dmub_cmd_header header; /**< Command header */
+	/** Command header. */
+	struct dmub_cmd_header header;
+	/** Data passed from driver to FW in a DMUB_CMD__DC_BLS_DCN_INIT command. */
+	struct dmub_cmd_dc_bls_dcn_init_data data;
 };
 
 /**
@@ -8164,6 +8347,14 @@ union dmub_rb_cmd {
 	struct dmub_rb_cmd_panel_polarity_reset panel_polarity_reset;
 
 	struct dmub_rb_cmd_dc_bls_dchvm_init dc_bls_dchvm_init;
+	/**
+	 * Definition of a DMUB_CMD__RAMLESS_LOBF_COPY_SETTINGS command.
+	 */
+	struct dmub_rb_cmd_ramless_lobf_copy_settings ramless_lobf_copy_settings;
+	/**
+	 * Definition of a DMUB_CMD__RAMLESS_LOBF_ENABLE command.
+	 */
+	struct dmub_rb_cmd_ramless_lobf_enable ramless_lobf_enable;
 };
 
 /**
-- 
2.43.0