From: Wayne Lin <Wayne.Lin@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Harry Wentland <harry.wentland@amd.com>,
Leo Li <sunpeng.li@amd.com>,
Aurabindo Pillai <aurabindo.pillai@amd.com>,
Roman Li <roman.li@amd.com>, Wayne Lin <wayne.lin@amd.com>,
Tom Chung <chiahsuan.chung@amd.com>,
"Fangzhi Zuo" <jerry.zuo@amd.com>,
Dan Wheeler <daniel.wheeler@amd.com>, Ray Wu <Ray.Wu@amd.com>,
Ivan Lipski <ivan.lipski@amd.com>, Alex Hung <alex.hung@amd.com>,
James Lin <PingLei.Lin@amd.com>,
Chenyu Chen <Chen-Yu.Chen@amd.com>,
Piotr Maziarz <piotr.maziarz@amd.com>,
Alvin Lee <alvin.lee2@amd.com>
Subject: [PATCH 18/74] drm/amd/display: Resolve clk_mgr DTBCLK DTO targets when the sequence is built
Date: Wed, 11 Nov 2026 09:28:24 +0800 [thread overview]
Message-ID: <20261111014100.3596072-19-Wayne.Lin@amd.com> (raw)
In-Reply-To: <20261111014100.3596072-1-Wayne.Lin@amd.com>
From: Piotr Maziarz <piotr.maziarz@amd.com>
[WHY]
The DTBCLK DTO step of the DCN401 and DCN60 clk_mgr block sequences
keeps a dc_state pointer and, when it executes, walks the state's streams,
looks up each OTG master, decides whether it uses an HPO encoder and reads
its pixel clock parameters. The step also carries an unused pointer to the
reference DTBCLK.
[HOW]
Add clk_mgr_build_dtbclk_dto_target(), which resolves one HPO stream's
clock source, pixel clock parameters, PLL settings and link encoding while
the sequence is built, and clk_mgr_program_dtbclk_dto(), which programs it.
The builders emit one DTBCLK DTO step per HPO stream, and the clk_mgr
sequence capacity grows by MAX_PIPES - 1 to hold them.
The per-ASIC copies of the DTBCLK DTO loop are removed.
Cc: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
---
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 37 +++++++++++++
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 53 +++----------------
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.h | 9 ++--
.../display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c | 53 +++----------------
.../display/dc/clk_mgr/dcn60/dcn60_clk_mgr.h | 6 +--
.../amd/display/dc/inc/hw/clk_mgr_internal.h | 16 ++++++
6 files changed, 73 insertions(+), 101 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index cf1f1c8761c6..28dc3eb3e472 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -144,6 +144,43 @@ void clk_mgr_program_dpp_dto(
}
}
+bool clk_mgr_build_dtbclk_dto_target(
+ const struct dc *dc,
+ struct dc_state *context,
+ const struct dc_stream_state *stream,
+ struct clk_mgr_dtbclk_dto_target *target)
+{
+ struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(&context->res_ctx, stream);
+
+ ASSERT(otg_master);
+ if (!otg_master)
+ return false;
+
+ ASSERT(otg_master->clock_source);
+ ASSERT(otg_master->clock_source->funcs->program_pix_clk);
+ ASSERT(otg_master->stream_res.pix_clk_params.controller_id >= CONTROLLER_ID_D0);
+
+ if (!dc->link_srv->dp_is_128b_132b_signal(otg_master) &&
+ !dc_is_hdmi_frl_signal(otg_master->stream->signal))
+ return false;
+
+ if (otg_master->stream_res.pix_clk_params.controller_id <= CONTROLLER_ID_UNDEFINED)
+ return false;
+
+ target->clock_source = otg_master->clock_source;
+ target->pix_clk_params = otg_master->stream_res.pix_clk_params;
+ target->pll_settings = otg_master->pll_settings;
+ target->encoding = dc->link_srv->dp_get_encoding_format(
+ &otg_master->link_config.dp_link_settings);
+ return true;
+}
+
+void clk_mgr_program_dtbclk_dto(struct clk_mgr_dtbclk_dto_target *target)
+{
+ target->clock_source->funcs->program_pix_clk(target->clock_source,
+ &target->pix_clk_params, target->encoding, &target->pll_settings);
+}
+
void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)
{
struct dc_link *edp_links[MAX_NUM_EDP];
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
index d609f77d5298..0785f70fb535 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -523,43 +523,6 @@ static void dcn401_auto_dpm_test_log(
}
}
-static void dcn401_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
- struct dc_state *context,
- int ref_dtbclk_khz)
-{
- (void)ref_dtbclk_khz;
- int i;
- struct dccg *dccg = clk_mgr->dccg;
- struct pipe_ctx *otg_master;
- bool use_hpo_encoder;
-
-
- for (i = 0; i < context->stream_count; i++) {
- otg_master = resource_get_otg_master_for_stream(
- &context->res_ctx, context->streams[i]);
- ASSERT(otg_master);
- if (!otg_master)
- continue;
-
- ASSERT(otg_master->clock_source);
- ASSERT(otg_master->clock_source->funcs->program_pix_clk);
- ASSERT(otg_master->stream_res.pix_clk_params.controller_id >= CONTROLLER_ID_D0);
-
- use_hpo_encoder = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(otg_master);
- use_hpo_encoder |= dc_is_hdmi_frl_signal(otg_master->stream->signal);
- if (!use_hpo_encoder)
- continue;
-
- if (otg_master->stream_res.pix_clk_params.controller_id > CONTROLLER_ID_UNDEFINED)
- otg_master->clock_source->funcs->program_pix_clk(
- otg_master->clock_source,
- &otg_master->stream_res.pix_clk_params,
- dccg->ctx->dc->link_srv->dp_get_encoding_format(
- &otg_master->link_config.dp_link_settings),
- &otg_master->pll_settings);
- }
-}
-
static int dcn401_set_hard_min_by_freq_optimized(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, int requested_clk_khz)
{
if (!clk_mgr->smu_present || !dcn401_is_ppclk_dpm_enabled(clk_mgr, clk))
@@ -710,10 +673,7 @@ static void dcn401_execute_block_sequence(struct clk_mgr *clk_mgr_base, unsigned
¶ms->update_dppclk_dto_params.targets);
break;
case CLK_MGR401_UPDATE_DTBCLK_DTO:
- dcn401_update_clocks_update_dtb_dto(
- clk_mgr_internal,
- params->update_dtbclk_dto_params.context,
- *params->update_dtbclk_dto_params.ref_dtbclk_khz);
+ clk_mgr_program_dtbclk_dto(¶ms->update_dtbclk_dto_params);
break;
case CLK_MGR401_UPDATE_DENTIST:
dcn401_update_clocks_update_dentist(
@@ -1119,10 +1079,13 @@ static unsigned int dcn401_build_update_display_clocks_sequence(
num_steps++;
/* Update DTO in DCCG */
- block_sequence[num_steps].params.update_dtbclk_dto_params.context = context;
- block_sequence[num_steps].params.update_dtbclk_dto_params.ref_dtbclk_khz = &clk_mgr_base->clks.ref_dtbclk_khz;
- block_sequence[num_steps].func = CLK_MGR401_UPDATE_DTBCLK_DTO;
- num_steps++;
+ for (i = 0; i < context->stream_count; i++) {
+ if (!clk_mgr_build_dtbclk_dto_target(dc, context, context->streams[i],
+ &block_sequence[num_steps].params.update_dtbclk_dto_params))
+ continue;
+ block_sequence[num_steps].func = CLK_MGR401_UPDATE_DTBCLK_DTO;
+ num_steps++;
+ }
}
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
index 7f03a30546a2..a2ba8b665a14 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
@@ -5,7 +5,8 @@
#ifndef __DCN401_CLK_MGR_H_
#define __DCN401_CLK_MGR_H_
-#define DCN401_CLK_MGR_MAX_SEQUENCE_SIZE 30
+/* Leaves room for a DTBCLK DTO step per stream. */
+#define DCN401_CLK_MGR_MAX_SEQUENCE_SIZE (30 + MAX_PIPES - 1)
union dcn401_clk_mgr_block_sequence_params {
struct {
@@ -57,11 +58,7 @@ union dcn401_clk_mgr_block_sequence_params {
int *ref_dppclk_khz;
struct clk_mgr_dpp_dto_targets targets;
} update_dppclk_dto_params;
- struct {
- /* inputs */
- struct dc_state *context;
- int *ref_dtbclk_khz;
- } update_dtbclk_dto_params;
+ struct clk_mgr_dtbclk_dto_target update_dtbclk_dto_params;
struct {
/* inputs */
struct dc_state *context;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
index 6f16bc33b6af..43d1932085b7 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
@@ -208,43 +208,6 @@ static int dcn60_set_clock_freq_optimized(struct clk_mgr_internal *clk_mgr, PPCL
return actual_clk_khz;
}
-static void dcn60_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
- struct dc_state *context,
- int ref_dtbclk_khz)
-{
- (void)ref_dtbclk_khz;
- int i;
- struct dccg *dccg = clk_mgr->dccg;
- struct pipe_ctx *otg_master;
- bool use_hpo_encoder;
-
- for (i = 0; i < context->stream_count; i++) {
- otg_master = resource_get_otg_master_for_stream(
- &context->res_ctx, context->streams[i]);
-
- ASSERT(otg_master);
- if (!otg_master)
- continue;
-
- ASSERT(otg_master->clock_source);
- ASSERT(otg_master->clock_source->funcs->program_pix_clk);
- ASSERT(otg_master->stream_res.pix_clk_params.controller_id >= CONTROLLER_ID_D0);
-
- use_hpo_encoder = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(otg_master);
- use_hpo_encoder |= dc_is_hdmi_frl_signal(otg_master->stream->signal);
- if (!use_hpo_encoder)
- continue;
-
- if (otg_master->stream_res.pix_clk_params.controller_id > CONTROLLER_ID_UNDEFINED)
- otg_master->clock_source->funcs->program_pix_clk(
- otg_master->clock_source,
- &otg_master->stream_res.pix_clk_params,
- dccg->ctx->dc->link_srv->dp_get_encoding_format(
- &otg_master->link_config.dp_link_settings),
- &otg_master->pll_settings);
- }
-}
-
static unsigned int dcn60_build_update_display_clocks_sequence(
struct clk_mgr *clk_mgr_base,
struct dc_state *context,
@@ -316,10 +279,13 @@ static unsigned int dcn60_build_update_display_clocks_sequence(
num_steps++;
/* Update DTO in DCCG */
- block_sequence[num_steps].params.update_dtbclk_dto_params.context = context;
- block_sequence[num_steps].params.update_dtbclk_dto_params.ref_dtbclk_khz = &clk_mgr_base->clks.ref_dtbclk_khz;
- block_sequence[num_steps].func = CLK_MGR60_UPDATE_DTBCLK_DTO;
- num_steps++;
+ for (i = 0; i < context->stream_count; i++) {
+ if (!clk_mgr_build_dtbclk_dto_target(dc, context, context->streams[i],
+ &block_sequence[num_steps].params.update_dtbclk_dto_params))
+ continue;
+ block_sequence[num_steps].func = CLK_MGR60_UPDATE_DTBCLK_DTO;
+ num_steps++;
+ }
}
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
@@ -1196,10 +1162,7 @@ static void dcn60_execute_block_sequence(struct clk_mgr *clk_mgr_base, unsigned
¶ms->update_dppclk_dto_params.targets);
break;
case CLK_MGR60_UPDATE_DTBCLK_DTO:
- dcn60_update_clocks_update_dtb_dto(
- clk_mgr_internal,
- params->update_dtbclk_dto_params.context,
- *params->update_dtbclk_dto_params.ref_dtbclk_khz);
+ clk_mgr_program_dtbclk_dto(¶ms->update_dtbclk_dto_params);
break;
case CLK_MGR60_UPDATE_PSR_WAIT_LOOP:
params->update_psr_wait_loop_params.dmcu->funcs->set_psr_wait_loop(
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.h
index 6d96ec8440a2..bd61817a5ef9 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.h
@@ -49,11 +49,7 @@ union dcn60_clk_mgr_block_sequence_params {
int *ref_dppclk_khz;
struct clk_mgr_dpp_dto_targets targets;
} update_dppclk_dto_params;
- struct {
- /* inputs */
- struct dc_state *context;
- int *ref_dtbclk_khz;
- } update_dtbclk_dto_params;
+ struct clk_mgr_dtbclk_dto_target update_dtbclk_dto_params;
struct {
/* inputs */
struct dc_state *context;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index c6c087197f82..ff43c1814766 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -624,6 +624,22 @@ void clk_mgr_program_dpp_dto(
int ref_dppclk_khz,
const struct clk_mgr_dpp_dto_targets *targets);
+/* DTBCLK DTO programming of one HPO stream, resolved from dc_state when a clock update is built. */
+struct clk_mgr_dtbclk_dto_target {
+ struct clock_source *clock_source;
+ struct pixel_clk_params pix_clk_params;
+ struct pll_settings pll_settings;
+ enum dp_link_encoding encoding;
+};
+
+bool clk_mgr_build_dtbclk_dto_target(
+ const struct dc *dc,
+ struct dc_state *context,
+ const struct dc_stream_state *stream,
+ struct clk_mgr_dtbclk_dto_target *target);
+
+void clk_mgr_program_dtbclk_dto(struct clk_mgr_dtbclk_dto_target *target);
+
#endif //__DAL_CLK_MGR_INTERNAL_H__
--
2.43.0
next prev parent reply other threads:[~2026-11-11 1:41 UTC|newest]
Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-11 1:28 [PATCH 00/74] DC Patches November 16, 2026 Wayne Lin
2026-11-11 1:28 ` [PATCH 01/74] drm/amd/display: Fix elapsed time indentation Wayne Lin
2026-11-11 1:28 ` [PATCH 02/74] drm/amd/display: Correct the forced YCbCr420 comment Wayne Lin
2026-11-11 1:28 ` [PATCH 03/74] drm/amd/display: Remove duplicate block sequence leftovers Wayne Lin
2026-11-11 1:28 ` [PATCH 04/74] drm/amd/display: Skip UPSP programming when UPSP regs are absent Wayne Lin
2026-11-11 1:28 ` [PATCH 05/74] drm/amd/display: Dispatch commit_state_hw through dc2_funcs Wayne Lin
2026-11-11 1:28 ` [PATCH 06/74] drm/amd/display: Add leaf BLS entries for a virtual commit Wayne Lin
2026-11-11 1:28 ` [PATCH 07/74] drm/amd/display: Build the dcn401 virtual commit natively Wayne Lin
2026-11-11 1:28 ` [PATCH 08/74] drm/amd/display: Move HDMI FRL Polling Outside dc_lock Wayne Lin
2026-11-11 1:28 ` [PATCH 09/74] drm/amd/display: Extend the IOMMU mismatch workaround to DCN42B Wayne Lin
2026-11-11 1:28 ` [PATCH 10/74] drm/amd/display: Stop HDMI FRL status polling on fini Wayne Lin
2026-11-12 8:51 ` Eren Özen
2026-11-11 1:28 ` [PATCH 11/74] drm/amd/display: Relax stutter constraints for DRR streams Wayne Lin
2026-11-11 1:28 ` [PATCH 12/74] drm/amd/display: Include Ramless Idle in stutter relaxation Wayne Lin
2026-11-11 1:28 ` [PATCH 13/74] drm/amd/display: Initialize DMUB LSDMA ring buffer Wayne Lin
2026-11-11 1:28 ` [PATCH 14/74] drm/amd/display: Fix FFE test automation link rate change Wayne Lin
2026-11-11 1:28 ` [PATCH 15/74] drm/amd/display: Update indicate pstate enable sequence Wayne Lin
2026-11-11 1:28 ` [PATCH 16/74] drm/amd/display: HWSS Refactor - Watermarks Wayne Lin
2026-11-11 1:28 ` [PATCH 17/74] drm/amd/display: Resolve clk_mgr DPP DTO targets when the sequence is built Wayne Lin
2026-11-11 1:28 ` Wayne Lin [this message]
2026-11-11 1:28 ` [PATCH 19/74] drm/amd/display: Resolve the DCN401 DENTIST divider " Wayne Lin
2026-11-11 1:28 ` [PATCH 20/74] drm/amd/display: Update default VCO frequency Wayne Lin
2026-11-11 1:28 ` [PATCH 21/74] drm/amd/display: commit validated target when minimal transition cannot be built Wayne Lin
2026-11-11 1:28 ` [PATCH 22/74] drm/amd/display: Update DP HPO to use correct APG instance Wayne Lin
2026-11-11 1:28 ` [PATCH 23/74] drm/amd/display: cleanup tiling and address formats Wayne Lin
2026-11-11 1:28 ` [PATCH 24/74] drm/amd/display: Enable SST PCON FRL DSC passthrough Wayne Lin
2026-11-11 1:28 ` [PATCH 25/74] drm/amd/display: Don't let HPD IRQ handler take dc_lock in reset Wayne Lin
2026-11-11 1:28 ` [PATCH 26/74] drm/amd/display: Skip visual confirm color programming when FW owns it Wayne Lin
2026-11-11 1:28 ` [PATCH 27/74] drm/amd/display: Fix Stage Optimizer Parameter Naming Wayne Lin
2026-11-11 1:28 ` [PATCH 28/74] drm/amd/display: Build the dcn401 seamless update in DC2 Wayne Lin
2026-11-11 1:28 ` [PATCH 29/74] drm/amd/display: Read accelerated mode through a query builder Wayne Lin
2026-11-11 1:28 ` [PATCH 30/74] drm/amd/display: Ensure exit IPS before checking flip status Wayne Lin
2026-11-11 1:28 ` [PATCH 31/74] drm/amd/display: Updating missing assignments for DCN6 Wayne Lin
2026-11-11 1:28 ` [PATCH 32/74] drm/amd/display: update dcn42b based on dcn42 Wayne Lin
2026-11-11 1:28 ` [PATCH 33/74] drm/amd/display: Build the kept-plane surface update in DC2 Wayne Lin
2026-11-11 1:28 ` [PATCH 34/74] drm/amd/display: Skip first-enable steps on a kept plane Wayne Lin
2026-11-11 1:28 ` [PATCH 35/74] drm/amd/display: Enable DRR stutter constraint relaxation on DCN42 Wayne Lin
2026-11-11 1:28 ` [PATCH 36/74] drm/amd/display: detect static screen state and propagate Wayne Lin
2026-11-11 1:28 ` [PATCH 37/74] drm/amd/display: Allow DC_PSR_MASK to enable PSR without DMUB PSR cap Wayne Lin
2026-11-11 1:28 ` [PATCH 38/74] drm/amd/display: Fix DSC teardown gating in post-unlock BLS sequence Wayne Lin
2026-11-11 1:28 ` [PATCH 39/74] drm/amd/display: Enable HDCP on DCN6 Wayne Lin
2026-11-11 1:28 ` [PATCH 40/74] drm/amd/display: enable DF C-state vote on DCN42B Wayne Lin
2026-11-11 1:28 ` [PATCH 41/74] drm/amd/display: Increase the DCN42 DDR5 stutter latency Wayne Lin
2026-11-11 1:28 ` [PATCH 42/74] drm/amd/display: [FW Promotion] Release 0.1.83.0 Wayne Lin
2026-11-11 1:28 ` [PATCH 43/74] drm/amd/display: Promote DC to 3.2.406 Wayne Lin
2026-11-11 1:28 ` [PATCH 44/74] drm/amd/display: Fix KUnit tiled EDID size Wayne Lin
2026-11-12 7:17 ` Eren Özen
2026-11-11 1:28 ` [PATCH 45/74] drm/amd/display: fix hubbub read state logging Wayne Lin
2026-11-11 1:28 ` [PATCH 46/74] drm/amd/display: Keep panel power across link-loss retrain Wayne Lin
2026-11-11 1:28 ` [PATCH 47/74] drm/amd/display: Don't shrink zero-area recout in full viewport visual confirm Wayne Lin
2026-11-11 1:28 ` [PATCH 48/74] drm/amd/display: Keep patched HDMI panels on FRL across detect Wayne Lin
2026-11-11 1:28 ` [PATCH 49/74] drm/amd/display: Use expanded DMUB-provided SoC BB and IP caps Wayne Lin
2026-11-11 1:28 ` [PATCH 50/74] drm/amd/display: Only force P-State on first plane if TTU is below WM Wayne Lin
2026-11-11 1:28 ` [PATCH 51/74] drm/amd/display: Program the kept-plane scaler in DC2 Wayne Lin
2026-11-11 1:28 ` [PATCH 52/74] drm/amd/display: Add and remove two MPO planes " Wayne Lin
2026-11-11 1:28 ` [PATCH 53/74] drm/amd/display: Add DC2 state facts and split the builders Wayne Lin
2026-11-11 1:29 ` [PATCH 54/74] drm/amd/display: Program DC2 commit stereo once Wayne Lin
2026-11-11 1:29 ` [PATCH 55/74] drm/amd/display: Read DCN6 SOP constraints from the idle row Wayne Lin
2026-11-11 1:29 ` [PATCH 56/74] drm/amd/display: Use soc_bb hostvm fraction instead of hardcoded value Wayne Lin
2026-11-11 1:29 ` [PATCH 57/74] drm/amd/display: Increase state if dcfclk deep sleep needed exceeds dcfclk Wayne Lin
2026-11-11 1:29 ` [PATCH 58/74] drm/amd/display: Flip dml2_core_utils_get_segment_horizontal_contiguous() Inputs Wayne Lin
2026-11-11 1:29 ` [PATCH 59/74] drm/amd/display: Update DCN6 Calcs Wayne Lin
2026-11-11 1:29 ` [PATCH 60/74] drm/amd/display: Add effective_number_of_dpp parameter Wayne Lin
2026-11-11 1:29 ` [PATCH 61/74] drm/amd/display: Read DRAM channel width from SMU init table Wayne Lin
2026-11-11 1:29 ` [PATCH 62/74] drm/amd/display: Update DCN42B stutter latency to match DCN42 Wayne Lin
2026-11-11 1:29 ` [PATCH 63/74] drm/amd/display: Expect VRAM|GTT for the DMUB framebuffer Wayne Lin
2026-11-12 7:17 ` Eren Özen
2026-11-11 1:29 ` [PATCH 64/74] drm/amd/display: Report QoS latency bounds and request Wayne Lin
2026-11-11 1:29 ` [PATCH 65/74] drm/amd/display: Bypass chroma upsampling without the DPP cap Wayne Lin
2026-11-11 1:29 ` [PATCH 66/74] drm/amd/display: Limit VRAM aperture retrieval to DCN6 Wayne Lin
2026-11-11 1:29 ` [PATCH 67/74] drm/amd/display: Make DPP_PG_CONTROL and HUBP_PG_CONTROL BLS compliant Wayne Lin
2026-11-11 1:29 ` [PATCH 68/74] drm/amd/display: Seed boot clocks to avoid lowering pre-OS display clocks Wayne Lin
2026-11-11 1:29 ` [PATCH 69/74] drm/amd/display: Account for split pipe overlap in alt channel copy size Wayne Lin
2026-11-11 1:29 ` [PATCH 70/74] drm/amd/display: Get OPP heads and DPP pipes by stream in dc_resource Wayne Lin
2026-11-11 1:29 ` [PATCH 71/74] drm/amd/display: Program ODM 2:1 and 3:1 on one stream in DC2 Wayne Lin
2026-11-11 1:29 ` [PATCH 72/74] drm/amd/display: Enable Replay timing sync by default Wayne Lin
2026-11-11 1:29 ` [PATCH 73/74] drm/amd/display: [FW Promotion] Release 0.1.84.0 Wayne Lin
2026-11-11 1:29 ` [PATCH 74/74] drm/amd/display: Promote DC to 3.2.407 Wayne Lin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20261111014100.3596072-19-Wayne.Lin@amd.com \
--to=wayne.lin@amd.com \
--cc=Chen-Yu.Chen@amd.com \
--cc=PingLei.Lin@amd.com \
--cc=Ray.Wu@amd.com \
--cc=alex.hung@amd.com \
--cc=alvin.lee2@amd.com \
--cc=amd-gfx@lists.freedesktop.org \
--cc=aurabindo.pillai@amd.com \
--cc=chiahsuan.chung@amd.com \
--cc=daniel.wheeler@amd.com \
--cc=harry.wentland@amd.com \
--cc=ivan.lipski@amd.com \
--cc=jerry.zuo@amd.com \
--cc=piotr.maziarz@amd.com \
--cc=roman.li@amd.com \
--cc=sunpeng.li@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.