[PATCH 1/4] target/i386: Add TSA variant TSA-FILL

[PATCH 1/4] target/i386: Add TSA variant TSA-FILL

[Ben Cheatham]

Add tsa-fill-no feature bit to cpuid 0x80000021.ECX. This feature bit
indicates that the CPU is not vulnerable to TSA-FILL.

All Zen architectures other than Zen5 (EPYC-Turin) are not susceptible
to TSA-FILL.

Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
 target/i386/cpu.c | 2 +-
 target/i386/cpu.h | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e5ffb10d1565..f047fe8a90a7 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1453,7 +1453,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
         .type = CPUID_FEATURE_WORD,
         .feat_names = {
             NULL, "tsa-sq-no", "tsa-l1-no", NULL,
-            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, "tsa-fill-no",
             NULL, NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 641f3ee5c2fd..fe91a0255b6d 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1228,6 +1228,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
 #define CPUID_8000_0021_ECX_TSA_SQ_NO  (1U << 1)
 /* CPU is not vulnerable TSA SA-L1 attack */
 #define CPUID_8000_0021_ECX_TSA_L1_NO  (1U << 2)
+/* CPU is not vulnerable TSA FILL attack */
+#define CPUID_8000_0021_ECX_TSA_FILL_NO (1U << 7)
 
 /* Performance Monitoring Version 2 */
 #define CPUID_8000_0022_EAX_PERFMON_V2  (1U << 0)
-- 
2.53.0

[PATCH 2/4] target/i386: Add EPYC-Milan-v5 Model

[Ben Cheatham]

Add a new version of the EPYC-Milan model with the verw-clear
feature set. This feature is used to mitigate the TSA L1, SQ,
and FILL variants.

Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
 target/i386/cpu.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f047fe8a90a7..85745d5f907c 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6958,6 +6958,16 @@ static const X86CPUDefinition builtin_x86_defs[] = {
                 },
                 .cache_info = &epyc_milan_v3_cache_info
             },
+            {
+                .version = 5,
+                .props = (PropValue[]) {
+                    { "verw-clear", "on" },
+                    { "model-id",
+                      "AMD EPYC-Milan-v5 Processor" },
+                    { /* end of list */ }
+                },
+                .cache_info = &epyc_milan_v3_cache_info
+            },
             { /* end of list */ }
         }
     },
-- 
2.53.0

[PATCH 3/4] target/i386: Add EPYC-Genoa-v4 Model

[Ben Cheatham]

Add a new version of the EPYC-Genoa model with the verw-clear feature
set. This feature is used to mitigate the TSA L1, SQ, and FILL
variants.

Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
 target/i386/cpu.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 85745d5f907c..f80dd98d3ebd 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7075,6 +7075,16 @@ static const X86CPUDefinition builtin_x86_defs[] = {
                 },
                 .cache_info = &epyc_genoa_v2_cache_info
             },
+            {
+                .version = 4,
+                .props = (PropValue[]) {
+                    { "verw-clear", "on" },
+                    { "model-id",
+                      "AMD EPYC-Genoa-v4 Processor" },
+                    { /* end of list */ }
+                },
+                .cache_info = &epyc_genoa_v2_cache_info
+            },
             { /* end of list */ }
         }
     },
-- 
2.53.0

[PATCH 4/4] target/i386: Add EPYC-Turin-v3 Model

[Ben Cheatham]

Add a new version of the EPYC-Turin model with the verw-clear feature
set. This feature is used for TSA attack vector mitigations.

Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
 target/i386/cpu.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f80dd98d3ebd..c0cf782e8aca 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7327,6 +7327,16 @@ static const X86CPUDefinition builtin_x86_defs[] = {
                 },
                 .cache_info = &epyc_turin_cache_info
             },
+            {
+                .version = 3,
+                .props = (PropValue[]) {
+                    { "verw-clear", "on" },
+                    { "model-id",
+                      "AMD EPYC-Turin-v3 Processor" },
+                    { /* end of list */ }
+                },
+                .cache_info = &epyc_turin_cache_info
+            },
             { /* end of list */ }
         }
     },
-- 
2.53.0