[PATCH 0/4] Update TSA mitigations for Zen3+

[PATCH 0/4] Update TSA mitigations for Zen3+

[Ben Cheatham]

This set adds new model versions for Zen3 (EPYC-Milan) through Zen5
(EPYC-Turin) to bring TSA mitigations up to date. This is done in two
parts:

	1. Add a definition for the new TSA-FILL variant (Patch 1)

		Only Zen5 is vulnerable to this TSA variant. QEMU invocations for 
		Zen3 and Zen4 may add "+tsa-fill-no" to the "-cpu" argument to
		set this feature bit.

		This bit is not set by default because it's not supported
		by SEV firmware on Zen3 and Zen4. If you try to start a SEV-SNP
		VM with this bit set the guest will fail to boot due to the
		firmware rejecting the modified CPUID page.

	2. Set the "verw-clear" feature bit for Zen3 through Zen5
	(Patches 2, 3, and 4)

		This bit is used to mitigate the TSA-L1 and TSA-SQ vectors on
		Zen3 and Zen4, and the TSA-FILL variant on Zen5. The definition
		for verw-clear was already in place, but unused. This set
		rectifies that by setting the verw-clear bit in an updated model
		for Zen3, 4, and 5.

		Updated microcode is required for Zen5. Any revision later than
		0xb002175 for Turin Classic or 0x0B101066 for Turin Dense will
		work. Updated microcode is available in the latest PI release
		or from linux-firmware.

		Updated microcode has been available for Zen3 & Zen4 for a
		while, but there is a revision check performed by the Linux
		kernel. If QEMU is complaining about the "verw-clear" bit being
		missing, please update to the latest PI release or microcode in
		linux-firmware.

Linux kernel support for these changes was just merged, see [1].

Quick note: This set conflicts with the Venice & Turin v3 model I sent out
a few weeks ago[2]. The only conflicting portion is the Turin model patch,
either that patch's number can be bumped to v4 or the two patches can be
merged if both sets are picked up at the same time.

[1]:
Link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=cf27412f19c9cc5909b9107cd1b3f4ab7608e362
[2]:
Link: https://lore.kernel.org/qemu-devel/20261029195623.2209-1-Benjamin.Cheatham@amd.com/

Thanks,
Ben

Ben Cheatham (4):
  target/i386: Add TSA attack variant TSA-FILL
  target/i386: Add EPYC-Milan-v5 Model
  target/i386: Add EPYC-Genoa-v4 Model
  target/i386: Add EPYC-Turin-v3 Model

 target/i386/cpu.c | 32 +++++++++++++++++++++++++++++++-
 target/i386/cpu.h |  2 ++
 2 files changed, 33 insertions(+), 1 deletion(-)

base-commit: fd7ab698c921

-- 
2.53.0

[PATCH 1/4] target/i386: Add TSA variant TSA-FILL

[Ben Cheatham]

Add tsa-fill-no feature bit to cpuid 0x80000021.ECX. This feature bit
indicates that the CPU is not vulnerable to TSA-FILL.

All Zen architectures other than Zen5 (EPYC-Turin) are not susceptible
to TSA-FILL.

Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
 target/i386/cpu.c | 2 +-
 target/i386/cpu.h | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e5ffb10d1565..f047fe8a90a7 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1453,7 +1453,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
         .type = CPUID_FEATURE_WORD,
         .feat_names = {
             NULL, "tsa-sq-no", "tsa-l1-no", NULL,
-            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, "tsa-fill-no",
             NULL, NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 641f3ee5c2fd..fe91a0255b6d 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1228,6 +1228,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
 #define CPUID_8000_0021_ECX_TSA_SQ_NO  (1U << 1)
 /* CPU is not vulnerable TSA SA-L1 attack */
 #define CPUID_8000_0021_ECX_TSA_L1_NO  (1U << 2)
+/* CPU is not vulnerable TSA FILL attack */
+#define CPUID_8000_0021_ECX_TSA_FILL_NO (1U << 7)
 
 /* Performance Monitoring Version 2 */
 #define CPUID_8000_0022_EAX_PERFMON_V2  (1U << 0)
-- 
2.53.0

[PATCH 2/4] target/i386: Add EPYC-Milan-v5 Model

[Ben Cheatham]

Add a new version of the EPYC-Milan model with the verw-clear
feature set. This feature is used to mitigate the TSA L1, SQ,
and FILL variants.

Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
 target/i386/cpu.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f047fe8a90a7..85745d5f907c 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6958,6 +6958,16 @@ static const X86CPUDefinition builtin_x86_defs[] = {
                 },
                 .cache_info = &epyc_milan_v3_cache_info
             },
+            {
+                .version = 5,
+                .props = (PropValue[]) {
+                    { "verw-clear", "on" },
+                    { "model-id",
+                      "AMD EPYC-Milan-v5 Processor" },
+                    { /* end of list */ }
+                },
+                .cache_info = &epyc_milan_v3_cache_info
+            },
             { /* end of list */ }
         }
     },
-- 
2.53.0

[PATCH 3/4] target/i386: Add EPYC-Genoa-v4 Model

[Ben Cheatham]

Add a new version of the EPYC-Genoa model with the verw-clear feature
set. This feature is used to mitigate the TSA L1, SQ, and FILL
variants.

Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
 target/i386/cpu.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 85745d5f907c..f80dd98d3ebd 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7075,6 +7075,16 @@ static const X86CPUDefinition builtin_x86_defs[] = {
                 },
                 .cache_info = &epyc_genoa_v2_cache_info
             },
+            {
+                .version = 4,
+                .props = (PropValue[]) {
+                    { "verw-clear", "on" },
+                    { "model-id",
+                      "AMD EPYC-Genoa-v4 Processor" },
+                    { /* end of list */ }
+                },
+                .cache_info = &epyc_genoa_v2_cache_info
+            },
             { /* end of list */ }
         }
     },
-- 
2.53.0

[PATCH 4/4] target/i386: Add EPYC-Turin-v3 Model

[Ben Cheatham]

Add a new version of the EPYC-Turin model with the verw-clear feature
set. This feature is used for TSA attack vector mitigations.

Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
 target/i386/cpu.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f80dd98d3ebd..c0cf782e8aca 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7327,6 +7327,16 @@ static const X86CPUDefinition builtin_x86_defs[] = {
                 },
                 .cache_info = &epyc_turin_cache_info
             },
+            {
+                .version = 3,
+                .props = (PropValue[]) {
+                    { "verw-clear", "on" },
+                    { "model-id",
+                      "AMD EPYC-Turin-v3 Processor" },
+                    { /* end of list */ }
+                },
+                .cache_info = &epyc_turin_cache_info
+            },
             { /* end of list */ }
         }
     },
-- 
2.53.0