From: Damien Le Moal <dlemoal@kernel.org>
To: "Niklas Cassel" <cassel@kernel.org>,
"Jingoo Han" <jingoohan1@gmail.com>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>
Cc: Wilfred Mallawa <wilfred.mallawa@wdc.com>,
Laszlo Fiat <laszlo.fiat@proton.me>,
linux-pci@vger.kernel.org
Subject: Re: [PATCH 3/4] PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link up
Date: Wed, 11 Jun 2025 21:35:27 +0900 [thread overview]
Message-ID: <32c601d5-629b-442e-8b72-0cb6a8fd6500@kernel.org> (raw)
In-Reply-To: <20250611105140.1639031-9-cassel@kernel.org>
On 6/11/25 19:51, Niklas Cassel wrote:
> As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link speeds
> greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link
> training completes before sending a Configuration Request.
>
> Add this delay in dw_pcie_wait_for_link(), after the link is reported as
> up. The delay will only be performed in the success case where the link
> came up.
>
> DWC glue drivers that have a link up IRQ (drivers that set
> use_linkup_irq = true) do not call dw_pcie_wait_for_link(), instead they
> perform this delay in their threaded link up IRQ handler.
>
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
--
Damien Le Moal
Western Digital Research
next prev parent reply other threads:[~2025-06-11 12:35 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-11 10:51 [PATCH 0/4] PCI: dwc: Do not enumerate bus before endpoint devices are ready Niklas Cassel
2025-06-11 10:51 ` Niklas Cassel
2025-06-11 10:51 ` [PATCH 1/4] PCI: dw-rockchip: " Niklas Cassel
2025-06-11 10:51 ` Niklas Cassel
2025-06-11 12:33 ` Damien Le Moal
2025-06-11 12:33 ` Damien Le Moal
2025-06-11 21:14 ` Bjorn Helgaas
2025-06-11 21:14 ` Bjorn Helgaas
2025-06-12 11:19 ` Niklas Cassel
2025-06-12 11:19 ` Niklas Cassel
2025-06-12 11:38 ` Bjorn Helgaas
2025-06-12 11:38 ` Bjorn Helgaas
2025-06-12 11:40 ` Niklas Cassel
2025-06-12 11:40 ` Niklas Cassel
2025-06-12 12:21 ` Bjorn Helgaas
2025-06-12 12:21 ` Bjorn Helgaas
2025-06-12 13:00 ` Manivannan Sadhasivam
2025-06-12 13:00 ` Manivannan Sadhasivam
2025-06-12 14:44 ` Bjorn Helgaas
2025-06-12 14:44 ` Bjorn Helgaas
2025-06-12 15:03 ` Manivannan Sadhasivam
2025-06-12 15:03 ` Manivannan Sadhasivam
2025-06-12 15:24 ` Bjorn Helgaas
2025-06-12 15:24 ` Bjorn Helgaas
2025-06-12 16:51 ` Manivannan Sadhasivam
2025-06-12 16:51 ` Manivannan Sadhasivam
2025-06-11 10:51 ` [PATCH 2/4] PCI: qcom: " Niklas Cassel
2025-06-11 12:34 ` Damien Le Moal
2025-06-11 10:51 ` [PATCH 3/4] PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link up Niklas Cassel
2025-06-11 12:35 ` Damien Le Moal [this message]
2025-06-11 10:51 ` [PATCH 4/4] PCI: dwc: Reduce LINK_WAIT_SLEEP_MS Niklas Cassel
2025-06-11 12:38 ` Damien Le Moal
2025-06-11 12:45 ` Niklas Cassel
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