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From: Damien Le Moal <dlemoal@kernel.org>
To: "Niklas Cassel" <cassel@kernel.org>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Krishna chaitanya chundru" <quic_krichai@quicinc.com>
Cc: Wilfred Mallawa <wilfred.mallawa@wdc.com>,
	Laszlo Fiat <laszlo.fiat@proton.me>,
	linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH 2/4] PCI: qcom: Do not enumerate bus before endpoint devices are ready
Date: Wed, 11 Jun 2025 21:34:46 +0900	[thread overview]
Message-ID: <3d745c75-5f41-46ff-a276-cc9b8be84dc3@kernel.org> (raw)
In-Reply-To: <20250611105140.1639031-8-cassel@kernel.org>

On 6/11/25 19:51, Niklas Cassel wrote:
> Commit 36971d6c5a9a ("PCI: qcom: Don't wait for link if we can detect Link
> Up") changed so that we no longer call dw_pcie_wait_for_link(), and instead
> enumerate the bus directly after receiving the Link Up IRQ.
> 
> This means that there is no longer any delay between link up and the bus
> getting enumerated.
> 
> As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link speeds
> greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link
> training completes before sending a Configuration Request.
> 
> Add this delay in the threaded link up IRQ handler in order to satisfy
> the requirements of the PCIe spec.
> 
> Fixes: 36971d6c5a9a ("PCI: qcom: Don't wait for link if we can detect Link Up")
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index c789e3f85655..0a627f3b5e2c 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1565,6 +1565,13 @@ static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data)
>  
>  	if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) {
>  		dev_dbg(dev, "Received Link up event. Starting enumeration!\n");

Same comment here as for the dw-rockchip. Sleep before printing the message ?

> +		/*
> +		 * As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports
> +		 * Link speeds greater than 5.0 GT/s, software must wait a
> +		 * minimum of 100 ms after Link training completes before
> +		 * sending a Configuration Request.
> +		 */
> +		msleep(PCIE_T_RRS_READY_MS);
>  		/* Rescan the bus to enumerate endpoint devices */
>  		pci_lock_rescan_remove();
>  		pci_rescan_bus(pp->bridge->bus);

Either way,

Reviewed-by: Damien Le Moal <dlemoal@kernel.org>

-- 
Damien Le Moal
Western Digital Research

  reply	other threads:[~2025-06-11 12:34 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-11 10:51 [PATCH 0/4] PCI: dwc: Do not enumerate bus before endpoint devices are ready Niklas Cassel
2025-06-11 10:51 ` Niklas Cassel
2025-06-11 10:51 ` [PATCH 1/4] PCI: dw-rockchip: " Niklas Cassel
2025-06-11 10:51   ` Niklas Cassel
2025-06-11 12:33   ` Damien Le Moal
2025-06-11 12:33     ` Damien Le Moal
2025-06-11 21:14   ` Bjorn Helgaas
2025-06-11 21:14     ` Bjorn Helgaas
2025-06-12 11:19     ` Niklas Cassel
2025-06-12 11:19       ` Niklas Cassel
2025-06-12 11:38       ` Bjorn Helgaas
2025-06-12 11:38         ` Bjorn Helgaas
2025-06-12 11:40         ` Niklas Cassel
2025-06-12 11:40           ` Niklas Cassel
2025-06-12 12:21           ` Bjorn Helgaas
2025-06-12 12:21             ` Bjorn Helgaas
2025-06-12 13:00             ` Manivannan Sadhasivam
2025-06-12 13:00               ` Manivannan Sadhasivam
2025-06-12 14:44               ` Bjorn Helgaas
2025-06-12 14:44                 ` Bjorn Helgaas
2025-06-12 15:03                 ` Manivannan Sadhasivam
2025-06-12 15:03                   ` Manivannan Sadhasivam
2025-06-12 15:24                   ` Bjorn Helgaas
2025-06-12 15:24                     ` Bjorn Helgaas
2025-06-12 16:51                     ` Manivannan Sadhasivam
2025-06-12 16:51                       ` Manivannan Sadhasivam
2025-06-11 10:51 ` [PATCH 2/4] PCI: qcom: " Niklas Cassel
2025-06-11 12:34   ` Damien Le Moal [this message]
2025-06-11 10:51 ` [PATCH 3/4] PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link up Niklas Cassel
2025-06-11 12:35   ` Damien Le Moal
2025-06-11 10:51 ` [PATCH 4/4] PCI: dwc: Reduce LINK_WAIT_SLEEP_MS Niklas Cassel
2025-06-11 12:38   ` Damien Le Moal
2025-06-11 12:45     ` Niklas Cassel
  -- strict thread matches above, loose matches on Subject: below --
2025-05-05  9:26 [PATCH 0/4] PCI: dwc: Link Up IRQ fixes Niklas Cassel
2025-05-05  9:26 ` [PATCH 2/4] PCI: qcom: Do not enumerate bus before endpoint devices are ready Niklas Cassel

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