From: Paul Walmsley <pjw@kernel.org>
To: Guodong Xu <docular.xu@gmail.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
Shuah Khan <skhan@linuxfoundation.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, Zong Li <zong.li@sifive.com>,
Deepak Gupta <debug@rivosinc.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atish.patra@linux.dev>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Yixun Lan <dlan@kernel.org>,
Chen Wang <unicorn_wang@outlook.com>,
Inochi Amaoto <inochiama@gmail.com>,
Chen Wang <chen.wang@linux.dev>,
linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org,
Paul Walmsley <paul.walmsley@sifive.com>,
Conor Dooley <conor@kernel.org>,
Jesse Taube <jtaubepe@redhat.com>,
Charlie Jenkins <thecharlesjenkins@gmail.com>,
Andrew Jones <andrew.jones@oss.qualcomm.com>,
devicetree@vger.kernel.org, spacemit@lists.linux.dev,
sophgo@lists.linux.dev, linux-kselftest@vger.kernel.org,
Jesse Taube <jesse@rivosinc.com>,
Conor Dooley <conor.dooley@microchip.com>,
Charlie Jenkins <charlie@rivosinc.com>,
Andy Chiu <andybnac@gmail.com>
Subject: Re: [PATCH v5 05/17] riscv: Add Zicclsm to cpufeature and hwprobe
Date: Thu, 6 Aug 2026 12:31:28 -0600 (MDT) [thread overview]
Message-ID: <3cb41566-deea-689b-c445-2226d7f3f25a@kernel.org> (raw)
In-Reply-To: <20260701-rva23u64-hwprobe-v2-v5-5-2c61f94a695a@gmail.com>
On Wed, 1 Jul 2026, Guodong Xu wrote:
> From: Jesse Taube <jesse@rivosinc.com>
>
> Zicclsm requires misaligned support for all regular load and store
> instructions, both scalar and vector, but not AMOs or other
> specialized forms of memory access, to main memory regions with both
> the cacheability and coherence PMAs, as defined in the profiles spec.
> Even though mandated, misaligned loads and stores might execute
> extremely slowly. Standard software distributions should assume their
> existence only for correctness, not for performance.
>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Andy Chiu <andy.chiu@sifive.com>
> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
> Tested-by: Charlie Jenkins <charlie@rivosinc.com>
> Signed-off-by: Jesse Taube <jesse@rivosinc.com>
> [Rebased, rewrote doc text, minor commit message revisions]
> Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> Signed-off-by: Guodong Xu <docular.xu@gmail.com>
Thanks, queued for v7.3.
- Paul
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Paul Walmsley <pjw@kernel.org>
To: Guodong Xu <docular.xu@gmail.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
Shuah Khan <skhan@linuxfoundation.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, Zong Li <zong.li@sifive.com>,
Deepak Gupta <debug@rivosinc.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atish.patra@linux.dev>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Yixun Lan <dlan@kernel.org>,
Chen Wang <unicorn_wang@outlook.com>,
Inochi Amaoto <inochiama@gmail.com>,
Chen Wang <chen.wang@linux.dev>,
linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org,
Paul Walmsley <paul.walmsley@sifive.com>,
Conor Dooley <conor@kernel.org>,
Jesse Taube <jtaubepe@redhat.com>,
Charlie Jenkins <thecharlesjenkins@gmail.com>,
Andrew Jones <andrew.jones@oss.qualcomm.com>,
devicetree@vger.kernel.org, spacemit@lists.linux.dev,
sophgo@lists.linux.dev, linux-kselftest@vger.kernel.org,
Jesse Taube <jesse@rivosinc.com>,
Conor Dooley <conor.dooley@microchip.com>,
Charlie Jenkins <charlie@rivosinc.com>,
Andy Chiu <andybnac@gmail.com>
Subject: Re: [PATCH v5 05/17] riscv: Add Zicclsm to cpufeature and hwprobe
Date: Thu, 6 Aug 2026 12:31:28 -0600 (MDT) [thread overview]
Message-ID: <3cb41566-deea-689b-c445-2226d7f3f25a@kernel.org> (raw)
In-Reply-To: <20260701-rva23u64-hwprobe-v2-v5-5-2c61f94a695a@gmail.com>
On Wed, 1 Jul 2026, Guodong Xu wrote:
> From: Jesse Taube <jesse@rivosinc.com>
>
> Zicclsm requires misaligned support for all regular load and store
> instructions, both scalar and vector, but not AMOs or other
> specialized forms of memory access, to main memory regions with both
> the cacheability and coherence PMAs, as defined in the profiles spec.
> Even though mandated, misaligned loads and stores might execute
> extremely slowly. Standard software distributions should assume their
> existence only for correctness, not for performance.
>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Andy Chiu <andy.chiu@sifive.com>
> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
> Tested-by: Charlie Jenkins <charlie@rivosinc.com>
> Signed-off-by: Jesse Taube <jesse@rivosinc.com>
> [Rebased, rewrote doc text, minor commit message revisions]
> Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> Signed-off-by: Guodong Xu <docular.xu@gmail.com>
Thanks, queued for v7.3.
- Paul
WARNING: multiple messages have this Message-ID (diff)
From: Paul Walmsley <pjw@kernel.org>
To: Guodong Xu <docular.xu@gmail.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
Shuah Khan <skhan@linuxfoundation.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, Zong Li <zong.li@sifive.com>,
Deepak Gupta <debug@rivosinc.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atish.patra@linux.dev>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Yixun Lan <dlan@kernel.org>,
Chen Wang <unicorn_wang@outlook.com>,
Inochi Amaoto <inochiama@gmail.com>,
Chen Wang <chen.wang@linux.dev>,
linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org,
Paul Walmsley <paul.walmsley@sifive.com>,
Conor Dooley <conor@kernel.org>,
Jesse Taube <jtaubepe@redhat.com>,
Charlie Jenkins <thecharlesjenkins@gmail.com>,
Andrew Jones <andrew.jones@oss.qualcomm.com>,
devicetree@vger.kernel.org, spacemit@lists.linux.dev,
sophgo@lists.linux.dev, linux-kselftest@vger.kernel.org,
Jesse Taube <jesse@rivosinc.com>,
Conor Dooley <conor.dooley@microchip.com>,
Charlie Jenkins <charlie@rivosinc.com>,
Andy Chiu <andybnac@gmail.com>
Subject: Re: [PATCH v5 05/17] riscv: Add Zicclsm to cpufeature and hwprobe
Date: Thu, 6 Aug 2026 12:31:28 -0600 (MDT) [thread overview]
Message-ID: <3cb41566-deea-689b-c445-2226d7f3f25a@kernel.org> (raw)
In-Reply-To: <20260701-rva23u64-hwprobe-v2-v5-5-2c61f94a695a@gmail.com>
On Wed, 1 Jul 2026, Guodong Xu wrote:
> From: Jesse Taube <jesse@rivosinc.com>
>
> Zicclsm requires misaligned support for all regular load and store
> instructions, both scalar and vector, but not AMOs or other
> specialized forms of memory access, to main memory regions with both
> the cacheability and coherence PMAs, as defined in the profiles spec.
> Even though mandated, misaligned loads and stores might execute
> extremely slowly. Standard software distributions should assume their
> existence only for correctness, not for performance.
>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Andy Chiu <andy.chiu@sifive.com>
> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
> Tested-by: Charlie Jenkins <charlie@rivosinc.com>
> Signed-off-by: Jesse Taube <jesse@rivosinc.com>
> [Rebased, rewrote doc text, minor commit message revisions]
> Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> Signed-off-by: Guodong Xu <docular.xu@gmail.com>
Thanks, queued for v7.3.
- Paul
--
kvm-riscv mailing list
kvm-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/kvm-riscv
next prev parent reply other threads:[~2026-08-06 18:31 UTC|newest]
Thread overview: 87+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-01 12:52 [PATCH v5 00/17] riscv: hwprobe: Expose RVA23U64 base behavior Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` [PATCH v5 01/17] dt-bindings: riscv: sort multi-letter Z extensions alphanumerically Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-08 7:22 ` Paul Walmsley
2026-07-08 7:22 ` Paul Walmsley
2026-07-08 7:22 ` Paul Walmsley
2026-07-01 12:52 ` [PATCH v5 02/17] riscv: hwprobe.rst: Make indentation consistent Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-08 7:23 ` Paul Walmsley
2026-07-08 7:23 ` Paul Walmsley
2026-07-08 7:23 ` Paul Walmsley
2026-07-01 12:52 ` [PATCH v5 03/17] riscv: hwprobe.rst: Document EXT_ZICFISS and EXT_ZICFILP Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-08 7:23 ` Paul Walmsley
2026-07-08 7:23 ` Paul Walmsley
2026-07-08 7:23 ` Paul Walmsley
2026-07-01 12:52 ` [PATCH v5 04/17] riscv: Standardize extension capitalization Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-08-06 18:05 ` Paul Walmsley
2026-08-06 18:05 ` Paul Walmsley
2026-08-06 18:05 ` Paul Walmsley
2026-07-01 12:52 ` [PATCH v5 05/17] riscv: Add Zicclsm to cpufeature and hwprobe Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-08-06 18:31 ` Paul Walmsley [this message]
2026-08-06 18:31 ` Paul Walmsley
2026-08-06 18:31 ` Paul Walmsley
2026-07-01 12:52 ` [PATCH v5 06/17] riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs " Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-08-06 18:32 ` Paul Walmsley
2026-08-06 18:32 ` Paul Walmsley
2026-08-06 18:32 ` Paul Walmsley
2026-07-01 12:52 ` [PATCH v5 07/17] riscv: Add B to hwcap " Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 13:27 ` sashiko-bot
2026-07-01 12:52 ` [PATCH v5 08/17] dt-bindings: riscv: Require block-size for Zicbom, Zicbop, and Zicboz Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 13:35 ` sashiko-bot
2026-07-01 15:54 ` Rob Herring (Arm)
2026-07-01 15:54 ` Rob Herring (Arm)
2026-07-01 15:54 ` Rob Herring (Arm)
2026-07-01 20:39 ` Conor Dooley
2026-07-01 20:39 ` Conor Dooley
2026-07-01 20:39 ` Conor Dooley
2026-07-01 12:52 ` [PATCH v5 09/17] dt-bindings: riscv: Add Zic64b extension description Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 13:42 ` sashiko-bot
2026-07-01 12:52 ` [PATCH v5 10/17] riscv: Add Zic64b to cpufeature and hwprobe Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 13:53 ` sashiko-bot
2026-07-01 12:52 ` [PATCH v5 11/17] riscv: dts: spacemit: k3: Add Zic64b ISA extension Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` [PATCH v5 12/17] riscv: dts: spacemit: k1: " Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 14:00 ` sashiko-bot
2026-07-01 12:52 ` [PATCH v5 13/17] riscv: dts: sophgo: sg2044: " Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` [PATCH v5 14/17] riscv: Add a getter for user PMLEN support Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` [PATCH v5 15/17] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 14:22 ` sashiko-bot
2026-07-01 12:52 ` [PATCH v5 16/17] riscv: cpu: Output isa bases lines in cpuinfo Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` [PATCH v5 17/17] riscv: hwprobe: Introduce rva23u64 base behavior Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-01 12:52 ` Guodong Xu
2026-07-08 7:30 ` [PATCH v5 00/17] riscv: hwprobe: Expose RVA23U64 " patchwork-bot+linux-riscv
2026-07-08 7:30 ` patchwork-bot+linux-riscv
2026-07-08 7:30 ` patchwork-bot+linux-riscv
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