From: Oleksii Kurochko <oleksii.kurochko@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "Romain Caritey" <Romain.Caritey@microchip.com>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Connor Davis" <connojdavis@gmail.com>,
"Andrew Cooper" <andrew.cooper3@citrix.com>,
"Anthony PERARD" <anthony.perard@vates.tech>,
"Michal Orzel" <michal.orzel@amd.com>,
"Julien Grall" <julien@xen.org>,
"Roger Pau Monné" <roger.pau@citrix.com>,
"Stefano Stabellini" <sstabellini@kernel.org>,
xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 13/27] xen/riscv: add basic VGEIN management for AIA guests
Date: Mon, 13 Apr 2026 16:42:06 +0200 [thread overview]
Message-ID: <4b977410-8d24-41c3-9c83-7d95637ddea3@gmail.com> (raw)
In-Reply-To: <09fed304-685c-46a9-9159-72baa1721224@suse.com>
On 4/2/26 12:03 PM, Jan Beulich wrote:
> On 10.03.2026 18:08, Oleksii Kurochko wrote:
>> AIA provides a hardware-accelerated mechanism for delivering external
>> interrupts to domains via "guest interrupt files" located in IMSIC.
>> A single physical hart can implement multiple such files (up to GEILEN),
>> allowing several virtual harts to receive interrupts directly from hardware
>
> Isn't use of such an optimization coming prematurely? Shouldn't this series
> focus on getting basic functionality in place?
At the moment, we don't support only APLIC for guest interrupts as it
will require trap-and-emulation approach, so just from the start it was
decided to go with APLIC+IMSIC (IMSIC here as it only one interrupt
controller which exist and support VGEIN stuff at the momemnt) approach
and then when it will be needed back to only the case when APLIC is
supported.
Maybe, it was better to introduce in patch series where a lauching of
domain actually happens.
Considering that you've already made a review, I prefer then to have
this patch part of this patch series.
>
>> --- a/xen/arch/riscv/aia.c
>> +++ b/xen/arch/riscv/aia.c
>> @@ -1,11 +1,24 @@
>> /* SPDX-License-Identifier: GPL-2.0-only */
>>
>> +#include <xen/bitmap.h>
>> #include <xen/errno.h>
>> #include <xen/init.h>
>> #include <xen/sections.h>
>> +#include <xen/sched.h>
>> +#include <xen/spinlock.h>
>> #include <xen/types.h>
>> +#include <xen/xvmalloc.h>
>>
>> +#include <asm/aia.h>
>> #include <asm/cpufeature.h>
>> +#include <asm/csr.h>
>> +#include <asm/current.h>
>> +
>> +/*
>> + * Bitmap for each physical cpus to detect which VS (guest)
>> + * interrupt file id was used.
>> + */
>> +DEFINE_PER_CPU(struct vgein_bmp, vgein_bmp);
>
> Why can this not be static? All management looks to be in this same file.
It could be, it couldn't be before when I have vgein/hgei interrupt
handler in traps but after I decided to move it to aia.c, it looks like
it is fine to make it static.
>
>> @@ -14,12 +27,109 @@ bool aia_available(void)
>> return is_aia_available;
>> }
>>
>> +int __init vgein_init(unsigned int cpu)
>
> If this needs invoking once per CPU being brought up, it can't be __init.
Yes, it is going to be called inside the secondary CPU bring-up function.
__init sections are removed much later, after all CPUs are brought up,
so it looks like that at the moment when secondary CPUs are being
brought up, __init still exists and can be called.
>
> Also - static?
It isn't static because it will be called inside the secondary CPU
bring-up function.
>
>> +{
>> + struct vgein_bmp *vgein = &per_cpu(vgein_bmp, cpu);
>> +
>> + csr_write(CSR_HGEIE, -1UL);
>> + vgein->geilen = flsl(csr_read(CSR_HGEIE));
>> + csr_write(CSR_HGEIE, 0);
>> + if ( vgein->geilen )
>> + vgein->geilen--;
>
> I don't understand this. The "len" in "geilen" stands for "length", I suppose,
> i.e. the number of bits. Hmm, the spec itself is inconsistent: "The number of
> bits implemented in hgeip and hgeie for guest external interrupts is UNSPECIFIED
> and may be zero. This number is known as GEILEN." This may or may not include
> bit 0 (which is implemented, but r/o zero). Then saying "Hence, if GEILEN is
> nonzero, bits GEILEN:1 shall be writable in ..." suggests 0 isn't included, but
> that's not unambiguous.
But they explicitly wrote that: The least-significant bits are
implemented first, apart from bit 0. So bit 0 is explicitly excluded.
>
> Anyway, may I suggest
>
> vgein->geilen = flsl(csr_read(CSR_HGEIE) >> 1);
>
> instead?
It would be really better.
>
>> + BUG_ON(!vgein->geilen);
>
> You can return (an error, but see the respective remark on the earlier patch),
> no need to crash the system. That return may want to come after the printk()
> below, though.
>
>> + printk("cpu%d.geilen=%d\n", cpu, vgein->geilen);
>
> As before - %u please with unsigned int.
>
>> + if ( !vgein->bmp )
>
> Why would this check be needed?
>
>> + {
>> + vgein->bmp = xvzalloc_array(unsigned long, BITS_TO_LONGS(vgein->geilen));
>
> With the determination above, isn't BITS_TO_LONGS(vgein->geilen) ==
> BITS_PER_LONG in all cases? Surely you don't mean to runtime-allocate
> space for a single unsigned long? So I wonder is the dimension used
> is wrong.
Hm, I can't remember why I did so. You are right there is no any sense
to allocate a single unsinged long in runtime...
>
> If it isn't, dynamically allocating the owners array may be more
> useful, as (on RV64) occupies a fixed 512 bytes right now.
Agree, it make sense it will be much less memory if to allocate like:
vgein->owners = xvzalloc_array(struct vcpu *, vgein->geilen);
if ( !vgein->owners )
return -ENOMEM;
as maximum value of vgein->geilen is 63.
>
>> + if ( !vgein->bmp )
>> + return -ENOMEM;
>> + }
>> +
>> + spin_lock_init(&vgein->lock);
>> +
>> + return 0;
>> +}
>> +
>> int __init aia_init(void)
>> {
>> + int rc = 0;
>> +
>> if ( !riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ssaia) )
>> return -ENODEV;
>>
>> + if ( (rc = vgein_init(0)) )
>> + return rc;
>> +
>> is_aia_available = true;
>
> Ah, this answers a question of mine on the earlier patch: This boolean
> indicates more than just the extension being available. But why does
> the description there not simply say so? How am I as a reviewer supposed
> to know?
I relised that it is worse to mention that only when saw your reply in
the earlier patch, I will update the commit message for convience.
>
>> - return 0;
>> + return rc;
>> +}
>> +
>> +unsigned int vgein_assign(struct vcpu *v)
>> +{
>> + unsigned int vgein_id;
>> +
>
> Seemingly undue blank line.
>
>> + struct vgein_bmp *vgein_bmp = &per_cpu(vgein_bmp, v->processor);
>> + unsigned long *bmp = vgein_bmp->bmp;
>> + unsigned long flags;
>> +
>> + spin_lock_irqsave(&vgein_bmp->lock, flags);
>> + vgein_id = bitmap_weight(bmp, vgein_bmp->geilen);
>
> How can the ID to use be the number of bits which are set? This only works
> if all set bits are contiguous at the bottom.
Oh, it is really wrong. find_first_zero_bit() should be instead or
vgein_id = find_next_zero_bit(bmp, vgein_bmp->geilen + 1, 1);
>
>> + /*
>> + * All vCPU guest interrupt files are used and we don't support a case
>> + * when number of vCPU on 1 pCPU is bigger then geilen.
>> + */
>
> This wants checking in vgein_init() then. CPUs (beyond the boot one)
> violating this should not be brought online.
It'll be nice. But we can't know how many vCPUs will be ran on pCPU when
vgein_init() is executed.
>
>> + ASSERT(vgein_id < vgein_bmp->geilen);
>
> What if not bit is available? By asserting, you assume the caller will not
> call here when no ID is available.
It is just a temporary ASSERT() (as we don't support software guest
interrupt files) because in general it is fine if there is no bit
available, it will just mean that that no physical hardware guest
interrupt file is assigned to the virtual hart, and software-based
emulation (a "software file") must be used to handle guest external
interrupts.
Will it be better to return 0 now here and just don't create a vCPU
on ...
Yet there is no caller of this function,
> so how can one verify whether this assertion is appropriate?
... the caller side when an assignment is expected to be happen?
>
>> + bitmap_set(bmp, vgein_id, 1);
>
> __set_bit()?
I thought that it will be fine to use for bmp, bitmap_* functions().
__set_bit is what is called inside bitmap_set().
>
>> + spin_unlock_irqrestore(&vgein_bmp->lock, flags);
>> +
>> + /*
>> + * The vgein_id shouldn't be zero, as it will indicate that no guest
>> + * external interrupt source is selected for VS-level external interrupts
>> + * according to RISC-V priviliged spec:
>> + * 8.2.1 Hypervisor Status Register (hstatus) in RISC-V priviliged spec:
>
> Please avoid section numbers in such references. The section of this name
> in the version I'm looking at is 21.2.1.
>
>> + * The VGEIN (Virtual Guest External Interrupt Number) field selects
>> + * a guest external interrupt source for VS-level external interrupts.
>> + * VGEIN is a WLRL field that must be able to hold values between zero
>> + * and the maximum guest external interrupt number (known as GEILEN),
>> + * inclusive.
>> + * When VGEIN=0, no guest external interrupt source is selected for
>> + * VS-level external interrupts.
>> + */
>> + vgein_id++;
>
> Related to my comment regarding GEILEN, this shouldn't be necessary. Keep
> bits in their natural positions, and simply avoid using bit 0 (either by
> setting it during init and then never clearing it, or by starting the
> scan for clear bits at bit 1).
>
>> +#ifdef VGEIN_DEBUG
>> + printk("%s: %pv: vgein_id(%u), xen_cpu%d_bmp=%#lx\n",
>> + __func__, v, vgein_id, v->processor, *bmp);
>> +#endif
>> +
>> + vcpu_guest_cpu_user_regs(v)->hstatus &= ~HSTATUS_VGEIN;
>> + vcpu_guest_cpu_user_regs(v)->hstatus |=
>> + MASK_INSR(vgein_id, HSTATUS_VGEIN);
>
> When is this function going to be invoked? (As before, not knowing this is
> one of the problems with introducing functions with no callers.)
vgein_assign() function is going to be invoked during the call of
arch_vcpu_create().
I also thought to make vgein_assign() just work with vgein_id and just
return vgein_id and fill v->hstatus on the caller side. It looks a
little bit cleaner from some point of view.
It is still need to return vgein_id as it is needed for IMSIC's guest
interrupt file address calculation.
>
>> + return vgein_id;
>> +}
>> +
>> +void vgein_release(struct vcpu *v, unsigned int vgen_id)
>> +{
>> + unsigned long flags;
>> +
>
> Another seemingly stray blank line.
>
>> + struct vgein_bmp *vgein_bmp = &per_cpu(vgein_bmp, v->processor);
>> +
>> + spin_lock_irqsave(&vgein_bmp->lock, flags);
>> + bitmap_clear(vgein_bmp->bmp, vgen_id - 1, 1);
>
> __clear_bit()?
>
The same as with bitmap_set() as ->bmp is bitmap I expect that
bitmap_*() functions should be used. But just to avoid extra if() inside
bitmap_clear(), I will use __clear_bit().
>> + spin_unlock_irqrestore(&vgein_bmp->lock, flags);
>> +
>> +#ifdef VGEIN_DEBUG
>> + printk("%s: vgein_id(%u), xen_cpu%d_bmp=%#lx\n",
>> + __func__, vgen_id, v->processor, *vgein_bmp->bmp);
>
> I can't spot a difference from the message in vgein_assign(). How is one
> to distinguish the two in a log?
By function name which is the first argument (__func__).
>
>> --- a/xen/arch/riscv/include/asm/aia.h
>> +++ b/xen/arch/riscv/include/asm/aia.h
>> @@ -3,8 +3,26 @@
>> #ifndef ASM__RISCV__AIA_H
>> #define ASM__RISCV__AIA_H
>>
>> +#include <xen/percpu.h>
>> +#include <xen/spinlock.h>
>> +
>> +struct vcpu;
>> +
>> +struct vgein_bmp {
>
> What does the _bmp suffix indicate here? There's ...
>
>> + unsigned long *bmp;
>
> ... a bitmap field, yes, but ...
>
>> + spinlock_t lock;
>> + struct vcpu *owners[BITS_PER_LONG];
>> + unsigned int geilen;
>> +};
>
> ... the structure as a whole has quite a bit more.
Agree, there is no any sense for _bmp. It would be better to use _ctrl.
Also, I will move this struct to aia.c. Then it also make sense to
rename vgein_vmp variable just to vgein.
Thanks.
~ Oleksii
next prev parent reply other threads:[~2026-04-13 14:42 UTC|newest]
Thread overview: 123+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-10 17:08 [PATCH v1 00/27] [RISC-V] Introduce enablemenant of dom0less Oleksii Kurochko
2026-03-10 17:08 ` [PATCH v1 01/27] xen/riscv: Implement ARCH_PAGING_MEMPOOL Oleksii Kurochko
2026-03-11 8:18 ` Jan Beulich
2026-04-09 10:31 ` Oleksii Kurochko
2026-03-10 17:08 ` [PATCH v1 02/27] xen/riscv: Implement construct_domain() Oleksii Kurochko
2026-03-24 9:37 ` Jan Beulich
2026-04-09 11:26 ` Oleksii Kurochko
2026-04-09 12:58 ` Jan Beulich
2026-04-09 13:39 ` Oleksii Kurochko
2026-04-09 14:01 ` Oleksii Kurochko
2026-04-14 6:26 ` Julien Grall
2026-03-10 17:08 ` [PATCH v1 03/27] xen/riscv: implement prerequisites for domain_create() Oleksii Kurochko
2026-04-01 12:57 ` Jan Beulich
2026-04-09 11:55 ` Oleksii Kurochko
2026-03-10 17:08 ` [PATCH v1 04/27] xen/riscv: rework G-stage mode handling Oleksii Kurochko
2026-04-01 13:19 ` Jan Beulich
2026-04-07 10:47 ` Oleksii Kurochko
2026-04-07 13:43 ` Jan Beulich
2026-03-10 17:08 ` [PATCH v1 05/27] xen/riscv: introduce guest riscv,isa string Oleksii Kurochko
2026-04-01 13:49 ` Jan Beulich
2026-04-10 10:24 ` Oleksii Kurochko
2026-04-10 10:50 ` Jan Beulich
2026-03-10 17:08 ` [PATCH v1 06/27] xen/riscv: implement make_cpus_node() Oleksii Kurochko
2026-04-01 14:11 ` Jan Beulich
2026-04-10 11:19 ` Oleksii Kurochko
2026-04-10 12:02 ` Jan Beulich
2026-03-10 17:08 ` [PATCH v1 07/27] xen/riscv: implement make_timer_node() Oleksii Kurochko
2026-04-01 14:24 ` Jan Beulich
2026-04-10 11:54 ` Oleksii Kurochko
2026-03-10 17:08 ` [PATCH v1 08/27] xen/riscv: implement make_arch_nodes() Oleksii Kurochko
2026-04-01 14:29 ` Jan Beulich
2026-04-10 13:32 ` Oleksii Kurochko
2026-03-10 17:08 ` [PATCH v1 09/27] xen/riscv: implement make_intc_domU_node() Oleksii Kurochko
2026-04-01 14:38 ` Jan Beulich
2026-04-10 14:00 ` Oleksii Kurochko
2026-04-10 14:23 ` Jan Beulich
2026-03-10 17:08 ` [PATCH v1 10/27] xen/riscv: generate IMSIC DT node for guest domains Oleksii Kurochko
2026-04-01 15:05 ` Jan Beulich
2026-04-10 15:40 ` Oleksii Kurochko
2026-04-16 11:42 ` Jan Beulich
2026-04-17 8:10 ` Oleksii Kurochko
2026-04-17 13:50 ` Jan Beulich
2026-04-17 14:01 ` Oleksii Kurochko
2026-04-17 14:10 ` Jan Beulich
2026-03-10 17:08 ` [PATCH v1 11/27] xen/riscv: create APLIC " Oleksii Kurochko
2026-04-01 15:16 ` Jan Beulich
2026-04-13 8:43 ` Oleksii Kurochko
2026-04-13 8:48 ` Oleksii Kurochko
2026-04-16 11:49 ` Jan Beulich
2026-04-17 9:01 ` Oleksii Kurochko
2026-04-17 13:53 ` Jan Beulich
2026-04-17 14:27 ` Oleksii Kurochko
2026-03-10 17:08 ` [PATCH v1 12/27] xen/riscv: introduce aia_init() and aia_available() Oleksii Kurochko
2026-04-02 9:00 ` Jan Beulich
2026-04-13 9:32 ` Oleksii Kurochko
2026-04-16 12:06 ` Jan Beulich
2026-04-17 9:37 ` Oleksii Kurochko
2026-03-10 17:08 ` [PATCH v1 13/27] xen/riscv: add basic VGEIN management for AIA guests Oleksii Kurochko
2026-04-02 10:03 ` Jan Beulich
2026-04-13 14:42 ` Oleksii Kurochko [this message]
2026-04-16 12:21 ` Jan Beulich
2026-04-17 11:34 ` Oleksii Kurochko
2026-04-17 14:07 ` Jan Beulich
2026-04-20 7:52 ` Oleksii Kurochko
2026-03-10 17:08 ` [PATCH v1 14/27] xen/riscv: introduce per-vCPU IMSIC state Oleksii Kurochko
2026-04-02 11:31 ` Jan Beulich
2026-04-14 9:22 ` Oleksii Kurochko
2026-04-16 12:31 ` Jan Beulich
2026-04-16 12:31 ` Jan Beulich
2026-04-17 13:47 ` Oleksii Kurochko
2026-04-20 8:29 ` Jan Beulich
2026-03-10 17:08 ` [PATCH v1 15/27] xen/riscv: add very early virtual APLIC (vAPLIC) initialization support Oleksii Kurochko
2026-04-02 11:58 ` Jan Beulich
2026-04-14 10:27 ` Oleksii Kurochko
2026-04-16 12:42 ` Jan Beulich
2026-04-20 10:25 ` Oleksii Kurochko
2026-04-20 10:47 ` Jan Beulich
2026-03-10 17:08 ` [PATCH v1 16/27] xen/riscv: implement IRQ mapping for device passthrough Oleksii Kurochko
2026-04-02 12:22 ` Jan Beulich
2026-04-14 11:29 ` Oleksii Kurochko
2026-04-16 12:51 ` Jan Beulich
2026-04-20 11:39 ` Oleksii Kurochko
2026-04-20 13:45 ` Jan Beulich
2026-04-20 14:34 ` Oleksii Kurochko
2026-04-20 15:21 ` Jan Beulich
2026-04-20 15:31 ` Oleksii Kurochko
2026-03-10 17:08 ` [PATCH v1 17/27] xen/riscv: add missing APLIC register offsets, masks to asm/aplic.h Oleksii Kurochko
2026-04-02 12:51 ` Jan Beulich
2026-04-14 11:42 ` Oleksii Kurochko
2026-03-10 17:08 ` [PATCH v1 18/27] xen/riscv: add vaplic access check Oleksii Kurochko
2026-04-02 13:10 ` Jan Beulich
2026-04-14 11:45 ` Oleksii Kurochko
2026-04-15 7:35 ` Oleksii Kurochko
2026-04-16 13:01 ` Jan Beulich
2026-04-20 11:53 ` Oleksii Kurochko
2026-04-20 12:03 ` Jan Beulich
2026-03-10 17:08 ` [PATCH v1 19/27] xen/riscv: emulate guest writes to virtual APLIC MMIO Oleksii Kurochko
2026-04-02 14:18 ` Jan Beulich
2026-04-14 16:04 ` Oleksii Kurochko
2026-04-16 13:19 ` Jan Beulich
2026-04-20 15:02 ` Oleksii Kurochko
2026-04-20 15:27 ` Jan Beulich
2026-03-10 17:08 ` [PATCH v1 20/27] xen/riscv: emulate guest reads from " Oleksii Kurochko
2026-03-10 17:08 ` [PATCH v1 21/27] xen/riscv: introduce (de)initialization helpers for vINTC Oleksii Kurochko
2026-04-02 14:58 ` Jan Beulich
2026-04-15 7:50 ` Oleksii Kurochko
2026-04-16 13:23 ` Jan Beulich
2026-03-10 17:08 ` [PATCH v1 22/27] xen/riscv: implement init_intc_phandle() Oleksii Kurochko
2026-04-02 15:00 ` Jan Beulich
2026-03-10 17:08 ` [PATCH v1 23/27] xen/riscv: call do_initcalls() in start_xen() Oleksii Kurochko
2026-04-02 15:01 ` Jan Beulich
2026-03-10 17:08 ` [PATCH v1 24/27] xen/riscv: init rcu Oleksii Kurochko
2026-04-02 15:03 ` Jan Beulich
2026-04-14 11:50 ` Oleksii Kurochko
2026-03-10 17:08 ` [PATCH v1 25/27] xen/riscv: setup system domains Oleksii Kurochko
2026-03-10 17:08 ` [PATCH v1 26/27] xen/riscv: provide init_vuart() Oleksii Kurochko
2026-04-07 13:52 ` Jan Beulich
2026-03-10 17:09 ` [PATCH v1 27/27] xen/riscv: add initial dom0less infrastructure support Oleksii Kurochko
2026-04-07 14:11 ` Jan Beulich
2026-04-15 10:00 ` Oleksii Kurochko
2026-04-16 14:13 ` Jan Beulich
2026-04-15 10:28 ` Oleksii Kurochko
2026-04-16 14:15 ` Jan Beulich
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