[Qemu-devel] [PULL 00/30] ppc patch queue 2013-04-26

[Qemu-devel] [PULL 00/30] ppc patch queue 2013-04-26

[Alexander Graf]

Hi Blue / Aurelien,

This is my current patch queue for ppc.  Please pull.

Alex


The following changes since commit bf9b255f484fd61cbaa91faeff254140a0ecd18c:
  Anthony Liguori (1):
        gtk: refactor menu creation

are available in the git repository at:

  git://github.com/agraf/qemu.git ppc-for-upstream

Alexander Graf (4):
      linux-headers: Update to kvm/queue
      PPC: mac newworld: fix cpu NIP reset value
      PPC: Fix compile with profiling enabled
      PPC: Fix dcbz for linux-user on 970

Aurelien Jarno (12):
      target-ppc: Enable ISEL on POWER7
      target-ppc: fix nego and subf*o instructions
      target-ppc: optimize fabs, fnabs, fneg
      disas: Disassemble all ppc insns for the guest
      target-ppc: add instruction flags for Book I 2.05
      target-ppc: emulate cmpb instruction
      target-ppc: emulate prtyw and prtyd instructions
      target-ppc: emulate fcpsgn instruction
      target-ppc: emulate lfiwax instruction
      target-ppc: emulate load doubleword pair instructions
      target-ppc: emulate store doubleword pair instructions
      target-ppc: add support for extended mtfsf/mtfsfi forms

Bharat Bhushan (1):
      Enable kvm emulated watchdog

David Gibson (7):
      pseries: Fix incorrect calculation of RMA size in certain configurations
      pseries: Fixes and enhancements to L1 cache properties
      target-ppc: Add more stubs for POWER7 PMU registers
      pseries: Fix some small errors in XICS logic
      target-ppc: Synchronize VPA state with KVM
      pseries: Convert VIO code to QOM style type safe(ish) casts
      pseries: Generate device paths for VIO devices

Fabien Chouteau (3):
      PPC: Remove env->hreset_excp_prefix
      PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450
      PPC: Add breakpoint registers for 603 and e300

Richard Henderson (1):
      target-ppc: Fix narrow-mode add/sub carry output

Stuart Yoder (1):
      PPC: e500: advertise 4.2 MPIC only if KVM supports EPR

Tristan Gingold (1):
      powerpc: correctly handle fpu exceptions.

 disas.c                         |    1 +
 hw/char/spapr_vty.c             |   18 ++-
 hw/net/spapr_llan.c             |   24 ++--
 hw/nvram/spapr_nvram.c          |   10 +-
 hw/ppc/e500plat.c               |    7 +
 hw/ppc/mac_newworld.c           |    2 +
 hw/ppc/ppc_booke.c              |   45 ++++++-
 hw/ppc/spapr.c                  |   27 +++-
 hw/ppc/spapr_vio.c              |   41 ++++--
 hw/ppc/xics.c                   |    2 +
 hw/scsi/spapr_vscsi.c           |   15 ++-
 linux-headers/asm-powerpc/kvm.h |    5 +
 linux-headers/linux/kvm.h       |    3 +
 target-ppc/cpu-qom.h            |    1 +
 target-ppc/cpu.h                |    6 +-
 target-ppc/fpu_helper.c         |   71 +++-------
 target-ppc/helper.h             |    4 +-
 target-ppc/int_helper.c         |   15 ++
 target-ppc/kvm.c                |  237 +++++++++++++++++++++++++++++++-
 target-ppc/kvm_ppc.h            |   30 ++++
 target-ppc/machine.c            |    2 -
 target-ppc/mem_helper.c         |    2 +-
 target-ppc/translate.c          |  293 ++++++++++++++++++++++++++++++++++-----
 target-ppc/translate_init.c     |  117 ++++++++++------
 translate-all.c                 |    1 +
 25 files changed, 791 insertions(+), 188 deletions(-)

[Qemu-devel] [PATCH 01/30] target-ppc: Enable ISEL on POWER7

[Alexander Graf]

From: Aurelien Jarno <aurelien@aurel32.net>

ISEL is a Power ISA 2.06 instruction and thus is available on POWER7.
Given this is trapped and emulated by the Linux kernel, I guess it went
unnoticed.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/translate_init.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 781170f..aea7d27 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7004,7 +7004,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
     dc->desc = "POWER7";
     pcc->init_proc = init_proc_POWER7;
     pcc->check_pow = check_pow_nocheck;
-    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
                        PPC_FLOAT_STFIWX |
-- 
1.6.0.2

[Qemu-devel] [PATCH 02/30] PPC: e500: advertise 4.2 MPIC only if KVM supports EPR

[Alexander Graf]

From: Stuart Yoder <stuart.yoder@freescale.com>

Older KVM versions don't support EPR which breaks guests when we announce
MPIC variants that support EPR.

Catch that case and expose only MPIC version 2.0 which tells the guest that
we don't support the EPR capability yet.

Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
[agraf: Add comment, route cap check through kvm_ppc.c]
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppc/e500plat.c    |    7 +++++++
 target-ppc/kvm.c     |    7 +++++++
 target-ppc/kvm_ppc.h |    6 ++++++
 3 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
index 7292ce1..c852995 100644
--- a/hw/ppc/e500plat.c
+++ b/hw/ppc/e500plat.c
@@ -16,6 +16,7 @@
 #include "sysemu/device_tree.h"
 #include "hw/pci/pci.h"
 #include "hw/ppc/openpic.h"
+#include "kvm_ppc.h"
 
 static void e500plat_fixup_devtree(PPCE500Params *params, void *fdt)
 {
@@ -48,6 +49,12 @@ static void e500plat_init(QEMUMachineInitArgs *args)
         .mpic_version = OPENPIC_MODEL_FSL_MPIC_42,
     };
 
+    /* Older KVM versions don't support EPR which breaks guests when we announce
+       MPIC variants that support EPR. Revert to an older one for those */
+    if (kvm_enabled() && !kvmppc_has_cap_epr()) {
+        params.mpic_version = OPENPIC_MODEL_FSL_MPIC_20;
+    }
+
     ppce500_init(&params);
 }
 
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 5e9dddb..f2658bb 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -63,6 +63,7 @@ static int cap_ppc_rma;
 static int cap_spapr_tce;
 static int cap_hior;
 static int cap_one_reg;
+static int cap_epr;
 
 /* XXX We have a race condition where we actually have a level triggered
  *     interrupt, but the infrastructure can't expose that yet, so the guest
@@ -95,6 +96,7 @@ int kvm_arch_init(KVMState *s)
     cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE);
     cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG);
     cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR);
+    cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR);
 
     if (!cap_interrupt_level) {
         fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the "
@@ -1530,6 +1532,11 @@ int kvmppc_fixup_cpu(PowerPCCPU *cpu)
     return 0;
 }
 
+bool kvmppc_has_cap_epr(void)
+{
+    return cap_epr;
+}
+
 static int kvm_ppc_register_host_cpu_type(void)
 {
     TypeInfo type_info = {
diff --git a/target-ppc/kvm_ppc.h b/target-ppc/kvm_ppc.h
index 6bcc5cc..600d632 100644
--- a/target-ppc/kvm_ppc.h
+++ b/target-ppc/kvm_ppc.h
@@ -33,6 +33,7 @@ int kvmppc_reset_htab(int shift_hint);
 uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift);
 #endif /* !CONFIG_USER_ONLY */
 int kvmppc_fixup_cpu(PowerPCCPU *cpu);
+bool kvmppc_has_cap_epr(void);
 
 #else
 
@@ -129,6 +130,11 @@ static inline int kvmppc_fixup_cpu(PowerPCCPU *cpu)
 {
     return -1;
 }
+
+static inline bool kvmppc_has_cap_epr(void)
+{
+    return false;
+}
 #endif
 
 #ifndef CONFIG_KVM
-- 
1.6.0.2

[Qemu-devel] [PATCH 03/30] PPC: Remove env->hreset_excp_prefix

[Alexander Graf]

From: Fabien Chouteau <chouteau@adacore.com>

This value is not needed if we use correctly the MSR[IP] bit.

excp_prefix is always 0x00000000, except when the MSR[IP] bit is
implemented and set to 1, in that case excp_prefix is 0xfff00000.

The handling of MSR[IP] was already implemented but not used at reset
because the value of env->msr was changed "manually".

The patch uses the function hreg_store_msr() to set env->msr, this
ensures a good handling of MSR[IP] at reset, and therefore a good value
for excp_prefix.

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppc/spapr.c              |    6 ++++--
 target-ppc/cpu.h            |    1 -
 target-ppc/machine.c        |    2 --
 target-ppc/translate_init.c |   42 ++++++++++++------------------------------
 4 files changed, 16 insertions(+), 35 deletions(-)

diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 7a42501..e35c26f 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -801,8 +801,10 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args)
         /* Set time-base frequency to 512 MHz */
         cpu_ppc_tb_init(env, TIMEBASE_FREQ);
 
-        /* PAPR always has exception vectors in RAM not ROM */
-        env->hreset_excp_prefix = 0;
+        /* PAPR always has exception vectors in RAM not ROM. To ensure this,
+         * MSR[IP] should never be set.
+         */
+        env->msr_mask &= ~(1 << 6);
 
         /* Tell KVM that we're in PAPR mode */
         if (kvm_enabled()) {
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 42c36e2..99ebf7e 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1026,7 +1026,6 @@ struct CPUPPCState {
     /* Exception vectors */
     target_ulong excp_vectors[POWERPC_EXCP_NB];
     target_ulong excp_prefix;
-    target_ulong hreset_excp_prefix;
     target_ulong ivor_mask;
     target_ulong ivpr_mask;
     target_ulong hreset_vector;
diff --git a/target-ppc/machine.c b/target-ppc/machine.c
index 235b0d5..2d10adb 100644
--- a/target-ppc/machine.c
+++ b/target-ppc/machine.c
@@ -78,7 +78,6 @@ void cpu_save(QEMUFile *f, void *opaque)
     for (i = 0; i < POWERPC_EXCP_NB; i++)
         qemu_put_betls(f, &env->excp_vectors[i]);
     qemu_put_betls(f, &env->excp_prefix);
-    qemu_put_betls(f, &env->hreset_excp_prefix);
     qemu_put_betls(f, &env->ivor_mask);
     qemu_put_betls(f, &env->ivpr_mask);
     qemu_put_betls(f, &env->hreset_vector);
@@ -167,7 +166,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
     for (i = 0; i < POWERPC_EXCP_NB; i++)
         qemu_get_betls(f, &env->excp_vectors[i]);
     qemu_get_betls(f, &env->excp_prefix);
-    qemu_get_betls(f, &env->hreset_excp_prefix);
     qemu_get_betls(f, &env->ivor_mask);
     qemu_get_betls(f, &env->ivpr_mask);
     qemu_get_betls(f, &env->hreset_vector);
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index aea7d27..402ad2a 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -2593,7 +2593,6 @@ static void init_excp_4xx_real (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
-    env->hreset_excp_prefix = 0x00000000UL;
     env->ivor_mask = 0x0000FFF0UL;
     env->ivpr_mask = 0xFFFF0000UL;
     /* Hardware reset vector */
@@ -2618,7 +2617,6 @@ static void init_excp_4xx_softmmu (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
-    env->hreset_excp_prefix = 0x00000000UL;
     env->ivor_mask = 0x0000FFF0UL;
     env->ivpr_mask = 0xFFFF0000UL;
     /* Hardware reset vector */
@@ -2644,7 +2642,6 @@ static void init_excp_MPC5xx (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
     env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
     env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
-    env->hreset_excp_prefix = 0x00000000UL;
     env->ivor_mask = 0x0000FFF0UL;
     env->ivpr_mask = 0xFFFF0000UL;
     /* Hardware reset vector */
@@ -2676,7 +2673,6 @@ static void init_excp_MPC8xx (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
     env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
     env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
-    env->hreset_excp_prefix = 0x00000000UL;
     env->ivor_mask = 0x0000FFF0UL;
     env->ivpr_mask = 0xFFFF0000UL;
     /* Hardware reset vector */
@@ -2704,7 +2700,6 @@ static void init_excp_G2 (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
-    env->hreset_excp_prefix = 0x00000000UL;
     /* Hardware reset vector */
     env->hreset_vector = 0xFFFFFFFCUL;
 #endif
@@ -2733,7 +2728,6 @@ static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
     env->excp_vectors[POWERPC_EXCP_SPEU]     = 0x00000000;
     env->excp_vectors[POWERPC_EXCP_EFPDI]    = 0x00000000;
     env->excp_vectors[POWERPC_EXCP_EFPRI]    = 0x00000000;
-    env->hreset_excp_prefix = 0x00000000UL;
     env->ivor_mask = 0x0000FFF7UL;
     env->ivpr_mask = ivpr_mask;
     /* Hardware reset vector */
@@ -2760,7 +2754,6 @@ static void init_excp_BookE (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
-    env->hreset_excp_prefix = 0x00000000UL;
     env->ivor_mask = 0x0000FFE0UL;
     env->ivpr_mask = 0xFFFF0000UL;
     /* Hardware reset vector */
@@ -2783,7 +2776,6 @@ static void init_excp_601 (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
     env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
-    env->hreset_excp_prefix = 0xFFF00000UL;
     /* Hardware reset vector */
     env->hreset_vector = 0x00000100UL;
 #endif
@@ -2811,7 +2803,6 @@ static void init_excp_602 (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
-    env->hreset_excp_prefix = 0xFFF00000UL;
     /* Hardware reset vector */
     env->hreset_vector = 0xFFFFFFFCUL;
 #endif
@@ -2836,7 +2827,6 @@ static void init_excp_603 (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
-    env->hreset_excp_prefix = 0x00000000UL;
     /* Hardware reset vector */
     env->hreset_vector = 0xFFFFFFFCUL;
 #endif
@@ -2859,7 +2849,6 @@ static void init_excp_604 (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
-    env->hreset_excp_prefix = 0xFFF00000UL;
     /* Hardware reset vector */
     env->hreset_vector = 0x00000100UL;
 #endif
@@ -2883,7 +2872,6 @@ static void init_excp_7x0 (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
-    env->hreset_excp_prefix = 0x00000000UL;
     /* Hardware reset vector */
     env->hreset_vector = 0xFFFFFFFCUL;
 #endif
@@ -2906,7 +2894,6 @@ static void init_excp_750cl (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
-    env->hreset_excp_prefix = 0x00000000UL;
     /* Hardware reset vector */
     env->hreset_vector = 0xFFFFFFFCUL;
 #endif
@@ -2929,7 +2916,6 @@ static void init_excp_750cx (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
-    env->hreset_excp_prefix = 0x00000000UL;
     /* Hardware reset vector */
     env->hreset_vector = 0xFFFFFFFCUL;
 #endif
@@ -2957,7 +2943,6 @@ static void init_excp_7x5 (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
-    env->hreset_excp_prefix = 0x00000000UL;
     /* Hardware reset vector */
     env->hreset_vector = 0xFFFFFFFCUL;
 #endif
@@ -2983,7 +2968,6 @@ static void init_excp_7400 (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
-    env->hreset_excp_prefix = 0x00000000UL;
     /* Hardware reset vector */
     env->hreset_vector = 0xFFFFFFFCUL;
 #endif
@@ -3011,7 +2995,6 @@ static void init_excp_7450 (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
-    env->hreset_excp_prefix = 0x00000000UL;
     /* Hardware reset vector */
     env->hreset_vector = 0xFFFFFFFCUL;
 #endif
@@ -3041,7 +3024,6 @@ static void init_excp_970 (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
-    env->hreset_excp_prefix = 0x00000000FFF00000ULL;
     /* Hardware reset vector */
     env->hreset_vector = 0x0000000000000100ULL;
 #endif
@@ -3070,7 +3052,6 @@ static void init_excp_POWER7 (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
-    env->hreset_excp_prefix = 0;
     /* Hardware reset vector */
     env->hreset_vector = 0x0000000000000100ULL;
 #endif
@@ -7043,7 +7024,6 @@ static void init_ppc_proc(PowerPCCPU *cpu)
     /* Set all exception vectors to an invalid address */
     for (i = 0; i < POWERPC_EXCP_NB; i++)
         env->excp_vectors[i] = (target_ulong)(-1ULL);
-    env->hreset_excp_prefix = 0x00000000;
     env->ivor_mask = 0x00000000;
     env->ivpr_mask = 0x00000000;
     /* Default MMU definitions */
@@ -7080,9 +7060,7 @@ static void init_ppc_proc(PowerPCCPU *cpu)
     }
     /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
     (*pcc->init_proc)(env);
-#if !defined(CONFIG_USER_ONLY)
-    env->excp_prefix = env->hreset_excp_prefix;
-#endif
+
     /* MSR bits & flags consistency checks */
     if (env->msr_mask & (1 << 25)) {
         switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
@@ -8182,19 +8160,23 @@ static void ppc_cpu_reset(CPUState *s)
     msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
     msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
     msr |= (target_ulong)1 << MSR_PR;
-#else
-    env->excp_prefix = env->hreset_excp_prefix;
-    env->nip = env->hreset_vector | env->excp_prefix;
-    if (env->mmu_model != POWERPC_MMU_REAL) {
-        ppc_tlb_invalidate_all(env);
-    }
 #endif
-    env->msr = msr & env->msr_mask;
+
 #if defined(TARGET_PPC64)
     if (env->mmu_model & POWERPC_MMU_64) {
         env->msr |= (1ULL << MSR_SF);
     }
 #endif
+
+    hreg_store_msr(env, msr, 1);
+
+#if !defined(CONFIG_USER_ONLY)
+    env->nip = env->hreset_vector | env->excp_prefix;
+    if (env->mmu_model != POWERPC_MMU_REAL) {
+        ppc_tlb_invalidate_all(env);
+    }
+#endif
+
     hreg_compute_hflags(env);
     env->reserve_addr = (target_ulong)-1ULL;
     /* Be sure no exception or interrupt is pending */
-- 
1.6.0.2

[Qemu-devel] [PATCH 04/30] target-ppc: fix nego and subf*o instructions

[Alexander Graf]

From: Aurelien Jarno <aurelien@aurel32.net>

The overflow computation of nego and subf*o instructions has been broken
in commit ffe30937. Contrary to other targets, the instruction is subtract
from an not subtract on PowerPC.

This patch fixes the issue by using the correct argument in the xor
computation. Thanks to Peter Maydell for the hint.

With this change the PPC emulation passes the Gwenole Beauchesne
testsuite again.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/translate.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 5e741d1..294ab58 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -746,7 +746,7 @@ static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
 {
     TCGv t0 = tcg_temp_new();
 
-    tcg_gen_xor_tl(cpu_ov, arg0, arg1);
+    tcg_gen_xor_tl(cpu_ov, arg0, arg2);
     tcg_gen_xor_tl(t0, arg1, arg2);
     if (sub) {
         tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
-- 
1.6.0.2

[Qemu-devel] [PATCH 05/30] PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450

[Alexander Graf]

From: Fabien Chouteau <chouteau@adacore.com>

According to the different user's manuals, the vector offset for system
reset (both /HRESET and /SRESET) is 0x00100.

This patch may break support of some executables, as the power-on start
address may change. For a specific board, if the power-on start address
is different than HRESET vector (i.e. 0x00000100 or 0xfff00100), this
should be fixed in board's initialization code.

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/translate_init.c |   22 +++++++++++-----------
 1 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 402ad2a..f1d150a 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -2645,7 +2645,7 @@ static void init_excp_MPC5xx (CPUPPCState *env)
     env->ivor_mask = 0x0000FFF0UL;
     env->ivpr_mask = 0xFFFF0000UL;
     /* Hardware reset vector */
-    env->hreset_vector = 0xFFFFFFFCUL;
+    env->hreset_vector = 0x00000100UL;
 #endif
 }
 
@@ -2676,7 +2676,7 @@ static void init_excp_MPC8xx (CPUPPCState *env)
     env->ivor_mask = 0x0000FFF0UL;
     env->ivpr_mask = 0xFFFF0000UL;
     /* Hardware reset vector */
-    env->hreset_vector = 0xFFFFFFFCUL;
+    env->hreset_vector = 0x00000100UL;
 #endif
 }
 
@@ -2701,7 +2701,7 @@ static void init_excp_G2 (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
     /* Hardware reset vector */
-    env->hreset_vector = 0xFFFFFFFCUL;
+    env->hreset_vector = 0x00000100UL;
 #endif
 }
 
@@ -2804,7 +2804,7 @@ static void init_excp_602 (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
     /* Hardware reset vector */
-    env->hreset_vector = 0xFFFFFFFCUL;
+    env->hreset_vector = 0x00000100UL;
 #endif
 }
 
@@ -2828,7 +2828,7 @@ static void init_excp_603 (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
     /* Hardware reset vector */
-    env->hreset_vector = 0xFFFFFFFCUL;
+    env->hreset_vector = 0x00000100UL;
 #endif
 }
 
@@ -2873,7 +2873,7 @@ static void init_excp_7x0 (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
     /* Hardware reset vector */
-    env->hreset_vector = 0xFFFFFFFCUL;
+    env->hreset_vector = 0x00000100UL;
 #endif
 }
 
@@ -2895,7 +2895,7 @@ static void init_excp_750cl (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
     /* Hardware reset vector */
-    env->hreset_vector = 0xFFFFFFFCUL;
+    env->hreset_vector = 0x00000100UL;
 #endif
 }
 
@@ -2917,7 +2917,7 @@ static void init_excp_750cx (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
     /* Hardware reset vector */
-    env->hreset_vector = 0xFFFFFFFCUL;
+    env->hreset_vector = 0x00000100UL;
 #endif
 }
 
@@ -2944,7 +2944,7 @@ static void init_excp_7x5 (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
     /* Hardware reset vector */
-    env->hreset_vector = 0xFFFFFFFCUL;
+    env->hreset_vector = 0x00000100UL;
 #endif
 }
 
@@ -2969,7 +2969,7 @@ static void init_excp_7400 (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
     /* Hardware reset vector */
-    env->hreset_vector = 0xFFFFFFFCUL;
+    env->hreset_vector = 0x00000100UL;
 #endif
 }
 
@@ -2996,7 +2996,7 @@ static void init_excp_7450 (CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
     /* Hardware reset vector */
-    env->hreset_vector = 0xFFFFFFFCUL;
+    env->hreset_vector = 0x00000100UL;
 #endif
 }
 
-- 
1.6.0.2

Re: [Qemu-devel] [PATCH 05/30] PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450

[Andreas Färber]

Am 26.04.2013 20:21, schrieb Alexander Graf:
> From: Fabien Chouteau <chouteau@adacore.com>
> 
> According to the different user's manuals, the vector offset for system
> reset (both /HRESET and /SRESET) is 0x00100.
> 
> This patch may break support of some executables, as the power-on start
> address may change. For a specific board, if the power-on start address
> is different than HRESET vector (i.e. 0x00000100 or 0xfff00100), this
> should be fixed in board's initialization code.
> 
> Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
> Signed-off-by: Alexander Graf <agraf@suse.de>

According to git-bisect, this commit broke the prep machine (602).
Symptoms are a black screen with no VGA output from OHW or kernel.

Please suggest a fix.

Thanks,
Andreas

> ---
>  target-ppc/translate_init.c |   22 +++++++++++-----------
>  1 files changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 402ad2a..f1d150a 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -2645,7 +2645,7 @@ static void init_excp_MPC5xx (CPUPPCState *env)
>      env->ivor_mask = 0x0000FFF0UL;
>      env->ivpr_mask = 0xFFFF0000UL;
>      /* Hardware reset vector */
> -    env->hreset_vector = 0xFFFFFFFCUL;
> +    env->hreset_vector = 0x00000100UL;
>  #endif
>  }
>  
> @@ -2676,7 +2676,7 @@ static void init_excp_MPC8xx (CPUPPCState *env)
>      env->ivor_mask = 0x0000FFF0UL;
>      env->ivpr_mask = 0xFFFF0000UL;
>      /* Hardware reset vector */
> -    env->hreset_vector = 0xFFFFFFFCUL;
> +    env->hreset_vector = 0x00000100UL;
>  #endif
>  }
>  
> @@ -2701,7 +2701,7 @@ static void init_excp_G2 (CPUPPCState *env)
>      env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
>      env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
>      /* Hardware reset vector */
> -    env->hreset_vector = 0xFFFFFFFCUL;
> +    env->hreset_vector = 0x00000100UL;
>  #endif
>  }
>  
> @@ -2804,7 +2804,7 @@ static void init_excp_602 (CPUPPCState *env)
>      env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
>      env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
>      /* Hardware reset vector */
> -    env->hreset_vector = 0xFFFFFFFCUL;
> +    env->hreset_vector = 0x00000100UL;
>  #endif
>  }
>  
> @@ -2828,7 +2828,7 @@ static void init_excp_603 (CPUPPCState *env)
>      env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
>      env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
>      /* Hardware reset vector */
> -    env->hreset_vector = 0xFFFFFFFCUL;
> +    env->hreset_vector = 0x00000100UL;
>  #endif
>  }
>  
> @@ -2873,7 +2873,7 @@ static void init_excp_7x0 (CPUPPCState *env)
>      env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
>      env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
>      /* Hardware reset vector */
> -    env->hreset_vector = 0xFFFFFFFCUL;
> +    env->hreset_vector = 0x00000100UL;
>  #endif
>  }
>  
> @@ -2895,7 +2895,7 @@ static void init_excp_750cl (CPUPPCState *env)
>      env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
>      env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
>      /* Hardware reset vector */
> -    env->hreset_vector = 0xFFFFFFFCUL;
> +    env->hreset_vector = 0x00000100UL;
>  #endif
>  }
>  
> @@ -2917,7 +2917,7 @@ static void init_excp_750cx (CPUPPCState *env)
>      env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
>      env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
>      /* Hardware reset vector */
> -    env->hreset_vector = 0xFFFFFFFCUL;
> +    env->hreset_vector = 0x00000100UL;
>  #endif
>  }
>  
> @@ -2944,7 +2944,7 @@ static void init_excp_7x5 (CPUPPCState *env)
>      env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
>      env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
>      /* Hardware reset vector */
> -    env->hreset_vector = 0xFFFFFFFCUL;
> +    env->hreset_vector = 0x00000100UL;
>  #endif
>  }
>  
> @@ -2969,7 +2969,7 @@ static void init_excp_7400 (CPUPPCState *env)
>      env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
>      env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
>      /* Hardware reset vector */
> -    env->hreset_vector = 0xFFFFFFFCUL;
> +    env->hreset_vector = 0x00000100UL;
>  #endif
>  }
>  
> @@ -2996,7 +2996,7 @@ static void init_excp_7450 (CPUPPCState *env)
>      env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
>      env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
>      /* Hardware reset vector */
> -    env->hreset_vector = 0xFFFFFFFCUL;
> +    env->hreset_vector = 0x00000100UL;
>  #endif
>  }
>  
> 

Re: [Qemu-devel] [PATCH 05/30] PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450

[Fabien Chouteau]

On 04/28/2013 03:59 PM, Andreas Färber wrote:
> Am 26.04.2013 20:21, schrieb Alexander Graf:
>> From: Fabien Chouteau <chouteau@adacore.com>
>>
>> According to the different user's manuals, the vector offset for system
>> reset (both /HRESET and /SRESET) is 0x00100.
>>
>> This patch may break support of some executables, as the power-on start
>> address may change. For a specific board, if the power-on start address
>> is different than HRESET vector (i.e. 0x00000100 or 0xfff00100), this
>> should be fixed in board's initialization code.
>>
>> Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
>> Signed-off-by: Alexander Graf <agraf@suse.de>
> 
> According to git-bisect, this commit broke the prep machine (602).
> Symptoms are a black screen with no VGA output from OHW or kernel.
> 
> Please suggest a fix.
> 

Can you hand me the binaries so I can try to fix this?

-- 
Fabien Chouteau

Re: [Qemu-devel] [PATCH 05/30] PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450

[Andreas Färber]

Am 29.04.2013 12:38, schrieb Fabien Chouteau:
> On 04/28/2013 03:59 PM, Andreas Färber wrote:
>> Am 26.04.2013 20:21, schrieb Alexander Graf:
>>> From: Fabien Chouteau <chouteau@adacore.com>
>>>
>>> According to the different user's manuals, the vector offset for system
>>> reset (both /HRESET and /SRESET) is 0x00100.
>>>
>>> This patch may break support of some executables, as the power-on start
>>> address may change. For a specific board, if the power-on start address
>>> is different than HRESET vector (i.e. 0x00000100 or 0xfff00100), this
>>> should be fixed in board's initialization code.
>>>
>>> Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
>>> Signed-off-by: Alexander Graf <agraf@suse.de>
>>
>> According to git-bisect, this commit broke the prep machine (602).
>> Symptoms are a black screen with no VGA output from OHW or kernel.
>>
>> Please suggest a fix.
>>
> 
> Can you hand me the binaries so I can try to fix this?

The old ppc_rom.bin is still in qemu.git, so this should suffice:

./ppc-softmmu/qemu-system-ppc -M prep

Problem is, we can't really recompile that binary with changes - and to
switch to OpenBIOS after 1.5 to get rid of it, I need to test that my
incremental patches don't break anything. ;)

Andreas

Re: [Qemu-devel] [PATCH 05/30] PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450

[Aurelien Jarno]

On Mon, Apr 29, 2013 at 01:37:30PM +0200, Andreas Färber wrote:
> Am 29.04.2013 12:38, schrieb Fabien Chouteau:
> > On 04/28/2013 03:59 PM, Andreas Färber wrote:
> >> Am 26.04.2013 20:21, schrieb Alexander Graf:
> >>> From: Fabien Chouteau <chouteau@adacore.com>
> >>>
> >>> According to the different user's manuals, the vector offset for system
> >>> reset (both /HRESET and /SRESET) is 0x00100.
> >>>
> >>> This patch may break support of some executables, as the power-on start
> >>> address may change. For a specific board, if the power-on start address
> >>> is different than HRESET vector (i.e. 0x00000100 or 0xfff00100), this
> >>> should be fixed in board's initialization code.
> >>>
> >>> Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
> >>> Signed-off-by: Alexander Graf <agraf@suse.de>
> >>
> >> According to git-bisect, this commit broke the prep machine (602).
> >> Symptoms are a black screen with no VGA output from OHW or kernel.
> >>
> >> Please suggest a fix.
> >>
> > 
> > Can you hand me the binaries so I can try to fix this?
> 
> The old ppc_rom.bin is still in qemu.git, so this should suffice:
> 
> ./ppc-softmmu/qemu-system-ppc -M prep
> 
> Problem is, we can't really recompile that binary with changes - and to
> switch to OpenBIOS after 1.5 to get rid of it, I need to test that my
> incremental patches don't break anything. ;)

You can't really recompile this exact version, but you can recompile a
slightly older version, the one which is in the Debian archive:

http://packages.debian.org/source/unstable/openhackware

I don't know what are the difference between this one and the one in
QEMU though.

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

[Qemu-devel] [PATCH] Fix PReP NIP reset value

[Fabien Chouteau]

The value was changed by the "PPC: fix hreset_vector..." patch.

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
---
 hw/ppc/prep.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index cceab3e..2d0c4fe 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -427,6 +427,9 @@ static void ppc_prep_reset(void *opaque)
     PowerPCCPU *cpu = opaque;
 
     cpu_reset(CPU(cpu));
+
+    /* Reset address */
+    cpu->env.nip = 0xfffffffc;
 }
 
 /* PowerPC PREP hardware initialisation */
-- 
1.7.9.5

Re: [Qemu-devel] [PATCH] Fix PReP NIP reset value

[Alexander Graf]

On 04/30/2013 05:07 PM, Fabien Chouteau wrote:
> The value was changed by the "PPC: fix hreset_vector..." patch.
>
> Signed-off-by: Fabien Chouteau<chouteau@adacore.com>
> ---
>   hw/ppc/prep.c |    3 +++
>   1 file changed, 3 insertions(+)
>
> diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
> index cceab3e..2d0c4fe 100644
> --- a/hw/ppc/prep.c
> +++ b/hw/ppc/prep.c
> @@ -427,6 +427,9 @@ static void ppc_prep_reset(void *opaque)
>       PowerPCCPU *cpu = opaque;
>
>       cpu_reset(CPU(cpu));
> +
> +    /* Reset address */
> +    cpu->env.nip = 0xfffffffc;

Why does PREP reset at this vector? Is it architected to that? Does 601 
reset to that offset?

As an interim fix, I think this patch is ok however.


Alex

>   }
>
>   /* PowerPC PREP hardware initialisation */

Re: [Qemu-devel] [PATCH] Fix PReP NIP reset value

[Fabien Chouteau]

On 04/30/2013 05:24 PM, Alexander Graf wrote:
> On 04/30/2013 05:07 PM, Fabien Chouteau wrote:
>> The value was changed by the "PPC: fix hreset_vector..." patch.
>>
>> Signed-off-by: Fabien Chouteau<chouteau@adacore.com>
>> ---
>>   hw/ppc/prep.c |    3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
>> index cceab3e..2d0c4fe 100644
>> --- a/hw/ppc/prep.c
>> +++ b/hw/ppc/prep.c
>> @@ -427,6 +427,9 @@ static void ppc_prep_reset(void *opaque)
>>       PowerPCCPU *cpu = opaque;
>>
>>       cpu_reset(CPU(cpu));
>> +
>> +    /* Reset address */
>> +    cpu->env.nip = 0xfffffffc;
> 
> Why does PREP reset at this vector? Is it architected to that? Does 601 reset to that offset?
> 

I don't know why PReP reset here. As I said in the hreset_vector patch,
even if the core manual says that hreset is at 0xfff00100, the value is
in fact board specific. OpenHackWare expects 0xfffffffc as reset
address.

-- 
Fabien Chouteau

Re: [Qemu-devel] [PATCH] Fix PReP NIP reset value

[Alexander Graf]

On 04/30/2013 06:00 PM, Fabien Chouteau wrote:
> On 04/30/2013 05:24 PM, Alexander Graf wrote:
>> On 04/30/2013 05:07 PM, Fabien Chouteau wrote:
>>> The value was changed by the "PPC: fix hreset_vector..." patch.
>>>
>>> Signed-off-by: Fabien Chouteau<chouteau@adacore.com>
>>> ---
>>>    hw/ppc/prep.c |    3 +++
>>>    1 file changed, 3 insertions(+)
>>>
>>> diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
>>> index cceab3e..2d0c4fe 100644
>>> --- a/hw/ppc/prep.c
>>> +++ b/hw/ppc/prep.c
>>> @@ -427,6 +427,9 @@ static void ppc_prep_reset(void *opaque)
>>>        PowerPCCPU *cpu = opaque;
>>>
>>>        cpu_reset(CPU(cpu));
>>> +
>>> +    /* Reset address */
>>> +    cpu->env.nip = 0xfffffffc;
>> Why does PREP reset at this vector? Is it architected to that? Does 601 reset to that offset?
>>
> I don't know why PReP reset here. As I said in the hreset_vector patch,
> even if the core manual says that hreset is at 0xfff00100, the value is
> in fact board specific. OpenHackWare expects 0xfffffffc as reset
> address.

Do you have 601e or 601 specs handy? Maybe they have a different reset 
vector.

Maybe OHW is also just wrong ;).


Alex

Re: [Qemu-devel] [PATCH] Fix PReP NIP reset value

[Fabien Chouteau]

On 04/30/2013 06:06 PM, Alexander Graf wrote:
> On 04/30/2013 06:00 PM, Fabien Chouteau wrote:
>> On 04/30/2013 05:24 PM, Alexander Graf wrote:
>>> On 04/30/2013 05:07 PM, Fabien Chouteau wrote:
>>>> The value was changed by the "PPC: fix hreset_vector..." patch.
>>>>
>>>> Signed-off-by: Fabien Chouteau<chouteau@adacore.com>
>>>> ---
>>>>    hw/ppc/prep.c |    3 +++
>>>>    1 file changed, 3 insertions(+)
>>>>
>>>> diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
>>>> index cceab3e..2d0c4fe 100644
>>>> --- a/hw/ppc/prep.c
>>>> +++ b/hw/ppc/prep.c
>>>> @@ -427,6 +427,9 @@ static void ppc_prep_reset(void *opaque)
>>>>        PowerPCCPU *cpu = opaque;
>>>>
>>>>        cpu_reset(CPU(cpu));
>>>> +
>>>> +    /* Reset address */
>>>> +    cpu->env.nip = 0xfffffffc;
>>> Why does PREP reset at this vector? Is it architected to that? Does 601 reset to that offset?
>>>
>> I don't know why PReP reset here. As I said in the hreset_vector patch,
>> even if the core manual says that hreset is at 0xfff00100, the value is
>> in fact board specific. OpenHackWare expects 0xfffffffc as reset
>> address.
> 
> Do you have 601e or 601 specs handy? Maybe they have a different reset vector.
> 

None of the specs I have talk about 0xfffffffc...

> Maybe OHW is also just wrong ;).
> 

Maybe, but I have no way to prove it. 


-- 
Fabien Chouteau

Re: [Qemu-devel] [PATCH] Fix PReP NIP reset value

[Alexander Graf]

On 04/30/2013 06:23 PM, Fabien Chouteau wrote:
> On 04/30/2013 06:06 PM, Alexander Graf wrote:
>> On 04/30/2013 06:00 PM, Fabien Chouteau wrote:
>>> On 04/30/2013 05:24 PM, Alexander Graf wrote:
>>>> On 04/30/2013 05:07 PM, Fabien Chouteau wrote:
>>>>> The value was changed by the "PPC: fix hreset_vector..." patch.
>>>>>
>>>>> Signed-off-by: Fabien Chouteau<chouteau@adacore.com>
>>>>> ---
>>>>>     hw/ppc/prep.c |    3 +++
>>>>>     1 file changed, 3 insertions(+)
>>>>>
>>>>> diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
>>>>> index cceab3e..2d0c4fe 100644
>>>>> --- a/hw/ppc/prep.c
>>>>> +++ b/hw/ppc/prep.c
>>>>> @@ -427,6 +427,9 @@ static void ppc_prep_reset(void *opaque)
>>>>>         PowerPCCPU *cpu = opaque;
>>>>>
>>>>>         cpu_reset(CPU(cpu));
>>>>> +
>>>>> +    /* Reset address */
>>>>> +    cpu->env.nip = 0xfffffffc;
>>>> Why does PREP reset at this vector? Is it architected to that? Does 601 reset to that offset?
>>>>
>>> I don't know why PReP reset here. As I said in the hreset_vector patch,
>>> even if the core manual says that hreset is at 0xfff00100, the value is
>>> in fact board specific. OpenHackWare expects 0xfffffffc as reset
>>> address.
>> Do you have 601e or 601 specs handy? Maybe they have a different reset vector.
>>
> None of the specs I have talk about 0xfffffffc...
>
>> Maybe OHW is also just wrong ;).
>>
> Maybe, but I have no way to prove it.

Ok, let's leave it at that patch then ;). It'd be good to know if herve 
can boot his real images from 0x100. If so, OHW is likely at fault and 
we can revert the change once Andreas switched to OpenBIOS.


Alex

Re: [Qemu-devel] [PATCH] Fix PReP NIP reset value

[Hervé Poussineau]

Alexander Graf a écrit :
> On 04/30/2013 06:23 PM, Fabien Chouteau wrote:
>> On 04/30/2013 06:06 PM, Alexander Graf wrote:
>>> On 04/30/2013 06:00 PM, Fabien Chouteau wrote:
>>>> On 04/30/2013 05:24 PM, Alexander Graf wrote:
>>>>> On 04/30/2013 05:07 PM, Fabien Chouteau wrote:
>>>>>> The value was changed by the "PPC: fix hreset_vector..." patch.
>>>>>>
>>>>>> Signed-off-by: Fabien Chouteau<chouteau@adacore.com>
>>>>>> ---
>>>>>>     hw/ppc/prep.c |    3 +++
>>>>>>     1 file changed, 3 insertions(+)
>>>>>>
>>>>>> diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
>>>>>> index cceab3e..2d0c4fe 100644
>>>>>> --- a/hw/ppc/prep.c
>>>>>> +++ b/hw/ppc/prep.c
>>>>>> @@ -427,6 +427,9 @@ static void ppc_prep_reset(void *opaque)
>>>>>>         PowerPCCPU *cpu = opaque;
>>>>>>
>>>>>>         cpu_reset(CPU(cpu));
>>>>>> +
>>>>>> +    /* Reset address */
>>>>>> +    cpu->env.nip = 0xfffffffc;
>>>>> Why does PREP reset at this vector? Is it architected to that? Does 
>>>>> 601 reset to that offset?
>>>>>
>>>> I don't know why PReP reset here. As I said in the hreset_vector patch,
>>>> even if the core manual says that hreset is at 0xfff00100, the value is
>>>> in fact board specific. OpenHackWare expects 0xfffffffc as reset
>>>> address.
>>> Do you have 601e or 601 specs handy? Maybe they have a different 
>>> reset vector.
>>>
>> None of the specs I have talk about 0xfffffffc...
>>
>>> Maybe OHW is also just wrong ;).
>>>
>> Maybe, but I have no way to prove it.
> 
> Ok, let's leave it at that patch then ;). It'd be good to know if herve 
> can boot his real images from 0x100. If so, OHW is likely at fault and 
> we can revert the change once Andreas switched to OpenBIOS.

My real image only booted with a 601 and 604 which had a reset vector of 
0x00000100. With the committed change, 602 and 603 also work.
So I think that the change is correct, and that OpenHackWare incorrectly 
assumes a reset vector of 0xfffffffc...

Hervé

Re: [Qemu-devel] [PATCH] Fix PReP NIP reset value

[Fabien Chouteau]

On 04/30/2013 09:55 PM, Hervé Poussineau wrote:
> Alexander Graf a écrit :
>> On 04/30/2013 06:23 PM, Fabien Chouteau wrote:
>>> On 04/30/2013 06:06 PM, Alexander Graf wrote:
>>>> On 04/30/2013 06:00 PM, Fabien Chouteau wrote:
>>>>> On 04/30/2013 05:24 PM, Alexander Graf wrote:
>>>> Maybe OHW is also just wrong ;).
>>>>
>>> Maybe, but I have no way to prove it.
>>
>> Ok, let's leave it at that patch then ;). It'd be good to know if herve can boot his real images from 0x100. If so, OHW is likely at fault and we can revert the change once Andreas switched to OpenBIOS.
> 
> My real image only booted with a 601 and 604 which had a reset vector of 0x00000100. With the committed change, 602 and 603 also work.
> So I think that the change is correct, and that OpenHackWare incorrectly assumes a reset vector of 0xfffffffc...
> 

Thanks, so Alexander is right we should revert this patch when we
switch to OpenBios.


-- 
Fabien Chouteau

Re: [Qemu-devel] [PATCH] Fix PReP NIP reset value

[Andreas Färber]

Am 30.04.2013 17:07, schrieb Fabien Chouteau:
> The value was changed by the "PPC: fix hreset_vector..." patch.
> 
> Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
> ---
>  hw/ppc/prep.c |    3 +++
>  1 file changed, 3 insertions(+)

Thanks, applied to prep-up (with enhanced commit message):
http://repo.or.cz/w/qemu/afaerber.git/shortlog/refs/heads/prep-up

Andreas

> 
> diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
> index cceab3e..2d0c4fe 100644
> --- a/hw/ppc/prep.c
> +++ b/hw/ppc/prep.c
> @@ -427,6 +427,9 @@ static void ppc_prep_reset(void *opaque)
>      PowerPCCPU *cpu = opaque;
>  
>      cpu_reset(CPU(cpu));
> +
> +    /* Reset address */
> +    cpu->env.nip = 0xfffffffc;
>  }
>  
>  /* PowerPC PREP hardware initialisation */
> 

[Qemu-devel] [PATCH 06/30] PPC: Add breakpoint registers for 603 and e300

[Alexander Graf]

From: Fabien Chouteau <chouteau@adacore.com>

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/translate_init.c |   34 ++++++++++++++++++++++++++++++++++
 1 files changed, 34 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index f1d150a..a9bacd2 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -1149,6 +1149,13 @@ static void gen_spr_603 (CPUPPCState *env)
                  SPR_NOACCESS, SPR_NOACCESS,
                  &spr_read_generic, &spr_write_generic,
                  0x00000000);
+    /* Breakpoints */
+    /* XXX : not implemented */
+    spr_register(env, SPR_IABR, "IABR",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+
 }
 
 /* SPR specific to PowerPC G2 implementation */
@@ -4138,6 +4145,33 @@ static void init_proc_G2LE (CPUPPCState *env)
                  SPR_NOACCESS, SPR_NOACCESS,
                  &spr_read_generic, &spr_write_generic,
                  0x00000000);
+    /* Breakpoints */
+    /* XXX : not implemented */
+    spr_register(env, SPR_DABR, "DABR",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_DABR2, "DABR2",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_IABR2, "IABR2",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_IBCR, "IBCR",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_DBCR, "DBCR",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+
     /* Memory management */
     gen_low_BATs(env);
     gen_high_BATs(env);
-- 
1.6.0.2

[Qemu-devel] [PATCH 07/30] target-ppc: Fix narrow-mode add/sub carry output

[Alexander Graf]

From: Richard Henderson <rth@twiddle.net>

Broken in b5a73f8d8a57e940f9bbeb399a9e47897522ee9a, the carry itself was
fixed in 79482e5ab38a05ca8869040b0d8b8f451f16ff62.  But we still need to
produce the full 64-bit addition.

Simplify the conditions at the top of the functions for when we need a
new temporary.  Only plain addition is important enough to warrent avoiding
the temporary, and the extra tcg move op that would come with it.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/translate.c |   35 ++++++++++++++++++++++-------------
 1 files changed, 22 insertions(+), 13 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 294ab58..362ca3a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -768,22 +768,25 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
 {
     TCGv t0 = ret;
 
-    if (((compute_ca && add_ca) || compute_ov)
-        && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2)))  {
+    if (compute_ca || compute_ov) {
         t0 = tcg_temp_new();
     }
 
     if (compute_ca) {
         if (NARROW_MODE(ctx)) {
+            /* Caution: a non-obvious corner case of the spec is that we
+               must produce the *entire* 64-bit addition, but produce the
+               carry into bit 32.  */
             TCGv t1 = tcg_temp_new();
-            tcg_gen_ext32u_tl(t1, arg2);
-            tcg_gen_ext32u_tl(t0, arg1);
-            tcg_gen_add_tl(t0, t0, t1);
-            tcg_temp_free(t1);
+            tcg_gen_xor_tl(t1, arg1, arg2);        /* add without carry */
+            tcg_gen_add_tl(t0, arg1, arg2);
             if (add_ca) {
                 tcg_gen_add_tl(t0, t0, cpu_ca);
             }
-            tcg_gen_shri_tl(cpu_ca, t0, 32);
+            tcg_gen_xor_tl(cpu_ca, t0, t1);        /* bits changed w/ carry */
+            tcg_temp_free(t1);
+            tcg_gen_shri_tl(cpu_ca, cpu_ca, 32);   /* extract bit 32 */
+            tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
         } else {
             TCGv zero = tcg_const_tl(0);
             if (add_ca) {
@@ -1122,24 +1125,30 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
 {
     TCGv t0 = ret;
 
-    if (compute_ov && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2)))  {
+    if (compute_ca || compute_ov) {
         t0 = tcg_temp_new();
     }
 
     if (compute_ca) {
         /* dest = ~arg1 + arg2 [+ ca].  */
         if (NARROW_MODE(ctx)) {
+            /* Caution: a non-obvious corner case of the spec is that we
+               must produce the *entire* 64-bit addition, but produce the
+               carry into bit 32.  */
             TCGv inv1 = tcg_temp_new();
+            TCGv t1 = tcg_temp_new();
             tcg_gen_not_tl(inv1, arg1);
-            tcg_gen_ext32u_tl(t0, arg2);
-            tcg_gen_ext32u_tl(inv1, inv1);
             if (add_ca) {
-                tcg_gen_add_tl(t0, t0, cpu_ca);
+                tcg_gen_add_tl(t0, arg2, cpu_ca);
             } else {
-                tcg_gen_addi_tl(t0, t0, 1);
+                tcg_gen_addi_tl(t0, arg2, 1);
             }
+            tcg_gen_xor_tl(t1, arg2, inv1);         /* add without carry */
             tcg_gen_add_tl(t0, t0, inv1);
-            tcg_gen_shri_tl(cpu_ca, t0, 32);
+            tcg_gen_xor_tl(cpu_ca, t0, t1);         /* bits changes w/ carry */
+            tcg_temp_free(t1);
+            tcg_gen_shri_tl(cpu_ca, cpu_ca, 32);    /* extract bit 32 */
+            tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
         } else if (add_ca) {
             TCGv zero, inv1 = tcg_temp_new();
             tcg_gen_not_tl(inv1, arg1);
-- 
1.6.0.2

[Qemu-devel] [PATCH 08/30] linux-headers: Update to kvm/queue

[Alexander Graf]

Based on kvm.git queue branch with commit e1e2e605.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 linux-headers/asm-powerpc/kvm.h |    5 +++++
 linux-headers/linux/kvm.h       |    3 +++
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h
index 16064d0..ef072b1 100644
--- a/linux-headers/asm-powerpc/kvm.h
+++ b/linux-headers/asm-powerpc/kvm.h
@@ -417,4 +417,9 @@ struct kvm_get_htab_header {
 #define KVM_REG_PPC_EPCR	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x85)
 #define KVM_REG_PPC_EPR		(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x86)
 
+/* Timer Status Register OR/CLEAR interface */
+#define KVM_REG_PPC_OR_TSR	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x87)
+#define KVM_REG_PPC_CLEAR_TSR	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x88)
+#define KVM_REG_PPC_TCR		(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x89)
+#define KVM_REG_PPC_TSR		(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8a)
 #endif /* __LINUX_KVM_POWERPC_H */
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index caca979..eb02d8a 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -449,12 +449,15 @@ enum {
 	kvm_ioeventfd_flag_nr_datamatch,
 	kvm_ioeventfd_flag_nr_pio,
 	kvm_ioeventfd_flag_nr_deassign,
+	kvm_ioeventfd_flag_nr_virtio_ccw_notify,
 	kvm_ioeventfd_flag_nr_max,
 };
 
 #define KVM_IOEVENTFD_FLAG_DATAMATCH (1 << kvm_ioeventfd_flag_nr_datamatch)
 #define KVM_IOEVENTFD_FLAG_PIO       (1 << kvm_ioeventfd_flag_nr_pio)
 #define KVM_IOEVENTFD_FLAG_DEASSIGN  (1 << kvm_ioeventfd_flag_nr_deassign)
+#define KVM_IOEVENTFD_FLAG_VIRTIO_CCW_NOTIFY \
+	(1 << kvm_ioeventfd_flag_nr_virtio_ccw_notify)
 
 #define KVM_IOEVENTFD_VALID_FLAG_MASK  ((1 << kvm_ioeventfd_flag_nr_max) - 1)
 
-- 
1.6.0.2

[Qemu-devel] [PATCH 09/30] Enable kvm emulated watchdog

[Alexander Graf]

From: Bharat Bhushan <r65777@freescale.com>

Enable the KVM emulated watchdog if KVM supports (use the
capability enablement in watchdog handler). Also watchdog exit
(KVM_EXIT_WATCHDOG) handling is added.
Watchdog state machine is cleared whenever VM state changes to running.
This is to handle the cases like return from debug halt etc.

Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
[agraf: rebase to current code base, fix non-kvm cases]
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppc/ppc_booke.c   |   45 +++++++++++++++++++++++++++---
 target-ppc/kvm.c     |   74 ++++++++++++++++++++++++++++++++++++++++++++++++++
 target-ppc/kvm_ppc.h |   24 ++++++++++++++++
 3 files changed, 139 insertions(+), 4 deletions(-)

diff --git a/hw/ppc/ppc_booke.c b/hw/ppc/ppc_booke.c
index 585f53b..e41b036 100644
--- a/hw/ppc/ppc_booke.c
+++ b/hw/ppc/ppc_booke.c
@@ -28,6 +28,7 @@
 #include "hw/timer/m48t59.h"
 #include "qemu/log.h"
 #include "hw/loader.h"
+#include "kvm_ppc.h"
 
 
 /* Timer Control Register */
@@ -211,6 +212,7 @@ void store_booke_tsr(CPUPPCState *env, target_ulong val)
     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 
     env->spr[SPR_BOOKE_TSR] &= ~val;
+    kvmppc_clear_tsr_bits(cpu, val);
     booke_update_irq(cpu);
 }
 
@@ -222,6 +224,7 @@ void store_booke_tcr(CPUPPCState *env, target_ulong val)
 
     tb_env = env->tb_env;
     env->spr[SPR_BOOKE_TCR] = val;
+    kvmppc_set_tcr(cpu);
 
     booke_update_irq(cpu);
 
@@ -234,7 +237,6 @@ void store_booke_tcr(CPUPPCState *env, target_ulong val)
                              booke_get_wdt_target(env, tb_env),
                              &booke_timer->wdt_next,
                              booke_timer->wdt_timer);
-
 }
 
 static void ppc_booke_timer_reset_handle(void *opaque)
@@ -242,16 +244,39 @@ static void ppc_booke_timer_reset_handle(void *opaque)
     PowerPCCPU *cpu = opaque;
     CPUPPCState *env = &cpu->env;
 
-    env->spr[SPR_BOOKE_TSR] = 0;
-    env->spr[SPR_BOOKE_TCR] = 0;
+    store_booke_tcr(env, 0);
+    store_booke_tsr(env, -1);
+}
 
-    booke_update_irq(cpu);
+/*
+ * This function will be called whenever the CPU state changes.
+ * CPU states are defined "typedef enum RunState".
+ * Regarding timer, When CPU state changes to running after debug halt
+ * or similar cases which takes time then in between final watchdog
+ * expiry happenes. This will cause exit to QEMU and configured watchdog
+ * action will be taken. To avoid this we always clear the watchdog state when
+ * state changes to running.
+ */
+static void cpu_state_change_handler(void *opaque, int running, RunState state)
+{
+    PowerPCCPU *cpu = opaque;
+    CPUPPCState *env = &cpu->env;
+
+    if (!running) {
+        return;
+    }
+
+    /*
+     * Clear watchdog interrupt condition by clearing TSR.
+     */
+    store_booke_tsr(env, TSR_ENW | TSR_WIS | TSR_WRS_MASK);
 }
 
 void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags)
 {
     ppc_tb_t *tb_env;
     booke_timer_t *booke_timer;
+    int ret = 0;
 
     tb_env      = g_malloc0(sizeof(ppc_tb_t));
     booke_timer = g_malloc0(sizeof(booke_timer_t));
@@ -269,5 +294,17 @@ void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags)
     booke_timer->wdt_timer =
         qemu_new_timer_ns(vm_clock, &booke_wdt_cb, cpu);
 
+    ret = kvmppc_booke_watchdog_enable(cpu);
+
+    if (ret) {
+        /* TODO: Start the QEMU emulated watchdog if not running on KVM.
+         * Also start the QEMU emulated watchdog if KVM does not support
+         * emulated watchdog or somehow it is not enabled (supported but
+         * not enabled is though some bug and requires debugging :)).
+         */
+    }
+
+    qemu_add_vm_change_state_handler(cpu_state_change_handler, cpu);
+
     qemu_register_reset(ppc_booke_timer_reset_handle, cpu);
 }
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index f2658bb..759983d 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -37,6 +37,7 @@
 #include "hw/sysbus.h"
 #include "hw/ppc/spapr.h"
 #include "hw/ppc/spapr_vio.h"
+#include "sysemu/watchdog.h"
 
 //#define DEBUG_KVM
 
@@ -64,6 +65,7 @@ static int cap_spapr_tce;
 static int cap_hior;
 static int cap_one_reg;
 static int cap_epr;
+static int cap_ppc_watchdog;
 
 /* XXX We have a race condition where we actually have a level triggered
  *     interrupt, but the infrastructure can't expose that yet, so the guest
@@ -97,6 +99,7 @@ int kvm_arch_init(KVMState *s)
     cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG);
     cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR);
     cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR);
+    cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG);
 
     if (!cap_interrupt_level) {
         fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the "
@@ -1094,6 +1097,12 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
         run->epr.epr = ldl_phys(env->mpic_iack);
         ret = 0;
         break;
+    case KVM_EXIT_WATCHDOG:
+        dprintf("handle watchdog expiry\n");
+        watchdog_perform_action();
+        ret = 0;
+        break;
+
     default:
         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
         ret = -1;
@@ -1103,6 +1112,71 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
     return ret;
 }
 
+int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
+{
+    CPUState *cs = CPU(cpu);
+    uint32_t bits = tsr_bits;
+    struct kvm_one_reg reg = {
+        .id = KVM_REG_PPC_OR_TSR,
+        .addr = (uintptr_t) &bits,
+    };
+
+    return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+}
+
+int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
+{
+
+    CPUState *cs = CPU(cpu);
+    uint32_t bits = tsr_bits;
+    struct kvm_one_reg reg = {
+        .id = KVM_REG_PPC_CLEAR_TSR,
+        .addr = (uintptr_t) &bits,
+    };
+
+    return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+}
+
+int kvmppc_set_tcr(PowerPCCPU *cpu)
+{
+    CPUState *cs = CPU(cpu);
+    CPUPPCState *env = &cpu->env;
+    uint32_t tcr = env->spr[SPR_BOOKE_TCR];
+
+    struct kvm_one_reg reg = {
+        .id = KVM_REG_PPC_TCR,
+        .addr = (uintptr_t) &tcr,
+    };
+
+    return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+}
+
+int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu)
+{
+    CPUState *cs = CPU(cpu);
+    struct kvm_enable_cap encap = {};
+    int ret;
+
+    if (!kvm_enabled()) {
+        return -1;
+    }
+
+    if (!cap_ppc_watchdog) {
+        printf("warning: KVM does not support watchdog");
+        return -1;
+    }
+
+    encap.cap = KVM_CAP_PPC_BOOKE_WATCHDOG;
+    ret = kvm_vcpu_ioctl(cs, KVM_ENABLE_CAP, &encap);
+    if (ret < 0) {
+        fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n",
+                __func__, strerror(-ret));
+        return ret;
+    }
+
+    return ret;
+}
+
 static int read_cpuinfo(const char *field, char *value, int len)
 {
     FILE *f;
diff --git a/target-ppc/kvm_ppc.h b/target-ppc/kvm_ppc.h
index 600d632..771cfbe 100644
--- a/target-ppc/kvm_ppc.h
+++ b/target-ppc/kvm_ppc.h
@@ -25,6 +25,10 @@ int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level);
 void kvmppc_set_papr(PowerPCCPU *cpu);
 void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy);
 int kvmppc_smt_threads(void);
+int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits);
+int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits);
+int kvmppc_set_tcr(PowerPCCPU *cpu);
+int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu);
 #ifndef CONFIG_USER_ONLY
 off_t kvmppc_alloc_rma(const char *name, MemoryRegion *sysmem);
 void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t window_size, int *pfd);
@@ -90,6 +94,26 @@ static inline int kvmppc_smt_threads(void)
     return 1;
 }
 
+static inline int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
+{
+    return 0;
+}
+
+static inline int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
+{
+    return 0;
+}
+
+static inline int kvmppc_set_tcr(PowerPCCPU *cpu)
+{
+    return 0;
+}
+
+static inline int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu)
+{
+    return -1;
+}
+
 #ifndef CONFIG_USER_ONLY
 static inline off_t kvmppc_alloc_rma(const char *name, MemoryRegion *sysmem)
 {
-- 
1.6.0.2

[Qemu-devel] [PATCH 10/30] PPC: mac newworld: fix cpu NIP reset value

[Alexander Graf]

On -M mac99, we can run 970 CPUs. However, these CPUs define the initial
instruction pointer they start execution at as part of their bootup protocol,
so effectively it's up to the board to decide where they start.

This went unnoticed, because they used to boot at the same location our flash
was mapped to, but due to the recent reset changes our 970 CPUs want to reset
to 0x100 now, which is always a 0 instruction.

Set the initial IP to something reasonable for -M mac99.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Fabien Chouteau <chouteau@adacore.com>
---
 hw/ppc/mac_newworld.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 4a9b883..ce44e95 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -126,6 +126,8 @@ static void ppc_core99_reset(void *opaque)
     PowerPCCPU *cpu = opaque;
 
     cpu_reset(CPU(cpu));
+    /* 970 CPUs want to get their initial IP as part of their boot protocol */
+    cpu->env.nip = PROM_ADDR + 0x100;
 }
 
 /* PowerPC Mac99 hardware initialisation */
-- 
1.6.0.2

[Qemu-devel] [PATCH 11/30] PPC: Fix compile with profiling enabled

[Alexander Graf]

When using profiling, we rely on profile_getclock() being available
at our disposal. Somehow that function got moved from an indirect
include we used to have in translate-init.c, so that we were now
left not properly compiling anymore.

Add an explicit include to timer.h which defines profile_getclock,
so that we can compile again.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 translate-all.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/translate-all.c b/translate-all.c
index d04a116..da93608 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -55,6 +55,7 @@
 #else
 #include "exec/address-spaces.h"
 #endif
+#include "qemu/timer.h"
 
 #include "exec/cputlb.h"
 #include "translate-all.h"
-- 
1.6.0.2

[Qemu-devel] [PATCH 12/30] pseries: Fix incorrect calculation of RMA size in certain configurations

[Alexander Graf]

From: David Gibson <david@gibson.dropbear.id.au>

For the pseries machine, we need to advertise to the guest the size of its
RMA - that is the amount of memory it can access with the MMU off.  For HV
KVM, this is constrained by the hardware limitations on the virtual RMA of
one hash PTE per PTE group in the hash page table.  We already had code to
calculate this, but it was assuming the VRMA page size was the same as the
(host) backing page size for guest RAM.

In the case of a host kernel configured for 64k base page size, but running
on hardware (or firmware) which only allows 4k pages, the hose will do all
its allocations with a 64k page size, but still use 4k hardware pages for
actual mappings.  Usually that's transparent to things running under the
host, but in the case of the maximum VRMA size it's not.

This patch refines the RMA size calculation to instead use the largest
available hardware page size (as reported by the SMMU_INFO call) which is
less than or equal to the backing page size.  This now gives the correct
RMA size in all cases I've tested.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/kvm.c |   26 +++++++++++++++++++++++++-
 1 files changed, 25 insertions(+), 1 deletions(-)

diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 759983d..a1fa8d3 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -1446,11 +1446,35 @@ off_t kvmppc_alloc_rma(const char *name, MemoryRegion *sysmem)
 
 uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift)
 {
+    struct kvm_ppc_smmu_info info;
+    long rampagesize, best_page_shift;
+    int i;
+
     if (cap_ppc_rma >= 2) {
         return current_size;
     }
+
+    /* Find the largest hardware supported page size that's less than
+     * or equal to the (logical) backing page size of guest RAM */
+    kvm_get_smmu_info(ppc_env_get_cpu(first_cpu), &info);
+    rampagesize = getrampagesize();
+    best_page_shift = 0;
+
+    for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) {
+        struct kvm_ppc_one_seg_page_size *sps = &info.sps[i];
+
+        if (!sps->page_shift) {
+            continue;
+        }
+
+        if ((sps->page_shift > best_page_shift)
+            && ((1UL << sps->page_shift) <= rampagesize)) {
+            best_page_shift = sps->page_shift;
+        }
+    }
+
     return MIN(current_size,
-               getrampagesize() << (hash_shift - 7));
+               1ULL << (best_page_shift + hash_shift - 7));
 }
 #endif
 
-- 
1.6.0.2

[Qemu-devel] [PATCH 13/30] pseries: Fixes and enhancements to L1 cache properties

[Alexander Graf]

From: David Gibson <david@gibson.dropbear.id.au>

PAPR requires that the device tree's CPU nodes have several properties
with information about the L1 cache.  We already create two of these
properties, but with incorrect names - "[id]cache-block-size" instead
of "[id]-cache-block-size" (note the extra hyphen).

We were also missing some of the required cache properties.  This
patch adds the [id]-cache-line-size properties (which have the same
values as the block size properties in all current cases).  We also
add the [id]-cache-size properties.

Adding the cache sizes requires some extra infrastructure in the
general target-ppc code to (optionally) set the cache sizes for
various CPUs.  The CPU family descriptions in translate_init.c can set
these sizes - this patch adds correct information for POWER7, I'm
leaving other CPU types to people who have a physical example to
verify against.  In addition, for -cpu host we take the values
advertised by the host (if available) and use those to override the
information based on PVR.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppc/spapr.c              |   21 +++++++++++++++++++--
 target-ppc/cpu-qom.h        |    1 +
 target-ppc/kvm.c            |   10 ++++++++++
 target-ppc/translate_init.c |    3 +++
 4 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index e35c26f..c96ac81 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -308,6 +308,7 @@ static void *spapr_create_fdt_skel(const char *cpu_model,
 
     for (env = first_cpu; env != NULL; env = env->next_cpu) {
         CPUState *cpu = CPU(ppc_env_get_cpu(env));
+        PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
         int index = cpu->cpu_index;
         uint32_t servers_prop[smp_threads];
         uint32_t gservers_prop[smp_threads * 2];
@@ -333,10 +334,26 @@ static void *spapr_create_fdt_skel(const char *cpu_model,
         _FDT((fdt_property_string(fdt, "device_type", "cpu")));
 
         _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
-        _FDT((fdt_property_cell(fdt, "dcache-block-size",
+        _FDT((fdt_property_cell(fdt, "d-cache-block-size",
                                 env->dcache_line_size)));
-        _FDT((fdt_property_cell(fdt, "icache-block-size",
+        _FDT((fdt_property_cell(fdt, "d-cache-line-size",
+                                env->dcache_line_size)));
+        _FDT((fdt_property_cell(fdt, "i-cache-block-size",
+                                env->icache_line_size)));
+        _FDT((fdt_property_cell(fdt, "i-cache-line-size",
                                 env->icache_line_size)));
+
+        if (pcc->l1_dcache_size) {
+            _FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size)));
+        } else {
+            fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n");
+        }
+        if (pcc->l1_icache_size) {
+            _FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size)));
+        } else {
+            fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n");
+        }
+
         _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq)));
         _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq)));
         _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
index c27cef7..eb03a00 100644
--- a/target-ppc/cpu-qom.h
+++ b/target-ppc/cpu-qom.h
@@ -63,6 +63,7 @@ typedef struct PowerPCCPUClass {
     powerpc_input_t bus_model;
     uint32_t flags;
     int bfd_mach;
+    uint32_t l1_dcache_size, l1_icache_size;
 #if defined(TARGET_PPC64)
     const struct ppc_segment_page_sizes *sps;
 #endif
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index a1fa8d3..4e8f448 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -1603,6 +1603,8 @@ static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
     uint32_t vmx = kvmppc_get_vmx();
     uint32_t dfp = kvmppc_get_dfp();
+    uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size");
+    uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size");
 
     /* Now fix up the class with information we can query from the host */
 
@@ -1615,6 +1617,14 @@ static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
         /* Only override when we know what the host supports */
         alter_insns(&pcc->insns_flags2, PPC2_DFP, dfp);
     }
+
+    if (dcache_size != -1) {
+        pcc->l1_dcache_size = dcache_size;
+    }
+
+    if (icache_size != -1) {
+        pcc->l1_icache_size = icache_size;
+    }
 }
 
 int kvmppc_fixup_cpu(PowerPCCPU *cpu)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index a9bacd2..769f5fd 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7004,6 +7004,7 @@ static void init_proc_POWER7 (CPUPPCState *env)
     init_excp_POWER7(env);
     env->dcache_line_size = 128;
     env->icache_line_size = 128;
+
     /* Allocate hardware IRQ controller */
     ppcPOWER7_irq_init(env);
     /* Can't find information on what this should be on reset.  This
@@ -7041,6 +7042,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
     pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
                  POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
                  POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR;
+    pcc->l1_dcache_size = 0x8000;
+    pcc->l1_icache_size = 0x8000;
 }
 #endif /* defined (TARGET_PPC64) */
 
-- 
1.6.0.2

[Qemu-devel] [PATCH 14/30] target-ppc: Add more stubs for POWER7 PMU registers

[Alexander Graf]

From: David Gibson <david@gibson.dropbear.id.au>

In addition to the performance monitor registers found on nearly all
6xx chips, the POWER7 has two additional counters (PMC5 & PMC6) and an
extra control register (MMCRA).  This patch adds stub support for them to
qemu - the registers won't do anything, but with this change won't cause
illegal instruction traps accessing them.  They're also registered with
their ONE_REG ids, so their value will be kept in sync with KVM where
appropriate.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/cpu.h            |    1 +
 target-ppc/translate_init.c |   12 ++++++++++++
 2 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 99ebf7e..b8b09b9 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1445,6 +1445,7 @@ static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp)
 #define SPR_PERF2             (0x302)
 #define SPR_RCPU_MI_RBA2      (0x302)
 #define SPR_MPC_MI_AP         (0x302)
+#define SPR_MMCRA             (0x302)
 #define SPR_PERF3             (0x303)
 #define SPR_RCPU_MI_RBA3      (0x303)
 #define SPR_MPC_MI_EPN        (0x303)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 769f5fd..b0e3536 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -6977,6 +6977,18 @@ static void init_proc_POWER7 (CPUPPCState *env)
                      SPR_NOACCESS, SPR_NOACCESS,
                      &spr_read_generic, &spr_write_generic,
                      KVM_REG_PPC_DSCR, 0x00000000);
+    spr_register_kvm(env, SPR_MMCRA, "SPR_MMCRA",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_MMCRA, 0x00000000);
+    spr_register_kvm(env, SPR_PMC5, "SPR_PMC5",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_PMC5, 0x00000000);
+    spr_register_kvm(env, SPR_PMC6, "SPR_PMC6",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_PMC6, 0x00000000);
 #endif /* !CONFIG_USER_ONLY */
     /* Memory management */
     /* XXX : not implemented */
-- 
1.6.0.2

[Qemu-devel] [PATCH 15/30] pseries: Fix some small errors in XICS logic

[Alexander Graf]

From: David Gibson <david@gibson.dropbear.id.au>

Under certain circumstances the emulation for the pseries "XICS" interrupt
controller was clearing a pending interrupt from the XISR register, without
also clearing the corresponding priority variable.  This will cause
problems later when can trigger sanity checks in the under-development
in-kernel XICS implementation.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppc/xics.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/hw/ppc/xics.c b/hw/ppc/xics.c
index 8e1e85e..1b25075 100644
--- a/hw/ppc/xics.c
+++ b/hw/ppc/xics.c
@@ -101,6 +101,7 @@ static void icp_set_cppr(struct icp_state *icp, int server, uint8_t cppr)
         if (XISR(ss) && (cppr <= ss->pending_priority)) {
             old_xisr = XISR(ss);
             ss->xirr &= ~XISR_MASK; /* Clear XISR */
+            ss->pending_priority = 0xff;
             qemu_irq_lower(ss->output);
             ics_reject(icp->ics, old_xisr);
         }
@@ -127,6 +128,7 @@ static uint32_t icp_accept(struct icp_server_state *ss)
 
     qemu_irq_lower(ss->output);
     ss->xirr = ss->pending_priority << 24;
+    ss->pending_priority = 0xff;
 
     trace_xics_icp_accept(xirr, ss->xirr);
 
-- 
1.6.0.2

[Qemu-devel] [PATCH 16/30] target-ppc: Synchronize VPA state with KVM

[Alexander Graf]

From: David Gibson <david@gibson.dropbear.id.au>

For PAPR guests, KVM tracks the various areas registered with the
H_REGISTER_VPA hypercall.  For full emulation, of course, these are tracked
within qemu.  At present these values are not synchronized.  This is a
problem for reset (qemu's reset of the VPA address is not pushed to KVM)
and will also be a problem for savevm / migration.

The kernel now supports accessing the VPA state via the ONE_REG interface,
this patch adds code to qemu to use that interface to keep the qemu and
KVM ideas of the VPA state synchronized.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/kvm.c |  120 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 120 insertions(+), 0 deletions(-)

diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 4e8f448..725071e 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -66,6 +66,7 @@ static int cap_hior;
 static int cap_one_reg;
 static int cap_epr;
 static int cap_ppc_watchdog;
+static int cap_papr;
 
 /* XXX We have a race condition where we actually have a level triggered
  *     interrupt, but the infrastructure can't expose that yet, so the guest
@@ -100,6 +101,8 @@ int kvm_arch_init(KVMState *s)
     cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR);
     cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR);
     cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG);
+    /* Note: we don't set cap_papr here, because this capability is
+     * only activated after this by kvmppc_set_papr() */
 
     if (!cap_interrupt_level) {
         fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the "
@@ -657,6 +660,103 @@ static int kvm_get_fp(CPUState *cs)
     return 0;
 }
 
+#if defined(TARGET_PPC64)
+static int kvm_get_vpa(CPUState *cs)
+{
+    PowerPCCPU *cpu = POWERPC_CPU(cs);
+    CPUPPCState *env = &cpu->env;
+    struct kvm_one_reg reg;
+    int ret;
+
+    reg.id = KVM_REG_PPC_VPA_ADDR;
+    reg.addr = (uintptr_t)&env->vpa_addr;
+    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+    if (ret < 0) {
+        dprintf("Unable to get VPA address from KVM: %s\n", strerror(errno));
+        return ret;
+    }
+
+    assert((uintptr_t)&env->slb_shadow_size
+           == ((uintptr_t)&env->slb_shadow_addr + 8));
+    reg.id = KVM_REG_PPC_VPA_SLB;
+    reg.addr = (uintptr_t)&env->slb_shadow_addr;
+    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+    if (ret < 0) {
+        dprintf("Unable to get SLB shadow state from KVM: %s\n",
+                strerror(errno));
+        return ret;
+    }
+
+    assert((uintptr_t)&env->dtl_size == ((uintptr_t)&env->dtl_addr + 8));
+    reg.id = KVM_REG_PPC_VPA_DTL;
+    reg.addr = (uintptr_t)&env->dtl_addr;
+    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+    if (ret < 0) {
+        dprintf("Unable to get dispatch trace log state from KVM: %s\n",
+                strerror(errno));
+        return ret;
+    }
+
+    return 0;
+}
+
+static int kvm_put_vpa(CPUState *cs)
+{
+    PowerPCCPU *cpu = POWERPC_CPU(cs);
+    CPUPPCState *env = &cpu->env;
+    struct kvm_one_reg reg;
+    int ret;
+
+    /* SLB shadow or DTL can't be registered unless a master VPA is
+     * registered.  That means when restoring state, if a VPA *is*
+     * registered, we need to set that up first.  If not, we need to
+     * deregister the others before deregistering the master VPA */
+    assert(env->vpa_addr || !(env->slb_shadow_addr || env->dtl_addr));
+
+    if (env->vpa_addr) {
+        reg.id = KVM_REG_PPC_VPA_ADDR;
+        reg.addr = (uintptr_t)&env->vpa_addr;
+        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+        if (ret < 0) {
+            dprintf("Unable to set VPA address to KVM: %s\n", strerror(errno));
+            return ret;
+        }
+    }
+
+    assert((uintptr_t)&env->slb_shadow_size
+           == ((uintptr_t)&env->slb_shadow_addr + 8));
+    reg.id = KVM_REG_PPC_VPA_SLB;
+    reg.addr = (uintptr_t)&env->slb_shadow_addr;
+    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+    if (ret < 0) {
+        dprintf("Unable to set SLB shadow state to KVM: %s\n", strerror(errno));
+        return ret;
+    }
+
+    assert((uintptr_t)&env->dtl_size == ((uintptr_t)&env->dtl_addr + 8));
+    reg.id = KVM_REG_PPC_VPA_DTL;
+    reg.addr = (uintptr_t)&env->dtl_addr;
+    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+    if (ret < 0) {
+        dprintf("Unable to set dispatch trace log state to KVM: %s\n",
+                strerror(errno));
+        return ret;
+    }
+
+    if (!env->vpa_addr) {
+        reg.id = KVM_REG_PPC_VPA_ADDR;
+        reg.addr = (uintptr_t)&env->vpa_addr;
+        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+        if (ret < 0) {
+            dprintf("Unable to set VPA address to KVM: %s\n", strerror(errno));
+            return ret;
+        }
+    }
+
+    return 0;
+}
+#endif /* TARGET_PPC64 */
+
 int kvm_arch_put_registers(CPUState *cs, int level)
 {
     PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -757,6 +857,14 @@ int kvm_arch_put_registers(CPUState *cs, int level)
                 kvm_put_one_spr(cs, id, i);
             }
         }
+
+#ifdef TARGET_PPC64
+        if (cap_papr) {
+            if (kvm_put_vpa(cs) < 0) {
+                dprintf("Warning: Unable to set VPA information to KVM\n");
+            }
+        }
+#endif /* TARGET_PPC64 */
     }
 
     return ret;
@@ -958,6 +1066,14 @@ int kvm_arch_get_registers(CPUState *cs)
                 kvm_get_one_spr(cs, id, i);
             }
         }
+
+#ifdef TARGET_PPC64
+        if (cap_papr) {
+            if (kvm_get_vpa(cs) < 0) {
+                dprintf("Warning: Unable to get VPA information from KVM\n");
+            }
+        }
+#endif
     }
 
     return 0;
@@ -1377,6 +1493,10 @@ void kvmppc_set_papr(PowerPCCPU *cpu)
     if (ret) {
         cpu_abort(env, "This KVM version does not support PAPR\n");
     }
+
+    /* Update the capability flag so we sync the right information
+     * with kvm */
+    cap_papr = 1;
 }
 
 void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy)
-- 
1.6.0.2

[Qemu-devel] [PATCH 17/30] pseries: Convert VIO code to QOM style type safe(ish) casts

[Alexander Graf]

From: David Gibson <david@gibson.dropbear.id.au>

Curerntly the pseries VIO device code contains quite a few explicit
uses of DO_UPCAST and plain C casts.  This is (obviously) type unsafe,
and not the conventional way of doing things in the QOM model.  This
patch converts the code to use the QOM convention of per-type macros
to do verified casts with OBJECT_CHECK().

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/char/spapr_vty.c    |   18 +++++++++++-------
 hw/net/spapr_llan.c    |   24 ++++++++++++++----------
 hw/nvram/spapr_nvram.c |   10 +++++++---
 hw/ppc/spapr_vio.c     |    4 ++--
 hw/scsi/spapr_vscsi.c  |   15 +++++++++------
 5 files changed, 43 insertions(+), 28 deletions(-)

diff --git a/hw/char/spapr_vty.c b/hw/char/spapr_vty.c
index afcec1f..2993848 100644
--- a/hw/char/spapr_vty.c
+++ b/hw/char/spapr_vty.c
@@ -12,16 +12,20 @@ typedef struct VIOsPAPRVTYDevice {
     uint8_t buf[VTERM_BUFSIZE];
 } VIOsPAPRVTYDevice;
 
+#define TYPE_VIO_SPAPR_VTY_DEVICE "spapr-vty"
+#define VIO_SPAPR_VTY_DEVICE(obj) \
+     OBJECT_CHECK(VIOsPAPRVTYDevice, (obj), TYPE_VIO_SPAPR_VTY_DEVICE)
+
 static int vty_can_receive(void *opaque)
 {
-    VIOsPAPRVTYDevice *dev = (VIOsPAPRVTYDevice *)opaque;
+    VIOsPAPRVTYDevice *dev = VIO_SPAPR_VTY_DEVICE(opaque);
 
     return (dev->in - dev->out) < VTERM_BUFSIZE;
 }
 
 static void vty_receive(void *opaque, const uint8_t *buf, int size)
 {
-    VIOsPAPRVTYDevice *dev = (VIOsPAPRVTYDevice *)opaque;
+    VIOsPAPRVTYDevice *dev = VIO_SPAPR_VTY_DEVICE(opaque);
     int i;
 
     if ((dev->in == dev->out) && size) {
@@ -36,7 +40,7 @@ static void vty_receive(void *opaque, const uint8_t *buf, int size)
 
 static int vty_getchars(VIOsPAPRDevice *sdev, uint8_t *buf, int max)
 {
-    VIOsPAPRVTYDevice *dev = (VIOsPAPRVTYDevice *)sdev;
+    VIOsPAPRVTYDevice *dev = VIO_SPAPR_VTY_DEVICE(sdev);
     int n = 0;
 
     while ((n < max) && (dev->out != dev->in)) {
@@ -48,7 +52,7 @@ static int vty_getchars(VIOsPAPRDevice *sdev, uint8_t *buf, int max)
 
 void vty_putchars(VIOsPAPRDevice *sdev, uint8_t *buf, int len)
 {
-    VIOsPAPRVTYDevice *dev = (VIOsPAPRVTYDevice *)sdev;
+    VIOsPAPRVTYDevice *dev = VIO_SPAPR_VTY_DEVICE(sdev);
 
     /* FIXME: should check the qemu_chr_fe_write() return value */
     qemu_chr_fe_write(dev->chardev, buf, len);
@@ -56,7 +60,7 @@ void vty_putchars(VIOsPAPRDevice *sdev, uint8_t *buf, int len)
 
 static int spapr_vty_init(VIOsPAPRDevice *sdev)
 {
-    VIOsPAPRVTYDevice *dev = (VIOsPAPRVTYDevice *)sdev;
+    VIOsPAPRVTYDevice *dev = VIO_SPAPR_VTY_DEVICE(sdev);
 
     if (!dev->chardev) {
         fprintf(stderr, "spapr-vty: Can't create vty without a chardev!\n");
@@ -151,7 +155,7 @@ static void spapr_vty_class_init(ObjectClass *klass, void *data)
 }
 
 static const TypeInfo spapr_vty_info = {
-    .name          = "spapr-vty",
+    .name          = TYPE_VIO_SPAPR_VTY_DEVICE,
     .parent        = TYPE_VIO_SPAPR_DEVICE,
     .instance_size = sizeof(VIOsPAPRVTYDevice),
     .class_init    = spapr_vty_class_init,
@@ -177,7 +181,7 @@ VIOsPAPRDevice *spapr_vty_get_default(VIOsPAPRBus *bus)
             continue;
         }
 
-        sdev = DO_UPCAST(VIOsPAPRDevice, qdev, iter);
+        sdev = VIO_SPAPR_DEVICE(iter);
 
         /* First VTY we've found, so it is selected for now */
         if (!selected) {
diff --git a/hw/net/spapr_llan.c b/hw/net/spapr_llan.c
index 34332f2..3150add 100644
--- a/hw/net/spapr_llan.c
+++ b/hw/net/spapr_llan.c
@@ -73,6 +73,10 @@ typedef uint64_t vlan_bd_t;
 #define VLAN_RX_BDS_OFF      16
 #define VLAN_MAX_BUFS        ((SPAPR_TCE_PAGE_SIZE - VLAN_RX_BDS_OFF) / 8)
 
+#define TYPE_VIO_SPAPR_VLAN_DEVICE "spapr-vlan"
+#define VIO_SPAPR_VLAN_DEVICE(obj) \
+     OBJECT_CHECK(VIOsPAPRVLANDevice, (obj), TYPE_VIO_SPAPR_VLAN_DEVICE)
+
 typedef struct VIOsPAPRVLANDevice {
     VIOsPAPRDevice sdev;
     NICConf nicconf;
@@ -93,8 +97,8 @@ static int spapr_vlan_can_receive(NetClientState *nc)
 static ssize_t spapr_vlan_receive(NetClientState *nc, const uint8_t *buf,
                                   size_t size)
 {
-    VIOsPAPRDevice *sdev = qemu_get_nic_opaque(nc);
-    VIOsPAPRVLANDevice *dev = (VIOsPAPRVLANDevice *)sdev;
+    VIOsPAPRVLANDevice *dev = qemu_get_nic_opaque(nc);
+    VIOsPAPRDevice *sdev = VIO_SPAPR_DEVICE(dev);
     vlan_bd_t rxq_bd = vio_ldq(sdev, dev->buf_list + VLAN_RXQ_BD_OFF);
     vlan_bd_t bd;
     int buf_ptr = dev->use_buf_ptr;
@@ -192,7 +196,7 @@ static NetClientInfo net_spapr_vlan_info = {
 
 static void spapr_vlan_reset(VIOsPAPRDevice *sdev)
 {
-    VIOsPAPRVLANDevice *dev = DO_UPCAST(VIOsPAPRVLANDevice, sdev, sdev);
+    VIOsPAPRVLANDevice *dev = VIO_SPAPR_VLAN_DEVICE(sdev);
 
     dev->buf_list = 0;
     dev->rx_bufs = 0;
@@ -201,7 +205,7 @@ static void spapr_vlan_reset(VIOsPAPRDevice *sdev)
 
 static int spapr_vlan_init(VIOsPAPRDevice *sdev)
 {
-    VIOsPAPRVLANDevice *dev = (VIOsPAPRVLANDevice *)sdev;
+    VIOsPAPRVLANDevice *dev = VIO_SPAPR_VLAN_DEVICE(sdev);
 
     qemu_macaddr_default_if_unset(&dev->nicconf.macaddr);
 
@@ -225,7 +229,7 @@ void spapr_vlan_create(VIOsPAPRBus *bus, NICInfo *nd)
 
 static int spapr_vlan_devnode(VIOsPAPRDevice *dev, void *fdt, int node_off)
 {
-    VIOsPAPRVLANDevice *vdev = (VIOsPAPRVLANDevice *)dev;
+    VIOsPAPRVLANDevice *vdev = VIO_SPAPR_VLAN_DEVICE(dev);
     uint8_t padded_mac[8] = {0, 0};
     int ret;
 
@@ -282,7 +286,7 @@ static target_ulong h_register_logical_lan(PowerPCCPU *cpu,
     target_ulong rec_queue = args[2];
     target_ulong filter_list = args[3];
     VIOsPAPRDevice *sdev = spapr_vio_find_by_reg(spapr->vio_bus, reg);
-    VIOsPAPRVLANDevice *dev = (VIOsPAPRVLANDevice *)sdev;
+    VIOsPAPRVLANDevice *dev = VIO_SPAPR_VLAN_DEVICE(sdev);
     vlan_bd_t filter_list_bd;
 
     if (!dev) {
@@ -341,7 +345,7 @@ static target_ulong h_free_logical_lan(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 {
     target_ulong reg = args[0];
     VIOsPAPRDevice *sdev = spapr_vio_find_by_reg(spapr->vio_bus, reg);
-    VIOsPAPRVLANDevice *dev = (VIOsPAPRVLANDevice *)sdev;
+    VIOsPAPRVLANDevice *dev = VIO_SPAPR_VLAN_DEVICE(sdev);
 
     if (!dev) {
         return H_PARAMETER;
@@ -365,7 +369,7 @@ static target_ulong h_add_logical_lan_buffer(PowerPCCPU *cpu,
     target_ulong reg = args[0];
     target_ulong buf = args[1];
     VIOsPAPRDevice *sdev = spapr_vio_find_by_reg(spapr->vio_bus, reg);
-    VIOsPAPRVLANDevice *dev = (VIOsPAPRVLANDevice *)sdev;
+    VIOsPAPRVLANDevice *dev = VIO_SPAPR_VLAN_DEVICE(sdev);
     vlan_bd_t bd;
 
     dprintf("H_ADD_LOGICAL_LAN_BUFFER(0x" TARGET_FMT_lx
@@ -413,7 +417,7 @@ static target_ulong h_send_logical_lan(PowerPCCPU *cpu, sPAPREnvironment *spapr,
     target_ulong *bufs = args + 1;
     target_ulong continue_token = args[7];
     VIOsPAPRDevice *sdev = spapr_vio_find_by_reg(spapr->vio_bus, reg);
-    VIOsPAPRVLANDevice *dev = (VIOsPAPRVLANDevice *)sdev;
+    VIOsPAPRVLANDevice *dev = VIO_SPAPR_VLAN_DEVICE(sdev);
     unsigned total_len;
     uint8_t *lbuf, *p;
     int i, nbufs;
@@ -511,7 +515,7 @@ static void spapr_vlan_class_init(ObjectClass *klass, void *data)
 }
 
 static const TypeInfo spapr_vlan_info = {
-    .name          = "spapr-vlan",
+    .name          = TYPE_VIO_SPAPR_VLAN_DEVICE,
     .parent        = TYPE_VIO_SPAPR_DEVICE,
     .instance_size = sizeof(VIOsPAPRVLANDevice),
     .class_init    = spapr_vlan_class_init,
diff --git a/hw/nvram/spapr_nvram.c b/hw/nvram/spapr_nvram.c
index 0cc6cba..1eb05c9 100644
--- a/hw/nvram/spapr_nvram.c
+++ b/hw/nvram/spapr_nvram.c
@@ -36,6 +36,10 @@ typedef struct sPAPRNVRAM {
     BlockDriverState *drive;
 } sPAPRNVRAM;
 
+#define TYPE_VIO_SPAPR_NVRAM "spapr-nvram"
+#define VIO_SPAPR_NVRAM(obj) \
+     OBJECT_CHECK(sPAPRNVRAM, (obj), TYPE_VIO_SPAPR_NVRAM)
+
 #define MIN_NVRAM_SIZE 8192
 #define DEFAULT_NVRAM_SIZE 65536
 #define MAX_NVRAM_SIZE (UINT16_MAX * 16)
@@ -134,7 +138,7 @@ static void rtas_nvram_store(sPAPREnvironment *spapr,
 
 static int spapr_nvram_init(VIOsPAPRDevice *dev)
 {
-    sPAPRNVRAM *nvram = (sPAPRNVRAM *)dev;
+    sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(dev);
 
     if (nvram->drive) {
         nvram->size = bdrv_getlength(nvram->drive);
@@ -157,7 +161,7 @@ static int spapr_nvram_init(VIOsPAPRDevice *dev)
 
 static int spapr_nvram_devnode(VIOsPAPRDevice *dev, void *fdt, int node_off)
 {
-    sPAPRNVRAM *nvram = (sPAPRNVRAM *)dev;
+    sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(dev);
 
     return fdt_setprop_cell(fdt, node_off, "#bytes", nvram->size);
 }
@@ -182,7 +186,7 @@ static void spapr_nvram_class_init(ObjectClass *klass, void *data)
 }
 
 static const TypeInfo spapr_nvram_type_info = {
-    .name          = "spapr-nvram",
+    .name          = TYPE_VIO_SPAPR_NVRAM,
     .parent        = TYPE_VIO_SPAPR_DEVICE,
     .instance_size = sizeof(sPAPRNVRAM),
     .class_init    = spapr_nvram_class_init,
diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c
index 4dbc315..ccc794d 100644
--- a/hw/ppc/spapr_vio.c
+++ b/hw/ppc/spapr_vio.c
@@ -379,7 +379,7 @@ static VIOsPAPRDevice *reg_conflict(VIOsPAPRDevice *dev)
      * the given dev might already be in the list.
      */
     QTAILQ_FOREACH(kid, &bus->bus.children, sibling) {
-        other = DO_UPCAST(VIOsPAPRDevice, qdev, kid->child);
+        other = VIO_SPAPR_DEVICE(kid->child);
 
         if (other != dev && other->reg == dev->reg) {
             return other;
@@ -391,7 +391,7 @@ static VIOsPAPRDevice *reg_conflict(VIOsPAPRDevice *dev)
 
 static void spapr_vio_busdev_reset(DeviceState *qdev)
 {
-    VIOsPAPRDevice *dev = DO_UPCAST(VIOsPAPRDevice, qdev, qdev);
+    VIOsPAPRDevice *dev = VIO_SPAPR_DEVICE(qdev);
     VIOsPAPRDeviceClass *pc = VIO_SPAPR_DEVICE_GET_CLASS(dev);
 
     /* Shut down the request queue and TCEs if necessary */
diff --git a/hw/scsi/spapr_vscsi.c b/hw/scsi/spapr_vscsi.c
index 999a463..3d322d5 100644
--- a/hw/scsi/spapr_vscsi.c
+++ b/hw/scsi/spapr_vscsi.c
@@ -91,6 +91,9 @@ typedef struct vscsi_req {
     int                     total_desc;
 } vscsi_req;
 
+#define TYPE_VIO_SPAPR_VSCSI_DEVICE "spapr-vscsi"
+#define VIO_SPAPR_VSCSI_DEVICE(obj) \
+     OBJECT_CHECK(VSCSIState, (obj), TYPE_VIO_SPAPR_VSCSI_DEVICE)
 
 typedef struct {
     VIOsPAPRDevice vdev;
@@ -461,7 +464,7 @@ static int vscsi_preprocess_desc(vscsi_req *req)
 /* Callback to indicate that the SCSI layer has completed a transfer.  */
 static void vscsi_transfer_data(SCSIRequest *sreq, uint32_t len)
 {
-    VSCSIState *s = DO_UPCAST(VSCSIState, vdev.qdev, sreq->bus->qbus.parent);
+    VSCSIState *s = VIO_SPAPR_VSCSI_DEVICE(sreq->bus->qbus.parent);
     vscsi_req *req = sreq->hba_private;
     uint8_t *buf;
     int rc = 0;
@@ -492,7 +495,7 @@ static void vscsi_transfer_data(SCSIRequest *sreq, uint32_t len)
 /* Callback to indicate that the SCSI layer has completed a transfer.  */
 static void vscsi_command_complete(SCSIRequest *sreq, uint32_t status, size_t resid)
 {
-    VSCSIState *s = DO_UPCAST(VSCSIState, vdev.qdev, sreq->bus->qbus.parent);
+    VSCSIState *s = VIO_SPAPR_VSCSI_DEVICE(sreq->bus->qbus.parent);
     vscsi_req *req = sreq->hba_private;
     int32_t res_in = 0, res_out = 0;
 
@@ -827,7 +830,7 @@ static void vscsi_got_payload(VSCSIState *s, vscsi_crq *crq)
 
 static int vscsi_do_crq(struct VIOsPAPRDevice *dev, uint8_t *crq_data)
 {
-    VSCSIState *s = DO_UPCAST(VSCSIState, vdev, dev);
+    VSCSIState *s = VIO_SPAPR_VSCSI_DEVICE(dev);
     vscsi_crq crq;
 
     memcpy(crq.raw, crq_data, 16);
@@ -897,7 +900,7 @@ static const struct SCSIBusInfo vscsi_scsi_info = {
 
 static void spapr_vscsi_reset(VIOsPAPRDevice *dev)
 {
-    VSCSIState *s = DO_UPCAST(VSCSIState, vdev, dev);
+    VSCSIState *s = VIO_SPAPR_VSCSI_DEVICE(dev);
     int i;
 
     memset(s->reqs, 0, sizeof(s->reqs));
@@ -908,7 +911,7 @@ static void spapr_vscsi_reset(VIOsPAPRDevice *dev)
 
 static int spapr_vscsi_init(VIOsPAPRDevice *dev)
 {
-    VSCSIState *s = DO_UPCAST(VSCSIState, vdev, dev);
+    VSCSIState *s = VIO_SPAPR_VSCSI_DEVICE(dev);
 
     dev->crq.SendFunc = vscsi_do_crq;
 
@@ -968,7 +971,7 @@ static void spapr_vscsi_class_init(ObjectClass *klass, void *data)
 }
 
 static const TypeInfo spapr_vscsi_info = {
-    .name          = "spapr-vscsi",
+    .name          = TYPE_VIO_SPAPR_VSCSI_DEVICE,
     .parent        = TYPE_VIO_SPAPR_DEVICE,
     .instance_size = sizeof(VSCSIState),
     .class_init    = spapr_vscsi_class_init,
-- 
1.6.0.2

[Qemu-devel] [PATCH 18/30] pseries: Generate device paths for VIO devices

[Alexander Graf]

From: David Gibson <david@gibson.dropbear.id.au>

This patch implements a get_dev_path qdev hook for the pseries paravirtual
VIO bus.  With upcoming savevm support, this will become very important for
scsi disks hanging of VIO virtual SCSI adapters.  scsibus_get_dev_path
uses the get_dev_path of the parent adapter if available, but otherwise
just uses a local channel/target/lun number to identify the device.  So if
two disks are present in the system having the same target and lun on
seperate VIO scsi adapters, savevm cannot distinguish them.  Since the
conventional way of using VSCSI adapters is to have just one disk per
adapter, such a conflict is very likely.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppc/spapr_vio.c |   37 +++++++++++++++++++++++--------------
 1 files changed, 23 insertions(+), 14 deletions(-)

diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c
index ccc794d..1405c32 100644
--- a/hw/ppc/spapr_vio.c
+++ b/hw/ppc/spapr_vio.c
@@ -53,9 +53,29 @@ static Property spapr_vio_props[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
+static char *spapr_vio_get_dev_name(DeviceState *qdev)
+{
+    VIOsPAPRDevice *dev = VIO_SPAPR_DEVICE(qdev);
+    VIOsPAPRDeviceClass *pc = VIO_SPAPR_DEVICE_GET_CLASS(dev);
+    char *name;
+
+    /* Device tree style name device@reg */
+    name = g_strdup_printf("%s@%x", pc->dt_name, dev->reg);
+
+    return name;
+}
+
+static void spapr_vio_bus_class_init(ObjectClass *klass, void *data)
+{
+    BusClass *k = BUS_CLASS(klass);
+
+    k->get_dev_path = spapr_vio_get_dev_name;
+}
+
 static const TypeInfo spapr_vio_bus_info = {
     .name = TYPE_SPAPR_VIO_BUS,
     .parent = TYPE_BUS,
+    .class_init = spapr_vio_bus_class_init,
     .instance_size = sizeof(VIOsPAPRBus),
 };
 
@@ -74,17 +94,6 @@ VIOsPAPRDevice *spapr_vio_find_by_reg(VIOsPAPRBus *bus, uint32_t reg)
     return NULL;
 }
 
-static char *vio_format_dev_name(VIOsPAPRDevice *dev)
-{
-    VIOsPAPRDeviceClass *pc = VIO_SPAPR_DEVICE_GET_CLASS(dev);
-    char *name;
-
-    /* Device tree style name device@reg */
-    name = g_strdup_printf("%s@%x", pc->dt_name, dev->reg);
-
-    return name;
-}
-
 #ifdef CONFIG_FDT
 static int vio_make_devnode(VIOsPAPRDevice *dev,
                             void *fdt)
@@ -98,7 +107,7 @@ static int vio_make_devnode(VIOsPAPRDevice *dev,
         return vdevice_off;
     }
 
-    dt_name = vio_format_dev_name(dev);
+    dt_name = spapr_vio_get_dev_name(DEVICE(dev));
     node_off = fdt_add_subnode(fdt, vdevice_off, dt_name);
     g_free(dt_name);
     if (node_off < 0) {
@@ -437,7 +446,7 @@ static int spapr_vio_busdev_init(DeviceState *qdev)
 
     /* Don't overwrite ids assigned on the command line */
     if (!dev->qdev.id) {
-        id = vio_format_dev_name(dev);
+        id = spapr_vio_get_dev_name(DEVICE(dev));
         dev->qdev.id = id;
     }
 
@@ -636,7 +645,7 @@ int spapr_populate_chosen_stdout(void *fdt, VIOsPAPRBus *bus)
         return offset;
     }
 
-    name = vio_format_dev_name(dev);
+    name = spapr_vio_get_dev_name(DEVICE(dev));
     path = g_strdup_printf("/vdevice/%s", name);
 
     ret = fdt_setprop_string(fdt, offset, "linux,stdout-path", path);
-- 
1.6.0.2

[Qemu-devel] [PATCH 19/30] powerpc: correctly handle fpu exceptions.

[Alexander Graf]

From: Tristan Gingold <gingold@adacore.com>

Raise the exception on the first occurence, do not wait for the next
floating point operation.

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/fpu_helper.c |   23 ++++++++++++-----------
 1 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 9e779ea..1e141fb 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -470,6 +470,18 @@ void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
 
 void helper_float_check_status(CPUPPCState *env)
 {
+    int status = get_float_exception_flags(&env->fp_status);
+
+    if (status & float_flag_divbyzero) {
+        float_zero_divide_excp(env);
+    } else if (status & float_flag_overflow) {
+        float_overflow_excp(env);
+    } else if (status & float_flag_underflow) {
+        float_underflow_excp(env);
+    } else if (status & float_flag_inexact) {
+        float_inexact_excp(env);
+    }
+
     if (env->exception_index == POWERPC_EXCP_PROGRAM &&
         (env->error_code & POWERPC_EXCP_FP)) {
         /* Differred floating-point exception after target FPR update */
@@ -477,17 +489,6 @@ void helper_float_check_status(CPUPPCState *env)
             helper_raise_exception_err(env, env->exception_index,
                                        env->error_code);
         }
-    } else {
-        int status = get_float_exception_flags(&env->fp_status);
-        if (status & float_flag_divbyzero) {
-            float_zero_divide_excp(env);
-        } else if (status & float_flag_overflow) {
-            float_overflow_excp(env);
-        } else if (status & float_flag_underflow) {
-            float_underflow_excp(env);
-        } else if (status & float_flag_inexact) {
-            float_inexact_excp(env);
-        }
     }
 }
 
-- 
1.6.0.2

[Qemu-devel] [PATCH 20/30] PPC: Fix dcbz for linux-user on 970

[Alexander Graf]

The default with linux-user for dcbz on 970 is to emulate 32 byte clears.
However, redoing the dcbzl support we added a check to not honor the bit
in HID5 that sets this.

Remove the #ifdef check on linux user, so that we get 32 byte clears again.

Reported-by: Riku Voipio <riku.voipio@iki.fi>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/mem_helper.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
index 9783e52..d8e63ca 100644
--- a/target-ppc/mem_helper.c
+++ b/target-ppc/mem_helper.c
@@ -140,7 +140,7 @@ void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t is_dcbzl)
 {
     int dcbz_size = env->dcache_line_size;
 
-#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+#if defined(TARGET_PPC64)
     if (!is_dcbzl &&
         (env->excp_model == POWERPC_EXCP_970) &&
         ((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) {
-- 
1.6.0.2

[Qemu-devel] [PATCH 21/30] target-ppc: optimize fabs, fnabs, fneg

[Alexander Graf]

From: Aurelien Jarno <aurelien@aurel32.net>

fabs, fnabs and fneg are just flipping the bit sign of an FP register,
this can be implemented in TCG instead of using softfloat.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/fpu_helper.c |   31 -------------------------------
 target-ppc/helper.h     |    3 ---
 target-ppc/translate.c  |   40 ++++++++++++++++++++++++++++++++++------
 3 files changed, 34 insertions(+), 40 deletions(-)

diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 1e141fb..1f0eeab 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -596,37 +596,6 @@ uint64_t helper_fdiv(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
     return farg1.ll;
 }
 
-/* fabs */
-uint64_t helper_fabs(CPUPPCState *env, uint64_t arg)
-{
-    CPU_DoubleU farg;
-
-    farg.ll = arg;
-    farg.d = float64_abs(farg.d);
-    return farg.ll;
-}
-
-/* fnabs */
-uint64_t helper_fnabs(CPUPPCState *env, uint64_t arg)
-{
-    CPU_DoubleU farg;
-
-    farg.ll = arg;
-    farg.d = float64_abs(farg.d);
-    farg.d = float64_chs(farg.d);
-    return farg.ll;
-}
-
-/* fneg */
-uint64_t helper_fneg(CPUPPCState *env, uint64_t arg)
-{
-    CPU_DoubleU farg;
-
-    farg.ll = arg;
-    farg.d = float64_chs(farg.d);
-    return farg.ll;
-}
-
 /* fctiw - fctiw. */
 uint64_t helper_fctiw(CPUPPCState *env, uint64_t arg)
 {
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index d33ee66..07397b2 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -80,9 +80,6 @@ DEF_HELPER_4(fmadd, i64, env, i64, i64, i64)
 DEF_HELPER_4(fmsub, i64, env, i64, i64, i64)
 DEF_HELPER_4(fnmadd, i64, env, i64, i64, i64)
 DEF_HELPER_4(fnmsub, i64, env, i64, i64, i64)
-DEF_HELPER_2(fabs, i64, env, i64)
-DEF_HELPER_2(fnabs, i64, env, i64)
-DEF_HELPER_2(fneg, i64, env, i64)
 DEF_HELPER_2(fsqrt, i64, env, i64)
 DEF_HELPER_2(fre, i64, env, i64)
 DEF_HELPER_2(fres, i64, env, i64)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 362ca3a..6cc7893 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2170,7 +2170,16 @@ static void gen_fcmpu(DisasContext *ctx)
 /***                         Floating-point move                           ***/
 /* fabs */
 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
-GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
+static void gen_fabs(DisasContext *ctx)
+{
+    if (unlikely(!ctx->fpu_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_FPU);
+        return;
+    }
+    tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
+                     ~(1ULL << 63));
+    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
+}
 
 /* fmr  - fmr. */
 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
@@ -2186,10 +2195,29 @@ static void gen_fmr(DisasContext *ctx)
 
 /* fnabs */
 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
-GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
+static void gen_fnabs(DisasContext *ctx)
+{
+    if (unlikely(!ctx->fpu_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_FPU);
+        return;
+    }
+    tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
+                    1ULL << 63);
+    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
+}
+
 /* fneg */
 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
-GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
+static void gen_fneg(DisasContext *ctx)
+{
+    if (unlikely(!ctx->fpu_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_FPU);
+        return;
+    }
+    tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
+                     1ULL << 63);
+    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
+}
 
 /***                  Floating-Point status & ctrl register                ***/
 
@@ -8485,7 +8513,10 @@ GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
+GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
+GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
+GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
@@ -8842,9 +8873,6 @@ GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
-GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
-GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
-GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
 
 #undef GEN_LD
 #undef GEN_LDU
-- 
1.6.0.2

[Qemu-devel] [PATCH 22/30] disas: Disassemble all ppc insns for the guest

[Alexander Graf]

From: Aurelien Jarno <aurelien@aurel32.net>

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 disas.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/disas.c b/disas.c
index 67103e0..e51127e 100644
--- a/disas.c
+++ b/disas.c
@@ -227,6 +227,7 @@ void target_disas(FILE *out, CPUArchState *env, target_ulong code,
         s.info.mach = bfd_mach_ppc;
 #endif
     }
+    s.info.disassembler_options = (char *)"any";
     print_insn = print_insn_ppc;
 #elif defined(TARGET_M68K)
     print_insn = print_insn_m68k;
-- 
1.6.0.2

[Qemu-devel] [PATCH 23/30] target-ppc: add instruction flags for Book I 2.05

[Alexander Graf]

From: Aurelien Jarno <aurelien@aurel32.net>

.. and enable it on POWER7 CPU.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/cpu.h            |    4 +++-
 target-ppc/translate_init.c |    2 +-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index b8b09b9..7cacb56 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1870,8 +1870,10 @@ enum {
     PPC2_PRCNTL        = 0x0000000000000008ULL,
     /* Byte-reversed, indexed, double-word load and store                    */
     PPC2_DBRX          = 0x0000000000000010ULL,
+    /* Book I 2.05 PowerPC specification                                     */
+    PPC2_ISA205        = 0x0000000000000020ULL,
 
-#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX)
+#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX | PPC2_ISA205)
 };
 
 /*****************************************************************************/
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index b0e3536..6feb62a 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7042,7 +7042,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
                        PPC_64B | PPC_ALTIVEC |
                        PPC_SEGMENT_64B | PPC_SLBI |
                        PPC_POPCNTB | PPC_POPCNTWD;
-    pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX;
+    pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205;
     pcc->msr_mask = 0x800000000204FF36ULL;
     pcc->mmu_model = POWERPC_MMU_2_06;
 #if defined(CONFIG_SOFTMMU)
-- 
1.6.0.2

[Qemu-devel] [PATCH 24/30] target-ppc: emulate cmpb instruction

[Alexander Graf]

From: Aurelien Jarno <aurelien@aurel32.net>

Needed for Power ISA version 2.05 compliance.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/helper.h     |    1 +
 target-ppc/int_helper.c |   15 +++++++++++++++
 target-ppc/translate.c  |    8 ++++++++
 3 files changed, 24 insertions(+), 0 deletions(-)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 07397b2..56814b5 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -36,6 +36,7 @@ DEF_HELPER_3(mulldo, i64, env, i64, i64)
 DEF_HELPER_FLAGS_1(cntlzw, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_3(sraw, tl, env, tl, tl)
 #if defined(TARGET_PPC64)
 DEF_HELPER_FLAGS_1(cntlzd, TCG_CALL_NO_RWG_SE, tl, tl)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 54eca9b..e50bdd2 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -53,6 +53,21 @@ target_ulong helper_cntlzd(target_ulong t)
 }
 #endif
 
+target_ulong helper_cmpb(target_ulong rs, target_ulong rb)
+{
+    target_ulong mask = 0xff;
+    target_ulong ra = 0;
+    int i;
+
+    for (i = 0; i < sizeof(target_ulong); i++) {
+        if ((rs & mask) == (rb & mask)) {
+            ra |= mask;
+        }
+        mask <<= 8;
+    }
+    return ra;
+}
+
 /* shift right arithmetic helper */
 target_ulong helper_sraw(CPUPPCState *env, target_ulong value,
                          target_ulong shift)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 6cc7893..4d477d2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -739,6 +739,13 @@ static void gen_isel(DisasContext *ctx)
     tcg_temp_free_i32(t0);
 }
 
+/* cmpb: PowerPC 2.05 specification */
+static void gen_cmpb(DisasContext *ctx)
+{
+    gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
+                    cpu_gpr[rB(ctx->opcode)]);
+}
+
 /***                           Integer arithmetic                          ***/
 
 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
@@ -8463,6 +8470,7 @@ GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
+GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
-- 
1.6.0.2

[Qemu-devel] [PATCH 25/30] target-ppc: emulate prtyw and prtyd instructions

[Alexander Graf]

From: Aurelien Jarno <aurelien@aurel32.net>

Needed for Power ISA version 2.05 compliance.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
[agraf: fix 32-bit host compile, simplify code]
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/translate.c |   34 ++++++++++++++++++++++++++++++++++
 1 files changed, 34 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 4d477d2..2fabbaf 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1467,6 +1467,38 @@ static void gen_popcntd(DisasContext *ctx)
 }
 #endif
 
+/* prtyw: PowerPC 2.05 specification */
+static void gen_prtyw(DisasContext *ctx)
+{
+    TCGv ra = cpu_gpr[rA(ctx->opcode)];
+    TCGv rs = cpu_gpr[rS(ctx->opcode)];
+    TCGv t0 = tcg_temp_new();
+    tcg_gen_shri_tl(t0, rs, 16);
+    tcg_gen_xor_tl(ra, rs, t0);
+    tcg_gen_shri_tl(t0, ra, 8);
+    tcg_gen_xor_tl(ra, ra, t0);
+    tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
+    tcg_temp_free(t0);
+}
+
+#if defined(TARGET_PPC64)
+/* prtyd: PowerPC 2.05 specification */
+static void gen_prtyd(DisasContext *ctx)
+{
+    TCGv ra = cpu_gpr[rA(ctx->opcode)];
+    TCGv rs = cpu_gpr[rS(ctx->opcode)];
+    TCGv t0 = tcg_temp_new();
+    tcg_gen_shri_tl(t0, rs, 32);
+    tcg_gen_xor_tl(ra, rs, t0);
+    tcg_gen_shri_tl(t0, ra, 16);
+    tcg_gen_xor_tl(ra, ra, t0);
+    tcg_gen_shri_tl(t0, ra, 8);
+    tcg_gen_xor_tl(ra, ra, t0);
+    tcg_gen_andi_tl(ra, ra, 1);
+    tcg_temp_free(t0);
+}
+#endif
+
 #if defined(TARGET_PPC64)
 /* extsw & extsw. */
 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
@@ -8498,9 +8530,11 @@ GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
+GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
 #if defined(TARGET_PPC64)
 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
+GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
 #endif
 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
-- 
1.6.0.2

[Qemu-devel] [PATCH 26/30] target-ppc: emulate fcpsgn instruction

[Alexander Graf]

From: Aurelien Jarno <aurelien@aurel32.net>

Needed for Power ISA version 2.05 compliance.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/translate.c |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 2fabbaf..1989818 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2258,6 +2258,19 @@ static void gen_fneg(DisasContext *ctx)
     gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
 }
 
+/* fcpsgn: PowerPC 2.05 specification */
+/* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
+static void gen_fcpsgn(DisasContext *ctx)
+{
+    if (unlikely(!ctx->fpu_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_FPU);
+        return;
+    }
+    tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
+                        cpu_fpr[rB(ctx->opcode)], 0, 63);
+    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
+}
+
 /***                  Floating-Point status & ctrl register                ***/
 
 /* mcrfs */
@@ -8559,6 +8572,7 @@ GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
+GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
-- 
1.6.0.2

[Qemu-devel] [PATCH 27/30] target-ppc: emulate lfiwax instruction

[Alexander Graf]

From: Aurelien Jarno <aurelien@aurel32.net>

Needed for Power ISA version 2.05 compliance.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/translate.c |   18 ++++++++++++++++--
 1 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 1989818..4f92d8f 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2531,7 +2531,6 @@ static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
     }
 }
 
-#if defined(TARGET_PPC64)
 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
 {
     if (unlikely(ctx->le_mode)) {
@@ -2541,7 +2540,6 @@ static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
     } else
         tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
 }
-#endif
 
 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
 {
@@ -3300,6 +3298,21 @@ GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
  /* lfs lfsu lfsux lfsx */
 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
 
+/* lfiwax */
+static void gen_lfiwax(DisasContext *ctx)
+{
+    TCGv EA;
+    if (unlikely(!ctx->fpu_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_FPU);
+        return;
+    }
+    gen_set_access_type(ctx, ACCESS_FLOAT);
+    EA = tcg_temp_new();
+    gen_addr_reg_index(ctx, EA);
+    gen_qemu_ld32s(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+    tcg_temp_free(EA);
+}
+
 /***                         Floating-point store                          ***/
 #define GEN_STF(name, stop, opc, type)                                        \
 static void glue(gen_, name)(DisasContext *ctx)                                       \
@@ -9014,6 +9027,7 @@ GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
 
 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
+GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
 
 #undef GEN_STF
 #undef GEN_STUF
-- 
1.6.0.2

[Qemu-devel] [PATCH 28/30] target-ppc: emulate load doubleword pair instructions

[Alexander Graf]

From: Aurelien Jarno <aurelien@aurel32.net>

Needed for Power ISA version 2.05 compliance. The check for odd register
pairs is done using the invalid bits.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/translate.c |   48 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 48 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 4f92d8f..62f9309 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3298,6 +3298,52 @@ GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
  /* lfs lfsu lfsux lfsx */
 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
 
+/* lfdp */
+static void gen_lfdp(DisasContext *ctx)
+{
+    TCGv EA;
+    if (unlikely(!ctx->fpu_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_FPU);
+        return;
+    }
+    gen_set_access_type(ctx, ACCESS_FLOAT);
+    EA = tcg_temp_new();
+    gen_addr_imm_index(ctx, EA, 0);                                           \
+    if (unlikely(ctx->le_mode)) {
+        gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+        tcg_gen_addi_tl(EA, EA, 8);
+        gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+    } else {
+        gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+        tcg_gen_addi_tl(EA, EA, 8);
+        gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+    }
+    tcg_temp_free(EA);
+}
+
+/* lfdpx */
+static void gen_lfdpx(DisasContext *ctx)
+{
+    TCGv EA;
+    if (unlikely(!ctx->fpu_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_FPU);
+        return;
+    }
+    gen_set_access_type(ctx, ACCESS_FLOAT);
+    EA = tcg_temp_new();
+    gen_addr_reg_index(ctx, EA);
+    if (unlikely(ctx->le_mode)) {
+        gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+        tcg_gen_addi_tl(EA, EA, 8);
+        gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+    } else {
+        gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+        tcg_gen_addi_tl(EA, EA, 8);
+        gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+    }
+    tcg_temp_free(EA);
+}
+
 /* lfiwax */
 static void gen_lfiwax(DisasContext *ctx)
 {
@@ -9028,6 +9074,8 @@ GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
 
 #undef GEN_STF
 #undef GEN_STUF
-- 
1.6.0.2

[Qemu-devel] [PATCH 29/30] target-ppc: emulate store doubleword pair instructions

[Alexander Graf]

From: Aurelien Jarno <aurelien@aurel32.net>

Needed for Power ISA version 2.05 compliance. The check for odd register
pairs is done using the invalid bits.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/translate.c |   48 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 48 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 62f9309..aba7e3f 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3452,6 +3452,52 @@ GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
 /* stfs stfsu stfsux stfsx */
 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
 
+/* stfdp */
+static void gen_stfdp(DisasContext *ctx)
+{
+    TCGv EA;
+    if (unlikely(!ctx->fpu_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_FPU);
+        return;
+    }
+    gen_set_access_type(ctx, ACCESS_FLOAT);
+    EA = tcg_temp_new();
+    gen_addr_imm_index(ctx, EA, 0);                                           \
+    if (unlikely(ctx->le_mode)) {
+        gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+        tcg_gen_addi_tl(EA, EA, 8);
+        gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+    } else {
+        gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+        tcg_gen_addi_tl(EA, EA, 8);
+        gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+    }
+    tcg_temp_free(EA);
+}
+
+/* stfdpx */
+static void gen_stfdpx(DisasContext *ctx)
+{
+    TCGv EA;
+    if (unlikely(!ctx->fpu_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_FPU);
+        return;
+    }
+    gen_set_access_type(ctx, ACCESS_FLOAT);
+    EA = tcg_temp_new();
+    gen_addr_reg_index(ctx, EA);
+    if (unlikely(ctx->le_mode)) {
+        gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+        tcg_gen_addi_tl(EA, EA, 8);
+        gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+    } else {
+        gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+        tcg_gen_addi_tl(EA, EA, 8);
+        gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+    }
+    tcg_temp_free(EA);
+}
+
 /* Optional: */
 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
 {
@@ -9099,6 +9145,8 @@ GEN_STXF(name, stop, 0x17, op | 0x00, type)
 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
+GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
 
 #undef GEN_CRLOGIC
 #define GEN_CRLOGIC(name, tcg_op, opc)                                        \
-- 
1.6.0.2

[Qemu-devel] [PATCH 30/30] target-ppc: add support for extended mtfsf/mtfsfi forms

[Alexander Graf]

From: Aurelien Jarno <aurelien@aurel32.net>

Power ISA 2.05 adds support for extended mtfsf/mtfsfi form, with a new
W field to select the upper part of the FPCSR register.

For that the helper is changed to handle 64-bit input values and mask with
up to 16 bits. The mtfsf/mtfsfi instructions do not have the W bit
marked as invalid anymore. Instead this is checked in the helper, which
therefore needs to access to the insns/insns_flags2. They are added in
the DisasContext struct. Finally change all accesses to the opcode fields
through extract helpers, prefixed with FP for consistency.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/fpu_helper.c |   17 +++++++----------
 target-ppc/translate.c  |   46 ++++++++++++++++++++++++++++++++++------------
 2 files changed, 41 insertions(+), 22 deletions(-)

diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 1f0eeab..4f60218 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -430,20 +430,17 @@ void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
 
 void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
 {
-    /*
-     * We use only the 32 LSB of the incoming fpr
-     */
-    uint32_t prev, new;
+    target_ulong prev, new;
     int i;
 
     prev = env->fpscr;
-    new = (uint32_t)arg;
-    new &= ~0x60000000;
-    new |= prev & 0x60000000;
-    for (i = 0; i < 8; i++) {
+    new = (target_ulong)arg;
+    new &= ~0x60000000LL;
+    new |= prev & 0x60000000LL;
+    for (i = 0; i < sizeof(target_ulong) * 2; i++) {
         if (mask & (1 << i)) {
-            env->fpscr &= ~(0xF << (4 * i));
-            env->fpscr |= new & (0xF << (4 * i));
+            env->fpscr &= ~(0xFLL << (4 * i));
+            env->fpscr |= new & (0xFLL << (4 * i));
         }
     }
     /* Update VX and FEX */
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index aba7e3f..9ecbc2e 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -202,6 +202,8 @@ typedef struct DisasContext {
     int spe_enabled;
     ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
     int singlestep_enabled;
+    uint64_t insns_flags;
+    uint64_t insns_flags2;
 } DisasContext;
 
 /* True when active word size < size of target_long.  */
@@ -423,9 +425,14 @@ EXTRACT_HELPER(ME, 1, 5);
 EXTRACT_HELPER(TO, 21, 5);
 
 EXTRACT_HELPER(CRM, 12, 8);
-EXTRACT_HELPER(FM, 17, 8);
 EXTRACT_HELPER(SR, 16, 4);
+
+/* mtfsf/mtfsfi */
+EXTRACT_HELPER(FPBF, 19, 3);
 EXTRACT_HELPER(FPIMM, 12, 4);
+EXTRACT_HELPER(FPL, 21, 1);
+EXTRACT_HELPER(FPFLM, 17, 8);
+EXTRACT_HELPER(FPW, 16, 1);
 
 /***                            Jump target decoding                       ***/
 /* Displacement */
@@ -2360,19 +2367,27 @@ static void gen_mtfsb1(DisasContext *ctx)
 static void gen_mtfsf(DisasContext *ctx)
 {
     TCGv_i32 t0;
-    int L = ctx->opcode & 0x02000000;
+    int flm, l, w;
 
     if (unlikely(!ctx->fpu_enabled)) {
         gen_exception(ctx, POWERPC_EXCP_FPU);
         return;
     }
+    flm = FPFLM(ctx->opcode);
+    l = FPL(ctx->opcode);
+    w = FPW(ctx->opcode);
+    if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
+        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
+        return;
+    }
     /* NIP cannot be restored if the memory exception comes from an helper */
     gen_update_nip(ctx, ctx->nip - 4);
     gen_reset_fpstatus();
-    if (L)
-        t0 = tcg_const_i32(0xff);
-    else
-        t0 = tcg_const_i32(FM(ctx->opcode));
+    if (l) {
+        t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
+    } else {
+        t0 = tcg_const_i32(flm << (w * 8));
+    }
     gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
     tcg_temp_free_i32(t0);
     if (unlikely(Rc(ctx->opcode) != 0)) {
@@ -2386,7 +2401,7 @@ static void gen_mtfsf(DisasContext *ctx)
 /* mtfsfi */
 static void gen_mtfsfi(DisasContext *ctx)
 {
-    int bf, sh;
+    int bf, sh, w;
     TCGv_i64 t0;
     TCGv_i32 t1;
 
@@ -2394,12 +2409,17 @@ static void gen_mtfsfi(DisasContext *ctx)
         gen_exception(ctx, POWERPC_EXCP_FPU);
         return;
     }
-    bf = crbD(ctx->opcode) >> 2;
-    sh = 7 - bf;
+    w = FPW(ctx->opcode);
+    bf = FPBF(ctx->opcode);
+    if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
+        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
+        return;
+    }
+    sh = (8 * w) + 7 - bf;
     /* NIP cannot be restored if the memory exception comes from an helper */
     gen_update_nip(ctx, ctx->nip - 4);
     gen_reset_fpstatus();
-    t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
+    t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
     t1 = tcg_const_i32(1 << sh);
     gen_helper_store_fpscr(cpu_env, t0, t1);
     tcg_temp_free_i64(t0);
@@ -8682,8 +8702,8 @@ GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
-GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
-GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
+GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
+GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
 #if defined(TARGET_PPC64)
 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
@@ -9721,6 +9741,8 @@ static inline void gen_intermediate_code_internal(CPUPPCState *env,
     ctx.exception = POWERPC_EXCP_NONE;
     ctx.spr_cb = env->spr_cb;
     ctx.mem_idx = env->mmu_idx;
+    ctx.insns_flags = env->insns_flags;
+    ctx.insns_flags2 = env->insns_flags2;
     ctx.access_type = -1;
     ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
 #if defined(TARGET_PPC64)
-- 
1.6.0.2

Re: [Qemu-devel] [PULL 00/30] ppc patch queue 2013-04-26

[Blue Swirl]

On Fri, Apr 26, 2013 at 6:21 PM, Alexander Graf <agraf@suse.de> wrote:
> Hi Blue / Aurelien,
>
> This is my current patch queue for ppc.  Please pull.

Does not build with --enable-debug:
  CC    ppc-softmmu/target-ppc/translate.o
/src/qemu/target-ppc/translate.c: In function 'gen_lfiwax':
/src/qemu/target-ppc/translate.c:3378:5: error: incompatible type for
argument 2 of 'gen_qemu_ld32s'
/src/qemu/target-ppc/translate.c:2554:20: note: expected 'TCGv_i32'
but argument is of type 'TCGv_i64'

>
> Alex
>
>
> The following changes since commit bf9b255f484fd61cbaa91faeff254140a0ecd18c:
>   Anthony Liguori (1):
>         gtk: refactor menu creation
>
> are available in the git repository at:
>
>   git://github.com/agraf/qemu.git ppc-for-upstream
>
> Alexander Graf (4):
>       linux-headers: Update to kvm/queue
>       PPC: mac newworld: fix cpu NIP reset value
>       PPC: Fix compile with profiling enabled
>       PPC: Fix dcbz for linux-user on 970
>
> Aurelien Jarno (12):
>       target-ppc: Enable ISEL on POWER7
>       target-ppc: fix nego and subf*o instructions
>       target-ppc: optimize fabs, fnabs, fneg
>       disas: Disassemble all ppc insns for the guest
>       target-ppc: add instruction flags for Book I 2.05
>       target-ppc: emulate cmpb instruction
>       target-ppc: emulate prtyw and prtyd instructions
>       target-ppc: emulate fcpsgn instruction
>       target-ppc: emulate lfiwax instruction
>       target-ppc: emulate load doubleword pair instructions
>       target-ppc: emulate store doubleword pair instructions
>       target-ppc: add support for extended mtfsf/mtfsfi forms
>
> Bharat Bhushan (1):
>       Enable kvm emulated watchdog
>
> David Gibson (7):
>       pseries: Fix incorrect calculation of RMA size in certain configurations
>       pseries: Fixes and enhancements to L1 cache properties
>       target-ppc: Add more stubs for POWER7 PMU registers
>       pseries: Fix some small errors in XICS logic
>       target-ppc: Synchronize VPA state with KVM
>       pseries: Convert VIO code to QOM style type safe(ish) casts
>       pseries: Generate device paths for VIO devices
>
> Fabien Chouteau (3):
>       PPC: Remove env->hreset_excp_prefix
>       PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450
>       PPC: Add breakpoint registers for 603 and e300
>
> Richard Henderson (1):
>       target-ppc: Fix narrow-mode add/sub carry output
>
> Stuart Yoder (1):
>       PPC: e500: advertise 4.2 MPIC only if KVM supports EPR
>
> Tristan Gingold (1):
>       powerpc: correctly handle fpu exceptions.
>
>  disas.c                         |    1 +
>  hw/char/spapr_vty.c             |   18 ++-
>  hw/net/spapr_llan.c             |   24 ++--
>  hw/nvram/spapr_nvram.c          |   10 +-
>  hw/ppc/e500plat.c               |    7 +
>  hw/ppc/mac_newworld.c           |    2 +
>  hw/ppc/ppc_booke.c              |   45 ++++++-
>  hw/ppc/spapr.c                  |   27 +++-
>  hw/ppc/spapr_vio.c              |   41 ++++--
>  hw/ppc/xics.c                   |    2 +
>  hw/scsi/spapr_vscsi.c           |   15 ++-
>  linux-headers/asm-powerpc/kvm.h |    5 +
>  linux-headers/linux/kvm.h       |    3 +
>  target-ppc/cpu-qom.h            |    1 +
>  target-ppc/cpu.h                |    6 +-
>  target-ppc/fpu_helper.c         |   71 +++-------
>  target-ppc/helper.h             |    4 +-
>  target-ppc/int_helper.c         |   15 ++
>  target-ppc/kvm.c                |  237 +++++++++++++++++++++++++++++++-
>  target-ppc/kvm_ppc.h            |   30 ++++
>  target-ppc/machine.c            |    2 -
>  target-ppc/mem_helper.c         |    2 +-
>  target-ppc/translate.c          |  293 ++++++++++++++++++++++++++++++++++-----
>  target-ppc/translate_init.c     |  117 ++++++++++------
>  translate-all.c                 |    1 +
>  25 files changed, 791 insertions(+), 188 deletions(-)

Re: [Qemu-devel] [PULL 00/30] ppc patch queue 2013-04-26

[Alexander Graf]

Am 26.04.2013 um 22:09 schrieb Blue Swirl <blauwirbel@gmail.com>:

> On Fri, Apr 26, 2013 at 6:21 PM, Alexander Graf <agraf@suse.de> wrote:
>> Hi Blue / Aurelien,
>> 
>> This is my current patch queue for ppc.  Please pull.
> 
> Does not build with --enable-debug:
>  CC    ppc-softmmu/target-ppc/translate.o
> /src/qemu/target-ppc/translate.c: In function 'gen_lfiwax':
> /src/qemu/target-ppc/translate.c:3378:5: error: incompatible type for
> argument 2 of 'gen_qemu_ld32s'
> /src/qemu/target-ppc/translate.c:2554:20: note: expected 'TCGv_i32'
> but argument is of type 'TCGv_i64'

I pushed an updated, fixed tree.

Alex

> 
>> 
>> Alex
>> 
>> 
>> The following changes since commit bf9b255f484fd61cbaa91faeff254140a0ecd18c:
>>  Anthony Liguori (1):
>>        gtk: refactor menu creation
>> 
>> are available in the git repository at:
>> 
>>  git://github.com/agraf/qemu.git ppc-for-upstream
>> 
>> Alexander Graf (4):
>>      linux-headers: Update to kvm/queue
>>      PPC: mac newworld: fix cpu NIP reset value
>>      PPC: Fix compile with profiling enabled
>>      PPC: Fix dcbz for linux-user on 970
>> 
>> Aurelien Jarno (12):
>>      target-ppc: Enable ISEL on POWER7
>>      target-ppc: fix nego and subf*o instructions
>>      target-ppc: optimize fabs, fnabs, fneg
>>      disas: Disassemble all ppc insns for the guest
>>      target-ppc: add instruction flags for Book I 2.05
>>      target-ppc: emulate cmpb instruction
>>      target-ppc: emulate prtyw and prtyd instructions
>>      target-ppc: emulate fcpsgn instruction
>>      target-ppc: emulate lfiwax instruction
>>      target-ppc: emulate load doubleword pair instructions
>>      target-ppc: emulate store doubleword pair instructions
>>      target-ppc: add support for extended mtfsf/mtfsfi forms
>> 
>> Bharat Bhushan (1):
>>      Enable kvm emulated watchdog
>> 
>> David Gibson (7):
>>      pseries: Fix incorrect calculation of RMA size in certain configurations
>>      pseries: Fixes and enhancements to L1 cache properties
>>      target-ppc: Add more stubs for POWER7 PMU registers
>>      pseries: Fix some small errors in XICS logic
>>      target-ppc: Synchronize VPA state with KVM
>>      pseries: Convert VIO code to QOM style type safe(ish) casts
>>      pseries: Generate device paths for VIO devices
>> 
>> Fabien Chouteau (3):
>>      PPC: Remove env->hreset_excp_prefix
>>      PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450
>>      PPC: Add breakpoint registers for 603 and e300
>> 
>> Richard Henderson (1):
>>      target-ppc: Fix narrow-mode add/sub carry output
>> 
>> Stuart Yoder (1):
>>      PPC: e500: advertise 4.2 MPIC only if KVM supports EPR
>> 
>> Tristan Gingold (1):
>>      powerpc: correctly handle fpu exceptions.
>> 
>> disas.c                         |    1 +
>> hw/char/spapr_vty.c             |   18 ++-
>> hw/net/spapr_llan.c             |   24 ++--
>> hw/nvram/spapr_nvram.c          |   10 +-
>> hw/ppc/e500plat.c               |    7 +
>> hw/ppc/mac_newworld.c           |    2 +
>> hw/ppc/ppc_booke.c              |   45 ++++++-
>> hw/ppc/spapr.c                  |   27 +++-
>> hw/ppc/spapr_vio.c              |   41 ++++--
>> hw/ppc/xics.c                   |    2 +
>> hw/scsi/spapr_vscsi.c           |   15 ++-
>> linux-headers/asm-powerpc/kvm.h |    5 +
>> linux-headers/linux/kvm.h       |    3 +
>> target-ppc/cpu-qom.h            |    1 +
>> target-ppc/cpu.h                |    6 +-
>> target-ppc/fpu_helper.c         |   71 +++-------
>> target-ppc/helper.h             |    4 +-
>> target-ppc/int_helper.c         |   15 ++
>> target-ppc/kvm.c                |  237 +++++++++++++++++++++++++++++++-
>> target-ppc/kvm_ppc.h            |   30 ++++
>> target-ppc/machine.c            |    2 -
>> target-ppc/mem_helper.c         |    2 +-
>> target-ppc/translate.c          |  293 ++++++++++++++++++++++++++++++++++-----
>> target-ppc/translate_init.c     |  117 ++++++++++------
>> translate-all.c                 |    1 +
>> 25 files changed, 791 insertions(+), 188 deletions(-)

Re: [Qemu-devel] [PULL 00/30] ppc patch queue 2013-04-26

[Aurelien Jarno]

On Fri, Apr 26, 2013 at 11:03:12PM +0200, Alexander Graf wrote:
> 
> 
> Am 26.04.2013 um 22:09 schrieb Blue Swirl <blauwirbel@gmail.com>:
> 
> > On Fri, Apr 26, 2013 at 6:21 PM, Alexander Graf <agraf@suse.de> wrote:
> >> Hi Blue / Aurelien,
> >> 
> >> This is my current patch queue for ppc.  Please pull.
> > 
> > Does not build with --enable-debug:
> >  CC    ppc-softmmu/target-ppc/translate.o
> > /src/qemu/target-ppc/translate.c: In function 'gen_lfiwax':
> > /src/qemu/target-ppc/translate.c:3378:5: error: incompatible type for
> > argument 2 of 'gen_qemu_ld32s'
> > /src/qemu/target-ppc/translate.c:2554:20: note: expected 'TCGv_i32'
> > but argument is of type 'TCGv_i64'
> 
> I pushed an updated, fixed tree.
> 

Thanks, and sorry about that. Would it be possible to use the following
patch instead? It generates slightly better code (by folding the sign
extension in the load when possible).



target-ppc: emulate lfiwax instruction

Needed for Power ISA version 2.05 compliance.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-ppc/translate.c |   22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 1989818..b883a57 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2531,7 +2531,6 @@ static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
     }
 }
 
-#if defined(TARGET_PPC64)
 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
 {
     if (unlikely(ctx->le_mode)) {
@@ -2541,7 +2540,6 @@ static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
     } else
         tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
 }
-#endif
 
 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
 {
@@ -3300,6 +3298,25 @@ GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
  /* lfs lfsu lfsux lfsx */
 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
 
+/* lfiwax */
+static void gen_lfiwax(DisasContext *ctx)
+{
+    TCGv EA;
+    TCGv t0;
+    if (unlikely(!ctx->fpu_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_FPU);
+        return;
+    }
+    gen_set_access_type(ctx, ACCESS_FLOAT);
+    EA = tcg_temp_new();
+    t0 = tcg_temp_new();
+    gen_addr_reg_index(ctx, EA);
+    gen_qemu_ld32s(ctx, t0, EA);
+    tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
+    tcg_temp_free(EA);
+    tcg_temp_free(t0);
+}
+
 /***                         Floating-point store                          ***/
 #define GEN_STF(name, stop, opc, type)                                        \
 static void glue(gen_, name)(DisasContext *ctx)                                       \
@@ -9014,6 +9031,7 @@ GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
 
 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
+GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
 
 #undef GEN_STF
 #undef GEN_STUF
-- 
1.7.10.4


-- 
Aurelien Jarno	                        GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PULL 00/30] ppc patch queue 2013-04-26

[Alexander Graf]

Am 26.04.2013 um 23:17 schrieb Aurelien Jarno <aurelien@aurel32.net>:

> On Fri, Apr 26, 2013 at 11:03:12PM +0200, Alexander Graf wrote:
>> 
>> 
>> Am 26.04.2013 um 22:09 schrieb Blue Swirl <blauwirbel@gmail.com>:
>> 
>>> On Fri, Apr 26, 2013 at 6:21 PM, Alexander Graf <agraf@suse.de> wrote:
>>>> Hi Blue / Aurelien,
>>>> 
>>>> This is my current patch queue for ppc.  Please pull.
>>> 
>>> Does not build with --enable-debug:
>>> CC    ppc-softmmu/target-ppc/translate.o
>>> /src/qemu/target-ppc/translate.c: In function 'gen_lfiwax':
>>> /src/qemu/target-ppc/translate.c:3378:5: error: incompatible type for
>>> argument 2 of 'gen_qemu_ld32s'
>>> /src/qemu/target-ppc/translate.c:2554:20: note: expected 'TCGv_i32'
>>> but argument is of type 'TCGv_i64'
>> 
>> I pushed an updated, fixed tree.
> 
> Thanks, and sorry about that. Would it be possible to use the following
> patch instead? It generates slightly better code (by folding the sign
> extension in the load when possible).

How about you just apply the pull request, diff your version against what's in there and apply the diff on top :).

I'm quite sure that makes everyone's life easier ;).


Alex

> 
> 
> 
> target-ppc: emulate lfiwax instruction
> 
> Needed for Power ISA version 2.05 compliance.
> 
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
> ---
> target-ppc/translate.c |   22 ++++++++++++++++++++--
> 1 file changed, 20 insertions(+), 2 deletions(-)
> 
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 1989818..b883a57 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -2531,7 +2531,6 @@ static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
>     }
> }
> 
> -#if defined(TARGET_PPC64)
> static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
> {
>     if (unlikely(ctx->le_mode)) {
> @@ -2541,7 +2540,6 @@ static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
>     } else
>         tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
> }
> -#endif
> 
> static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
> {
> @@ -3300,6 +3298,25 @@ GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
>  /* lfs lfsu lfsux lfsx */
> GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
> 
> +/* lfiwax */
> +static void gen_lfiwax(DisasContext *ctx)
> +{
> +    TCGv EA;
> +    TCGv t0;
> +    if (unlikely(!ctx->fpu_enabled)) {
> +        gen_exception(ctx, POWERPC_EXCP_FPU);
> +        return;
> +    }
> +    gen_set_access_type(ctx, ACCESS_FLOAT);
> +    EA = tcg_temp_new();
> +    t0 = tcg_temp_new();
> +    gen_addr_reg_index(ctx, EA);
> +    gen_qemu_ld32s(ctx, t0, EA);
> +    tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
> +    tcg_temp_free(EA);
> +    tcg_temp_free(t0);
> +}
> +
> /***                         Floating-point store                          ***/
> #define GEN_STF(name, stop, opc, type)                                        \
> static void glue(gen_, name)(DisasContext *ctx)                                       \
> @@ -9014,6 +9031,7 @@ GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
> 
> GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
> GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
> +GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
> 
> #undef GEN_STF
> #undef GEN_STUF
> -- 
> 1.7.10.4
> 
> 
> -- 
> Aurelien Jarno                            GPG: 1024D/F1BCDB73
> aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PULL 00/30] ppc patch queue 2013-04-26

[Aurelien Jarno]

On Fri, Apr 26, 2013 at 11:42:19PM +0200, Alexander Graf wrote:
> 
> 
> Am 26.04.2013 um 23:17 schrieb Aurelien Jarno <aurelien@aurel32.net>:
> 
> > On Fri, Apr 26, 2013 at 11:03:12PM +0200, Alexander Graf wrote:
> >> 
> >> 
> >> Am 26.04.2013 um 22:09 schrieb Blue Swirl <blauwirbel@gmail.com>:
> >> 
> >>> On Fri, Apr 26, 2013 at 6:21 PM, Alexander Graf <agraf@suse.de> wrote:
> >>>> Hi Blue / Aurelien,
> >>>> 
> >>>> This is my current patch queue for ppc.  Please pull.
> >>> 
> >>> Does not build with --enable-debug:
> >>> CC    ppc-softmmu/target-ppc/translate.o
> >>> /src/qemu/target-ppc/translate.c: In function 'gen_lfiwax':
> >>> /src/qemu/target-ppc/translate.c:3378:5: error: incompatible type for
> >>> argument 2 of 'gen_qemu_ld32s'
> >>> /src/qemu/target-ppc/translate.c:2554:20: note: expected 'TCGv_i32'
> >>> but argument is of type 'TCGv_i64'
> >> 
> >> I pushed an updated, fixed tree.
> > 
> > Thanks, and sorry about that. Would it be possible to use the following
> > patch instead? It generates slightly better code (by folding the sign
> > extension in the load when possible).
> 
> How about you just apply the pull request, diff your version against what's in there and apply the diff on top :).

This considered as an abuse of my commit powers and usually leads to
complains.

> I'm quite sure that makes everyone's life easier ;).

Done anyway, I hope you won't complain ;)


Aurelien

-- 
Aurelien Jarno	                        GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PULL 00/30] ppc patch queue 2013-04-26

[Blue Swirl]

On Fri, Apr 26, 2013 at 6:21 PM, Alexander Graf <agraf@suse.de> wrote:
> Hi Blue / Aurelien,
>
> This is my current patch queue for ppc.  Please pull.

Thanks, pulled.

>
> Alex
>
>
> The following changes since commit bf9b255f484fd61cbaa91faeff254140a0ecd18c:
>   Anthony Liguori (1):
>         gtk: refactor menu creation
>
> are available in the git repository at:
>
>   git://github.com/agraf/qemu.git ppc-for-upstream
>
> Alexander Graf (4):
>       linux-headers: Update to kvm/queue
>       PPC: mac newworld: fix cpu NIP reset value
>       PPC: Fix compile with profiling enabled
>       PPC: Fix dcbz for linux-user on 970
>
> Aurelien Jarno (12):
>       target-ppc: Enable ISEL on POWER7
>       target-ppc: fix nego and subf*o instructions
>       target-ppc: optimize fabs, fnabs, fneg
>       disas: Disassemble all ppc insns for the guest
>       target-ppc: add instruction flags for Book I 2.05
>       target-ppc: emulate cmpb instruction
>       target-ppc: emulate prtyw and prtyd instructions
>       target-ppc: emulate fcpsgn instruction
>       target-ppc: emulate lfiwax instruction
>       target-ppc: emulate load doubleword pair instructions
>       target-ppc: emulate store doubleword pair instructions
>       target-ppc: add support for extended mtfsf/mtfsfi forms
>
> Bharat Bhushan (1):
>       Enable kvm emulated watchdog
>
> David Gibson (7):
>       pseries: Fix incorrect calculation of RMA size in certain configurations
>       pseries: Fixes and enhancements to L1 cache properties
>       target-ppc: Add more stubs for POWER7 PMU registers
>       pseries: Fix some small errors in XICS logic
>       target-ppc: Synchronize VPA state with KVM
>       pseries: Convert VIO code to QOM style type safe(ish) casts
>       pseries: Generate device paths for VIO devices
>
> Fabien Chouteau (3):
>       PPC: Remove env->hreset_excp_prefix
>       PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450
>       PPC: Add breakpoint registers for 603 and e300
>
> Richard Henderson (1):
>       target-ppc: Fix narrow-mode add/sub carry output
>
> Stuart Yoder (1):
>       PPC: e500: advertise 4.2 MPIC only if KVM supports EPR
>
> Tristan Gingold (1):
>       powerpc: correctly handle fpu exceptions.
>
>  disas.c                         |    1 +
>  hw/char/spapr_vty.c             |   18 ++-
>  hw/net/spapr_llan.c             |   24 ++--
>  hw/nvram/spapr_nvram.c          |   10 +-
>  hw/ppc/e500plat.c               |    7 +
>  hw/ppc/mac_newworld.c           |    2 +
>  hw/ppc/ppc_booke.c              |   45 ++++++-
>  hw/ppc/spapr.c                  |   27 +++-
>  hw/ppc/spapr_vio.c              |   41 ++++--
>  hw/ppc/xics.c                   |    2 +
>  hw/scsi/spapr_vscsi.c           |   15 ++-
>  linux-headers/asm-powerpc/kvm.h |    5 +
>  linux-headers/linux/kvm.h       |    3 +
>  target-ppc/cpu-qom.h            |    1 +
>  target-ppc/cpu.h                |    6 +-
>  target-ppc/fpu_helper.c         |   71 +++-------
>  target-ppc/helper.h             |    4 +-
>  target-ppc/int_helper.c         |   15 ++
>  target-ppc/kvm.c                |  237 +++++++++++++++++++++++++++++++-
>  target-ppc/kvm_ppc.h            |   30 ++++
>  target-ppc/machine.c            |    2 -
>  target-ppc/mem_helper.c         |    2 +-
>  target-ppc/translate.c          |  293 ++++++++++++++++++++++++++++++++++-----
>  target-ppc/translate_init.c     |  117 ++++++++++------
>  translate-all.c                 |    1 +
>  25 files changed, 791 insertions(+), 188 deletions(-)

Re: [Qemu-devel] [PULL 00/30] ppc patch queue 2013-04-26

[Blue Swirl]

On Fri, Apr 26, 2013 at 8:12 PM, Blue Swirl <blauwirbel@gmail.com> wrote:
> On Fri, Apr 26, 2013 at 6:21 PM, Alexander Graf <agraf@suse.de> wrote:
>> Hi Blue / Aurelien,
>>
>> This is my current patch queue for ppc.  Please pull.
>
> Thanks, pulled.

Sorry, replied to wrong pull request.

>
>>
>> Alex
>>
>>
>> The following changes since commit bf9b255f484fd61cbaa91faeff254140a0ecd18c:
>>   Anthony Liguori (1):
>>         gtk: refactor menu creation
>>
>> are available in the git repository at:
>>
>>   git://github.com/agraf/qemu.git ppc-for-upstream
>>
>> Alexander Graf (4):
>>       linux-headers: Update to kvm/queue
>>       PPC: mac newworld: fix cpu NIP reset value
>>       PPC: Fix compile with profiling enabled
>>       PPC: Fix dcbz for linux-user on 970
>>
>> Aurelien Jarno (12):
>>       target-ppc: Enable ISEL on POWER7
>>       target-ppc: fix nego and subf*o instructions
>>       target-ppc: optimize fabs, fnabs, fneg
>>       disas: Disassemble all ppc insns for the guest
>>       target-ppc: add instruction flags for Book I 2.05
>>       target-ppc: emulate cmpb instruction
>>       target-ppc: emulate prtyw and prtyd instructions
>>       target-ppc: emulate fcpsgn instruction
>>       target-ppc: emulate lfiwax instruction
>>       target-ppc: emulate load doubleword pair instructions
>>       target-ppc: emulate store doubleword pair instructions
>>       target-ppc: add support for extended mtfsf/mtfsfi forms
>>
>> Bharat Bhushan (1):
>>       Enable kvm emulated watchdog
>>
>> David Gibson (7):
>>       pseries: Fix incorrect calculation of RMA size in certain configurations
>>       pseries: Fixes and enhancements to L1 cache properties
>>       target-ppc: Add more stubs for POWER7 PMU registers
>>       pseries: Fix some small errors in XICS logic
>>       target-ppc: Synchronize VPA state with KVM
>>       pseries: Convert VIO code to QOM style type safe(ish) casts
>>       pseries: Generate device paths for VIO devices
>>
>> Fabien Chouteau (3):
>>       PPC: Remove env->hreset_excp_prefix
>>       PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450
>>       PPC: Add breakpoint registers for 603 and e300
>>
>> Richard Henderson (1):
>>       target-ppc: Fix narrow-mode add/sub carry output
>>
>> Stuart Yoder (1):
>>       PPC: e500: advertise 4.2 MPIC only if KVM supports EPR
>>
>> Tristan Gingold (1):
>>       powerpc: correctly handle fpu exceptions.
>>
>>  disas.c                         |    1 +
>>  hw/char/spapr_vty.c             |   18 ++-
>>  hw/net/spapr_llan.c             |   24 ++--
>>  hw/nvram/spapr_nvram.c          |   10 +-
>>  hw/ppc/e500plat.c               |    7 +
>>  hw/ppc/mac_newworld.c           |    2 +
>>  hw/ppc/ppc_booke.c              |   45 ++++++-
>>  hw/ppc/spapr.c                  |   27 +++-
>>  hw/ppc/spapr_vio.c              |   41 ++++--
>>  hw/ppc/xics.c                   |    2 +
>>  hw/scsi/spapr_vscsi.c           |   15 ++-
>>  linux-headers/asm-powerpc/kvm.h |    5 +
>>  linux-headers/linux/kvm.h       |    3 +
>>  target-ppc/cpu-qom.h            |    1 +
>>  target-ppc/cpu.h                |    6 +-
>>  target-ppc/fpu_helper.c         |   71 +++-------
>>  target-ppc/helper.h             |    4 +-
>>  target-ppc/int_helper.c         |   15 ++
>>  target-ppc/kvm.c                |  237 +++++++++++++++++++++++++++++++-
>>  target-ppc/kvm_ppc.h            |   30 ++++
>>  target-ppc/machine.c            |    2 -
>>  target-ppc/mem_helper.c         |    2 +-
>>  target-ppc/translate.c          |  293 ++++++++++++++++++++++++++++++++++-----
>>  target-ppc/translate_init.c     |  117 ++++++++++------
>>  translate-all.c                 |    1 +
>>  25 files changed, 791 insertions(+), 188 deletions(-)

Re: [Qemu-devel] [PATCH 05/30] PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450

[Artyom Tarasenko]

Hi Andreas,

On Mon, Apr 29, 2013 at 3:05 PM, Aurelien Jarno <aurelien@aurel32.net> wrote:
> On Mon, Apr 29, 2013 at 01:37:30PM +0200, Andreas Färber wrote:
>> Am 29.04.2013 12:38, schrieb Fabien Chouteau:
>> > On 04/28/2013 03:59 PM, Andreas Färber wrote:
>> >> Am 26.04.2013 20:21, schrieb Alexander Graf:
>> >>> From: Fabien Chouteau <chouteau@adacore.com>
>> >>>
>> >>> According to the different user's manuals, the vector offset for system
>> >>> reset (both /HRESET and /SRESET) is 0x00100.
>> >>>
>> >>> This patch may break support of some executables, as the power-on start
>> >>> address may change. For a specific board, if the power-on start address
>> >>> is different than HRESET vector (i.e. 0x00000100 or 0xfff00100), this
>> >>> should be fixed in board's initialization code.
>> >>>
>> >>> Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
>> >>> Signed-off-by: Alexander Graf <agraf@suse.de>
>> >>
>> >> According to git-bisect, this commit broke the prep machine (602).
>> >> Symptoms are a black screen with no VGA output from OHW or kernel.
>> >>
>> >> Please suggest a fix.
>> >>
>> >
>> > Can you hand me the binaries so I can try to fix this?
>>
>> The old ppc_rom.bin is still in qemu.git, so this should suffice:
>>
>> ./ppc-softmmu/qemu-system-ppc -M prep
>>
>> Problem is, we can't really recompile that binary with changes - and to
>> switch to OpenBIOS after 1.5 to get rid of it, I need to test that my
>> incremental patches don't break anything. ;)
>
> You can't really recompile this exact version, but you can recompile a
> slightly older version, the one which is in the Debian archive:
>
> http://packages.debian.org/source/unstable/openhackware
>
> I don't know what are the difference between this one and the one in
> QEMU though.

Fwiw last year I built ppc_rom.bin from this git tree:

git://github.com/tycho/openhackware.git

Saw no differences between this one and the binary one while booting Linux.

Artyom

--
Regards,
Artyom Tarasenko

linux/sparc and solaris/sparc under qemu blog:
http://tyom.blogspot.com/search/label/qemu