[PATCH 0/3] Use dedicated RI/XI exceptions for MIPSR5 cores

[PATCH 0/3] Use dedicated RI/XI exceptions for MIPSR5 cores

[Markos Chandras]

Hi,

This patchset adds support for unique RI/XI exceptions. This feature has
been added in MIPSr5. Using this feature, we reduce the time it takes
to deal with a TLB exception caused by the RI/XI bits since the TLB load
handler is skipped and we use the tlb_do_page_failt_0 path directly.

This patch depends on the Hardware Page Table Walker (HTW) patchset
http://www.linux-mips.org/archives/linux-mips/2014-07/msg00195.html

Leonid Yegoshin (3):
  MIPS: Add new option for unique RI/XI exceptions
  MIPS: Use dedicated exception handler if CPU supports RI/XI exceptions
  MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions

 arch/mips/include/asm/cpu-features.h | 3 +++
 arch/mips/include/asm/cpu.h          | 1 +
 arch/mips/include/asm/mipsregs.h     | 1 +
 arch/mips/kernel/cpu-probe.c         | 9 +++++++++
 arch/mips/kernel/traps.c             | 7 +++++++
 arch/mips/mm/tlbex.c                 | 4 ++--
 6 files changed, 23 insertions(+), 2 deletions(-)

-- 
2.0.0

[PATCH 0/3] Use dedicated RI/XI exceptions for MIPSR5 cores

[Markos Chandras]

Hi,

This patchset adds support for unique RI/XI exceptions. This feature has
been added in MIPSr5. Using this feature, we reduce the time it takes
to deal with a TLB exception caused by the RI/XI bits since the TLB load
handler is skipped and we use the tlb_do_page_failt_0 path directly.

This patch depends on the Hardware Page Table Walker (HTW) patchset
http://www.linux-mips.org/archives/linux-mips/2014-07/msg00195.html

Leonid Yegoshin (3):
  MIPS: Add new option for unique RI/XI exceptions
  MIPS: Use dedicated exception handler if CPU supports RI/XI exceptions
  MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions

 arch/mips/include/asm/cpu-features.h | 3 +++
 arch/mips/include/asm/cpu.h          | 1 +
 arch/mips/include/asm/mipsregs.h     | 1 +
 arch/mips/kernel/cpu-probe.c         | 9 +++++++++
 arch/mips/kernel/traps.c             | 7 +++++++
 arch/mips/mm/tlbex.c                 | 4 ++--
 6 files changed, 23 insertions(+), 2 deletions(-)

-- 
2.0.0

[PATCH 1/3] MIPS: Add new option for unique RI/XI exceptions

[Markos Chandras]

From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>

MIPSr5 added support for unique exception codes for the Read-Inhibit
and Execute-Inhibit exceptions.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
 arch/mips/include/asm/cpu-features.h | 3 +++
 arch/mips/include/asm/cpu.h          | 1 +
 2 files changed, 4 insertions(+)

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 3b9768e92e9e..eeb5400ed4ee 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -32,6 +32,9 @@
 #ifndef cpu_has_htw
 #define cpu_has_htw		(cpu_data[0].options & MIPS_CPU_HTW)
 #endif
+#ifndef cpu_has_rixiex
+#define cpu_has_rixiex		(cpu_data[0].options & MIPS_CPU_RIXIEX)
+#endif
 
 /*
  * For the moment we don't consider R6000 and R8000 so we can assume that
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 8219c0a5f77e..be13f2879c84 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -364,6 +364,7 @@ enum cpu_type_enum {
 #define MIPS_CPU_SEGMENTS	0x04000000ull /* CPU supports Segmentation Control registers */
 #define MIPS_CPU_EVA		0x80000000ull /* CPU supports Enhanced Virtual Addressing */
 #define MIPS_CPU_HTW		0x100000000ull /* CPU support Hardware Page Table Walker */
+#define MIPS_CPU_RIXIEX		0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
 
 /*
  * CPU ASE encodings
-- 
2.0.0

[PATCH 1/3] MIPS: Add new option for unique RI/XI exceptions

[Markos Chandras]

From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>

MIPSr5 added support for unique exception codes for the Read-Inhibit
and Execute-Inhibit exceptions.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
 arch/mips/include/asm/cpu-features.h | 3 +++
 arch/mips/include/asm/cpu.h          | 1 +
 2 files changed, 4 insertions(+)

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 3b9768e92e9e..eeb5400ed4ee 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -32,6 +32,9 @@
 #ifndef cpu_has_htw
 #define cpu_has_htw		(cpu_data[0].options & MIPS_CPU_HTW)
 #endif
+#ifndef cpu_has_rixiex
+#define cpu_has_rixiex		(cpu_data[0].options & MIPS_CPU_RIXIEX)
+#endif
 
 /*
  * For the moment we don't consider R6000 and R8000 so we can assume that
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 8219c0a5f77e..be13f2879c84 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -364,6 +364,7 @@ enum cpu_type_enum {
 #define MIPS_CPU_SEGMENTS	0x04000000ull /* CPU supports Segmentation Control registers */
 #define MIPS_CPU_EVA		0x80000000ull /* CPU supports Enhanced Virtual Addressing */
 #define MIPS_CPU_HTW		0x100000000ull /* CPU support Hardware Page Table Walker */
+#define MIPS_CPU_RIXIEX		0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
 
 /*
  * CPU ASE encodings
-- 
2.0.0

Re: [PATCH 1/3] MIPS: Add new option for unique RI/XI exceptions

[Sergei Shtylyov]

Hello.

On 07/15/2014 05:09 PM, Markos Chandras wrote:

> From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>

> MIPSr5 added support for unique exception codes for the Read-Inhibit
> and Execute-Inhibit exceptions.

> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
[...]

> diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
> index 8219c0a5f77e..be13f2879c84 100644
> --- a/arch/mips/include/asm/cpu.h
> +++ b/arch/mips/include/asm/cpu.h
> @@ -364,6 +364,7 @@ enum cpu_type_enum {
>   #define MIPS_CPU_SEGMENTS	0x04000000ull /* CPU supports Segmentation Control registers */
>   #define MIPS_CPU_EVA		0x80000000ull /* CPU supports Enhanced Virtual Addressing */
>   #define MIPS_CPU_HTW		0x100000000ull /* CPU support Hardware Page Table Walker */
> +#define MIPS_CPU_RIXIEX		0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */

    I think this conflicts with the MAAR patchset.

WBR, Sergei

Re: [PATCH 1/3] MIPS: Add new option for unique RI/XI exceptions

[Markos Chandras]

Hi Sergei,

On 07/15/2014 05:09 PM, Sergei Shtylyov wrote:
> Hello.
> 
> On 07/15/2014 05:09 PM, Markos Chandras wrote:
> 
>> From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
> 
>> MIPSr5 added support for unique exception codes for the Read-Inhibit
>> and Execute-Inhibit exceptions.
> 
>> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
>> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
> [...]
> 
>> diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
>> index 8219c0a5f77e..be13f2879c84 100644
>> --- a/arch/mips/include/asm/cpu.h
>> +++ b/arch/mips/include/asm/cpu.h
>> @@ -364,6 +364,7 @@ enum cpu_type_enum {
>>   #define MIPS_CPU_SEGMENTS    0x04000000ull /* CPU supports
>> Segmentation Control registers */
>>   #define MIPS_CPU_EVA        0x80000000ull /* CPU supports Enhanced
>> Virtual Addressing */
>>   #define MIPS_CPU_HTW        0x100000000ull /* CPU support Hardware
>> Page Table Walker */
>> +#define MIPS_CPU_RIXIEX        0x200000000ull /* CPU has unique
>> exception codes for {Read, Execute}-Inhibit exceptions */
> 
>    I think this conflicts with the MAAR patchset.
> 
> WBR, Sergei
> 

Well yes, but it's easy to resolve these conflicts.

-- 
markos

Re: [PATCH 1/3] MIPS: Add new option for unique RI/XI exceptions

[Markos Chandras]

Hi Sergei,

On 07/15/2014 05:09 PM, Sergei Shtylyov wrote:
> Hello.
> 
> On 07/15/2014 05:09 PM, Markos Chandras wrote:
> 
>> From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
> 
>> MIPSr5 added support for unique exception codes for the Read-Inhibit
>> and Execute-Inhibit exceptions.
> 
>> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
>> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
> [...]
> 
>> diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
>> index 8219c0a5f77e..be13f2879c84 100644
>> --- a/arch/mips/include/asm/cpu.h
>> +++ b/arch/mips/include/asm/cpu.h
>> @@ -364,6 +364,7 @@ enum cpu_type_enum {
>>   #define MIPS_CPU_SEGMENTS    0x04000000ull /* CPU supports
>> Segmentation Control registers */
>>   #define MIPS_CPU_EVA        0x80000000ull /* CPU supports Enhanced
>> Virtual Addressing */
>>   #define MIPS_CPU_HTW        0x100000000ull /* CPU support Hardware
>> Page Table Walker */
>> +#define MIPS_CPU_RIXIEX        0x200000000ull /* CPU has unique
>> exception codes for {Read, Execute}-Inhibit exceptions */
> 
>    I think this conflicts with the MAAR patchset.
> 
> WBR, Sergei
> 

Well yes, but it's easy to resolve these conflicts.

-- 
markos

[PATCH 2/3] MIPS: Use dedicated exception handler if CPU supports RI/XI exceptions

[Markos Chandras]

From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>

Use the regular tlb_do_page_fault_0 (no write) handler to handle
the RI and XI exceptions. Also skip the RI/XI validation check
on TLB load handler since it's redundant when the CPU has
unique RI/XI exceptions.

Singed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
 arch/mips/kernel/traps.c | 7 +++++++
 arch/mips/mm/tlbex.c     | 4 ++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 51706d6dd5b0..1a328b1e288b 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -90,6 +90,7 @@ extern asmlinkage void handle_mt(void);
 extern asmlinkage void handle_dsp(void);
 extern asmlinkage void handle_mcheck(void);
 extern asmlinkage void handle_reserved(void);
+extern void tlb_do_page_fault_0(void);
 
 void (*board_be_init)(void);
 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
@@ -2114,6 +2115,12 @@ void __init trap_init(void)
 		set_except_vector(15, handle_fpe);
 
 	set_except_vector(16, handle_ftlb);
+
+	if (cpu_has_rixiex) {
+		set_except_vector(19, tlb_do_page_fault_0);
+		set_except_vector(20, tlb_do_page_fault_0);
+	}
+
 	set_except_vector(21, handle_msa);
 	set_except_vector(22, handle_mdmx);
 
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 0d9d0f06dbb2..ccf8298e7ab2 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -1919,7 +1919,7 @@ static void build_r4000_tlb_load_handler(void)
 	if (m4kc_tlbp_war())
 		build_tlb_probe_entry(&p);
 
-	if (cpu_has_rixi) {
+	if (cpu_has_rixi && !cpu_has_rixiex) {
 		/*
 		 * If the page is not _PAGE_VALID, RI or XI could not
 		 * have triggered it.  Skip the expensive test..
@@ -1986,7 +1986,7 @@ static void build_r4000_tlb_load_handler(void)
 	build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
 	build_tlb_probe_entry(&p);
 
-	if (cpu_has_rixi) {
+	if (cpu_has_rixi && !cpu_has_rixiex) {
 		/*
 		 * If the page is not _PAGE_VALID, RI or XI could not
 		 * have triggered it.  Skip the expensive test..
-- 
2.0.0

[PATCH 2/3] MIPS: Use dedicated exception handler if CPU supports RI/XI exceptions

[Markos Chandras]

From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>

Use the regular tlb_do_page_fault_0 (no write) handler to handle
the RI and XI exceptions. Also skip the RI/XI validation check
on TLB load handler since it's redundant when the CPU has
unique RI/XI exceptions.

Singed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
 arch/mips/kernel/traps.c | 7 +++++++
 arch/mips/mm/tlbex.c     | 4 ++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 51706d6dd5b0..1a328b1e288b 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -90,6 +90,7 @@ extern asmlinkage void handle_mt(void);
 extern asmlinkage void handle_dsp(void);
 extern asmlinkage void handle_mcheck(void);
 extern asmlinkage void handle_reserved(void);
+extern void tlb_do_page_fault_0(void);
 
 void (*board_be_init)(void);
 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
@@ -2114,6 +2115,12 @@ void __init trap_init(void)
 		set_except_vector(15, handle_fpe);
 
 	set_except_vector(16, handle_ftlb);
+
+	if (cpu_has_rixiex) {
+		set_except_vector(19, tlb_do_page_fault_0);
+		set_except_vector(20, tlb_do_page_fault_0);
+	}
+
 	set_except_vector(21, handle_msa);
 	set_except_vector(22, handle_mdmx);
 
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 0d9d0f06dbb2..ccf8298e7ab2 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -1919,7 +1919,7 @@ static void build_r4000_tlb_load_handler(void)
 	if (m4kc_tlbp_war())
 		build_tlb_probe_entry(&p);
 
-	if (cpu_has_rixi) {
+	if (cpu_has_rixi && !cpu_has_rixiex) {
 		/*
 		 * If the page is not _PAGE_VALID, RI or XI could not
 		 * have triggered it.  Skip the expensive test..
@@ -1986,7 +1986,7 @@ static void build_r4000_tlb_load_handler(void)
 	build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
 	build_tlb_probe_entry(&p);
 
-	if (cpu_has_rixi) {
+	if (cpu_has_rixi && !cpu_has_rixiex) {
 		/*
 		 * If the page is not _PAGE_VALID, RI or XI could not
 		 * have triggered it.  Skip the expensive test..
-- 
2.0.0

[PATCH 3/3] MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions

[Markos Chandras]

From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>

Detect if the core supports unique exception codes for the
Read-Inhibit and Execute-Inhibit exceptions and set the
option accordingly. The RI/XI exception support is detected
by setting the 27th bit (IEC) of the PageGrain C0 register
and reading back the value of that register to verify the
bit is enabled.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
 arch/mips/include/asm/mipsregs.h | 1 +
 arch/mips/kernel/cpu-probe.c     | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 417125548bde..9775c1aba4d3 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -265,6 +265,7 @@
 #define PG_XIE		(_ULCAST_(1) <<	 30)
 #define PG_ELPA		(_ULCAST_(1) <<	 29)
 #define PG_ESP		(_ULCAST_(1) <<	 28)
+#define PG_IEC		(_ULCAST_(1) <<  27)
 
 /*
  * R4x00 interrupt enable / cause bits
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index eb1920ccd263..5995b19fbd66 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -438,6 +438,15 @@ static void decode_configs(struct cpuinfo_mips *c)
 
 	mips_probe_watch_registers(c);
 
+	if (cpu_has_rixi) {
+		/* Enable the RIXI exceptions */
+		write_c0_pagegrain(read_c0_pagegrain() | PG_IEC);
+		back_to_back_c0_hazard();
+		/* Verify the IEC bit is set */
+		if (read_c0_pagegrain() & PG_IEC)
+			c->options |= MIPS_CPU_RIXIEX;
+	}
+
 #ifndef CONFIG_MIPS_CPS
 	if (cpu_has_mips_r2) {
 		c->core = get_ebase_cpunum();
-- 
2.0.0

[PATCH 3/3] MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions

[Markos Chandras]

From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>

Detect if the core supports unique exception codes for the
Read-Inhibit and Execute-Inhibit exceptions and set the
option accordingly. The RI/XI exception support is detected
by setting the 27th bit (IEC) of the PageGrain C0 register
and reading back the value of that register to verify the
bit is enabled.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
 arch/mips/include/asm/mipsregs.h | 1 +
 arch/mips/kernel/cpu-probe.c     | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 417125548bde..9775c1aba4d3 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -265,6 +265,7 @@
 #define PG_XIE		(_ULCAST_(1) <<	 30)
 #define PG_ELPA		(_ULCAST_(1) <<	 29)
 #define PG_ESP		(_ULCAST_(1) <<	 28)
+#define PG_IEC		(_ULCAST_(1) <<  27)
 
 /*
  * R4x00 interrupt enable / cause bits
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index eb1920ccd263..5995b19fbd66 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -438,6 +438,15 @@ static void decode_configs(struct cpuinfo_mips *c)
 
 	mips_probe_watch_registers(c);
 
+	if (cpu_has_rixi) {
+		/* Enable the RIXI exceptions */
+		write_c0_pagegrain(read_c0_pagegrain() | PG_IEC);
+		back_to_back_c0_hazard();
+		/* Verify the IEC bit is set */
+		if (read_c0_pagegrain() & PG_IEC)
+			c->options |= MIPS_CPU_RIXIEX;
+	}
+
 #ifndef CONFIG_MIPS_CPS
 	if (cpu_has_mips_r2) {
 		c->core = get_ebase_cpunum();
-- 
2.0.0

Re: [PATCH 0/3] Use dedicated RI/XI exceptions for MIPSR5 cores

[David Daney]

On 07/15/2014 06:09 AM, Markos Chandras wrote:
> Hi,
>
> This patchset adds support for unique RI/XI exceptions. This feature has
> been added in MIPSr5. Using this feature, we reduce the time it takes
> to deal with a TLB exception caused by the RI/XI bits since the TLB load
> handler is skipped and we use the tlb_do_page_failt_0 path directly.
>
> This patch depends on the Hardware Page Table Walker (HTW) patchset
> http://www.linux-mips.org/archives/linux-mips/2014-07/msg00195.html

They are unrelated features, why the dependency?


>
> Leonid Yegoshin (3):
>    MIPS: Add new option for unique RI/XI exceptions
>    MIPS: Use dedicated exception handler if CPU supports RI/XI exceptions
>    MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions

There is code in mm/fault.c that generates the SIGSEGV for the RI/XI 
violations.  If we are using the dedicated RI/XI exception vectors, that 
code no longer has to make assumptions about what caused the exception.

I wonder if this should be reworked so that we don't make any 
assumptions about the cause of the exception.

David Daney


>
>   arch/mips/include/asm/cpu-features.h | 3 +++
>   arch/mips/include/asm/cpu.h          | 1 +
>   arch/mips/include/asm/mipsregs.h     | 1 +
>   arch/mips/kernel/cpu-probe.c         | 9 +++++++++
>   arch/mips/kernel/traps.c             | 7 +++++++
>   arch/mips/mm/tlbex.c                 | 4 ++--
>   6 files changed, 23 insertions(+), 2 deletions(-)
>

Re: [PATCH 0/3] Use dedicated RI/XI exceptions for MIPSR5 cores

[Markos Chandras]

Hi David,

On 07/15/2014 07:50 PM, David Daney wrote:
> On 07/15/2014 06:09 AM, Markos Chandras wrote:
>> Hi,
>>
>> This patchset adds support for unique RI/XI exceptions. This feature has
>> been added in MIPSr5. Using this feature, we reduce the time it takes
>> to deal with a TLB exception caused by the RI/XI bits since the TLB load
>> handler is skipped and we use the tlb_do_page_failt_0 path directly.
>>
>> This patch depends on the Hardware Page Table Walker (HTW) patchset
>> http://www.linux-mips.org/archives/linux-mips/2014-07/msg00195.html
> 
> They are unrelated features, why the dependency?
Because of the conflicts in cpu.h and cpu-features.h. I am just trying
to make Ralf' life easier when he tries to determine the order to apply
this patches.

-- 
markos

Re: [PATCH 0/3] Use dedicated RI/XI exceptions for MIPSR5 cores

[Markos Chandras]

Hi David,

On 07/15/2014 07:50 PM, David Daney wrote:
> On 07/15/2014 06:09 AM, Markos Chandras wrote:
>> Hi,
>>
>> This patchset adds support for unique RI/XI exceptions. This feature has
>> been added in MIPSr5. Using this feature, we reduce the time it takes
>> to deal with a TLB exception caused by the RI/XI bits since the TLB load
>> handler is skipped and we use the tlb_do_page_failt_0 path directly.
>>
>> This patch depends on the Hardware Page Table Walker (HTW) patchset
>> http://www.linux-mips.org/archives/linux-mips/2014-07/msg00195.html
> 
> They are unrelated features, why the dependency?
Because of the conflicts in cpu.h and cpu-features.h. I am just trying
to make Ralf' life easier when he tries to determine the order to apply
this patches.

-- 
markos