From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2] clocksource: arch_timer: Allow the device tree to specify the physical timer
Date: Thu, 11 Sep 2014 18:22:47 +0100 [thread overview]
Message-ID: <5411DA67.2040402@arm.com> (raw)
In-Reply-To: <CAD=FV=XMmizxJFPj0FEhJ7Gk4ZcQaUJDxf_Qq5kGKSvxDFVmzg@mail.gmail.com>
On 11/09/14 18:11, Doug Anderson wrote:
> Hi,
>
> On Thu, Sep 11, 2014 at 10:00 AM, Marc Zyngier <marc.zyngier@arm.com> wrote:
>> On 11/09/14 17:47, Will Deacon wrote:
>>> On Thu, Sep 11, 2014 at 05:16:44PM +0100, Doug Anderson wrote:
>>>> Some 32-bit (ARMv7) systems are architected like this:
>>>>
>>>> * The firmware doesn't know and doesn't care about hypervisor mode and
>>>> we don't want to add the complexity of hypervisor there.
>>>>
>>>> * The firmware isn't involved in SMP bringup or resume.
>>>>
>>>> * The ARCH timer come up with an uninitialized offset between the
>>>> virtual and physical counters. Each core gets a different random
>>>> offset.
>>>>
>>>> On systems like the above, it doesn't make sense to use the virtual
>>>> counter. There's nobody managing the offset and each time a core goes
>>>> down and comes back up it will get reinitialized to some other random
>>>> value.
>>>
>>> You probably need to rephrase this slightly, as there *is* still a
>>> requirement on the hypervisor/firmware (actually, two!). See below.
>>>
>>>> Let's add a property to the device tree to say that we shouldn't use
>>>> the virtual timer. Firmware could potentially remove this property
>>>> before passing the device tree to the kernel if it really wants the
>>>> kernel to use a virtual timer.
>>>>
>>>> Note that it's been said that ARM64 (ARMv8) systems the firmware and
>>>> kernel really can't be architected as described above. That means
>>>> using the physical timer like this really only makes sense for ARMv7
>>>> systems.
>>>
>>> I'd go further: this only makes sense if you're booting in secure SVC
>>> mode.
>>
>> If that's the case, what's the problem? Enter monitor mode, set SCR.NS
>> to one, nuke CNTVOFF, revert, job done.
>>
>> What am I missing?
>
> Stuff like this was talked about in the thread about Sonny's patch at
> <https://patchwork.kernel.org/patch/4790921/>
>
> ...in that case we were always talking about HYP mode, though. I
That's because I always assumed that you'd be running non-secure,
dropped there by some idiotic firmware without any way to go back up.
> don't think anyone has explicitly talked about just switching to
> monitor mode and then leaving ourselves in Secure SVC after we're
> done. It would be nice (especially for the VDSO guys) if we could
> just init the virtual offset...
>
> We would need to run this code potentially at processor bringup and
> after suspend/resume, but that seems possible too.
Note that this would be an ARMv7 only thing (you can't do that on ARMv8,
at all).
> Is the transition to monitor mode and back simple? Where would you
> suggest putting this code? It would definitely need to be pretty
> early. We'd also need to be able to detect that we're in Secure SVC
> and not mess up anyone else who happened to boot in Non Secure SVC.
This would have to live in some very early platform-specific code. The
ugly part is that you cannot find out what world you're in (accessing
SCR is going to send you to UNDEF-land if accessed from NS).
If I was suicidal, I'd suggest you could pass a parameter to the command
line, interpreted by the timer code... But I since I'm not, let's
pretend I haven't said anything... ;-)
M.
--
Jazz is not dead. It just smells funny...
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>
To: Doug Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Cc: Will Deacon <Will.Deacon-5wv7dgnIgG8@public.gmane.org>,
"olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org"
<olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org>,
Sonny Rao <sonnyrao-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
Catalin Marinas <Catalin.Marinas-5wv7dgnIgG8@public.gmane.org>,
Mark Rutland <Mark.Rutland-5wv7dgnIgG8@public.gmane.org>,
Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Sudeep Holla <Sudeep.Holla-5wv7dgnIgG8@public.gmane.org>,
Christopher Covington
<cov-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Lorenzo Pieralisi
<Lorenzo.Pieralisi-5wv7dgnIgG8@public.gmane.org>,
Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>,
Daniel Lezcano
<daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Nathan Lynch
<Nathan_Lynch-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>,
"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
"robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org"
<robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Pawel Moll <Pawel.Moll-5wv7dgnIgG8@public.gmane.org>,
"ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org"
<ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
"galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org"
<galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
"devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
Subject: Re: [PATCH v2] clocksource: arch_timer: Allow the device tree to specify the physical timer
Date: Thu, 11 Sep 2014 18:22:47 +0100 [thread overview]
Message-ID: <5411DA67.2040402@arm.com> (raw)
In-Reply-To: <CAD=FV=XMmizxJFPj0FEhJ7Gk4ZcQaUJDxf_Qq5kGKSvxDFVmzg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 11/09/14 18:11, Doug Anderson wrote:
> Hi,
>
> On Thu, Sep 11, 2014 at 10:00 AM, Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org> wrote:
>> On 11/09/14 17:47, Will Deacon wrote:
>>> On Thu, Sep 11, 2014 at 05:16:44PM +0100, Doug Anderson wrote:
>>>> Some 32-bit (ARMv7) systems are architected like this:
>>>>
>>>> * The firmware doesn't know and doesn't care about hypervisor mode and
>>>> we don't want to add the complexity of hypervisor there.
>>>>
>>>> * The firmware isn't involved in SMP bringup or resume.
>>>>
>>>> * The ARCH timer come up with an uninitialized offset between the
>>>> virtual and physical counters. Each core gets a different random
>>>> offset.
>>>>
>>>> On systems like the above, it doesn't make sense to use the virtual
>>>> counter. There's nobody managing the offset and each time a core goes
>>>> down and comes back up it will get reinitialized to some other random
>>>> value.
>>>
>>> You probably need to rephrase this slightly, as there *is* still a
>>> requirement on the hypervisor/firmware (actually, two!). See below.
>>>
>>>> Let's add a property to the device tree to say that we shouldn't use
>>>> the virtual timer. Firmware could potentially remove this property
>>>> before passing the device tree to the kernel if it really wants the
>>>> kernel to use a virtual timer.
>>>>
>>>> Note that it's been said that ARM64 (ARMv8) systems the firmware and
>>>> kernel really can't be architected as described above. That means
>>>> using the physical timer like this really only makes sense for ARMv7
>>>> systems.
>>>
>>> I'd go further: this only makes sense if you're booting in secure SVC
>>> mode.
>>
>> If that's the case, what's the problem? Enter monitor mode, set SCR.NS
>> to one, nuke CNTVOFF, revert, job done.
>>
>> What am I missing?
>
> Stuff like this was talked about in the thread about Sonny's patch at
> <https://patchwork.kernel.org/patch/4790921/>
>
> ...in that case we were always talking about HYP mode, though. I
That's because I always assumed that you'd be running non-secure,
dropped there by some idiotic firmware without any way to go back up.
> don't think anyone has explicitly talked about just switching to
> monitor mode and then leaving ourselves in Secure SVC after we're
> done. It would be nice (especially for the VDSO guys) if we could
> just init the virtual offset...
>
> We would need to run this code potentially at processor bringup and
> after suspend/resume, but that seems possible too.
Note that this would be an ARMv7 only thing (you can't do that on ARMv8,
at all).
> Is the transition to monitor mode and back simple? Where would you
> suggest putting this code? It would definitely need to be pretty
> early. We'd also need to be able to detect that we're in Secure SVC
> and not mess up anyone else who happened to boot in Non Secure SVC.
This would have to live in some very early platform-specific code. The
ugly part is that you cannot find out what world you're in (accessing
SCR is going to send you to UNDEF-land if accessed from NS).
If I was suicidal, I'd suggest you could pass a parameter to the command
line, interpreted by the timer code... But I since I'm not, let's
pretend I haven't said anything... ;-)
M.
--
Jazz is not dead. It just smells funny...
--
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WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <marc.zyngier@arm.com>
To: Doug Anderson <dianders@chromium.org>
Cc: Will Deacon <Will.Deacon@arm.com>,
"olof@lixom.net" <olof@lixom.net>,
Sonny Rao <sonnyrao@chromium.org>,
Catalin Marinas <Catalin.Marinas@arm.com>,
Mark Rutland <Mark.Rutland@arm.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Sudeep Holla <Sudeep.Holla@arm.com>,
Christopher Covington <cov@codeaurora.org>,
Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Nathan Lynch <Nathan_Lynch@mentor.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
Pawel Moll <Pawel.Moll@arm.com>,
"ijc+devicetree@hellion.org.uk" <ijc+devicetree@hellion.org.uk>,
"galak@codeaurora.org" <galak@codeaurora.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] clocksource: arch_timer: Allow the device tree to specify the physical timer
Date: Thu, 11 Sep 2014 18:22:47 +0100 [thread overview]
Message-ID: <5411DA67.2040402@arm.com> (raw)
In-Reply-To: <CAD=FV=XMmizxJFPj0FEhJ7Gk4ZcQaUJDxf_Qq5kGKSvxDFVmzg@mail.gmail.com>
On 11/09/14 18:11, Doug Anderson wrote:
> Hi,
>
> On Thu, Sep 11, 2014 at 10:00 AM, Marc Zyngier <marc.zyngier@arm.com> wrote:
>> On 11/09/14 17:47, Will Deacon wrote:
>>> On Thu, Sep 11, 2014 at 05:16:44PM +0100, Doug Anderson wrote:
>>>> Some 32-bit (ARMv7) systems are architected like this:
>>>>
>>>> * The firmware doesn't know and doesn't care about hypervisor mode and
>>>> we don't want to add the complexity of hypervisor there.
>>>>
>>>> * The firmware isn't involved in SMP bringup or resume.
>>>>
>>>> * The ARCH timer come up with an uninitialized offset between the
>>>> virtual and physical counters. Each core gets a different random
>>>> offset.
>>>>
>>>> On systems like the above, it doesn't make sense to use the virtual
>>>> counter. There's nobody managing the offset and each time a core goes
>>>> down and comes back up it will get reinitialized to some other random
>>>> value.
>>>
>>> You probably need to rephrase this slightly, as there *is* still a
>>> requirement on the hypervisor/firmware (actually, two!). See below.
>>>
>>>> Let's add a property to the device tree to say that we shouldn't use
>>>> the virtual timer. Firmware could potentially remove this property
>>>> before passing the device tree to the kernel if it really wants the
>>>> kernel to use a virtual timer.
>>>>
>>>> Note that it's been said that ARM64 (ARMv8) systems the firmware and
>>>> kernel really can't be architected as described above. That means
>>>> using the physical timer like this really only makes sense for ARMv7
>>>> systems.
>>>
>>> I'd go further: this only makes sense if you're booting in secure SVC
>>> mode.
>>
>> If that's the case, what's the problem? Enter monitor mode, set SCR.NS
>> to one, nuke CNTVOFF, revert, job done.
>>
>> What am I missing?
>
> Stuff like this was talked about in the thread about Sonny's patch at
> <https://patchwork.kernel.org/patch/4790921/>
>
> ...in that case we were always talking about HYP mode, though. I
That's because I always assumed that you'd be running non-secure,
dropped there by some idiotic firmware without any way to go back up.
> don't think anyone has explicitly talked about just switching to
> monitor mode and then leaving ourselves in Secure SVC after we're
> done. It would be nice (especially for the VDSO guys) if we could
> just init the virtual offset...
>
> We would need to run this code potentially at processor bringup and
> after suspend/resume, but that seems possible too.
Note that this would be an ARMv7 only thing (you can't do that on ARMv8,
at all).
> Is the transition to monitor mode and back simple? Where would you
> suggest putting this code? It would definitely need to be pretty
> early. We'd also need to be able to detect that we're in Secure SVC
> and not mess up anyone else who happened to boot in Non Secure SVC.
This would have to live in some very early platform-specific code. The
ugly part is that you cannot find out what world you're in (accessing
SCR is going to send you to UNDEF-land if accessed from NS).
If I was suicidal, I'd suggest you could pass a parameter to the command
line, interpreted by the timer code... But I since I'm not, let's
pretend I haven't said anything... ;-)
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2014-09-11 17:22 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-11 16:16 [PATCH v2] clocksource: arch_timer: Allow the device tree to specify the physical timer Doug Anderson
2014-09-11 16:16 ` Doug Anderson
2014-09-11 16:47 ` Will Deacon
2014-09-11 16:47 ` Will Deacon
2014-09-11 16:47 ` Will Deacon
2014-09-11 16:59 ` Doug Anderson
2014-09-11 16:59 ` Doug Anderson
2014-09-11 16:59 ` Doug Anderson
2014-09-11 17:07 ` Will Deacon
2014-09-11 17:07 ` Will Deacon
2014-09-11 17:14 ` Doug Anderson
2014-09-11 17:14 ` Doug Anderson
2014-09-11 17:00 ` Marc Zyngier
2014-09-11 17:00 ` Marc Zyngier
2014-09-11 17:11 ` Doug Anderson
2014-09-11 17:11 ` Doug Anderson
2014-09-11 17:11 ` Doug Anderson
2014-09-11 17:22 ` Marc Zyngier [this message]
2014-09-11 17:22 ` Marc Zyngier
2014-09-11 17:22 ` Marc Zyngier
2014-09-11 17:29 ` Doug Anderson
2014-09-11 17:29 ` Doug Anderson
2014-09-11 17:29 ` Doug Anderson
2014-09-11 17:43 ` Marc Zyngier
2014-09-11 17:43 ` Marc Zyngier
2014-09-11 17:43 ` Marc Zyngier
2014-09-11 23:55 ` Doug Anderson
2014-09-11 23:55 ` Doug Anderson
2014-09-11 23:55 ` Doug Anderson
2014-09-11 23:56 ` Stephen Boyd
2014-09-11 23:56 ` Stephen Boyd
2014-09-11 23:56 ` Stephen Boyd
2014-09-12 0:01 ` Doug Anderson
2014-09-12 0:01 ` Doug Anderson
2014-09-12 0:01 ` Doug Anderson
2014-09-12 10:20 ` Marc Zyngier
2014-09-12 10:20 ` Marc Zyngier
2014-09-12 0:14 ` Sonny Rao
2014-09-12 1:17 ` Stephen Boyd
2014-09-12 3:25 ` Sonny Rao
2014-09-12 3:25 ` Sonny Rao
2014-09-12 3:25 ` Sonny Rao
2014-09-12 11:43 ` Christopher Covington
2014-09-12 11:43 ` Christopher Covington
2014-09-12 11:43 ` Christopher Covington
2014-09-12 12:14 ` Marc Zyngier
2014-09-12 12:14 ` Marc Zyngier
2014-09-12 18:59 ` Stephen Boyd
2014-09-12 18:59 ` Stephen Boyd
2014-09-12 18:59 ` Stephen Boyd
2014-09-15 11:10 ` Catalin Marinas
2014-09-15 11:10 ` Catalin Marinas
2014-09-15 11:10 ` Catalin Marinas
2014-09-15 20:33 ` Stephen Boyd
2014-09-15 20:33 ` Stephen Boyd
2014-09-15 21:47 ` Sonny Rao
2014-09-15 21:47 ` Sonny Rao
2014-09-15 21:47 ` Sonny Rao
2014-09-15 21:49 ` Stephen Boyd
2014-09-15 21:49 ` Stephen Boyd
2014-09-15 21:49 ` Stephen Boyd
2014-09-15 21:52 ` Sonny Rao
2014-09-15 21:52 ` Sonny Rao
2014-09-15 21:52 ` Sonny Rao
2014-09-15 22:04 ` Sonny Rao
2014-09-15 22:04 ` Sonny Rao
2014-09-15 22:04 ` Sonny Rao
2014-09-15 22:51 ` Christopher Covington
2014-09-15 22:51 ` Christopher Covington
2014-09-15 22:51 ` Christopher Covington
2014-09-16 0:24 ` Sonny Rao
2014-09-16 0:24 ` Sonny Rao
2014-09-16 0:24 ` Sonny Rao
2014-09-16 10:42 ` Catalin Marinas
2014-09-16 10:42 ` Catalin Marinas
2014-09-16 10:42 ` Catalin Marinas
2014-09-16 11:22 ` Christopher Covington
2014-09-16 11:22 ` Christopher Covington
2014-09-16 11:22 ` Christopher Covington
2014-09-16 11:03 ` Catalin Marinas
2014-09-16 11:03 ` Catalin Marinas
2014-09-16 11:03 ` Catalin Marinas
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