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From: Timur Tabi <timur@codeaurora.org>
To: Andre Przywara <andre.przywara@arm.com>, Jun Nie <jun.nie@linaro.org>
Cc: "linux@arm.linux.org.uk" <linux@arm.linux.org.uk>,
	"peter@hurleysoftware.com" <peter@hurleysoftware.com>,
	"jason.liu@linaro.org" <jason.liu@linaro.org>,
	"gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
	Andrew Jackson <Andrew.Jackson@arm.com>,
	"linux-serial@vger.kernel.org" <linux-serial@vger.kernel.org>,
	"shawn.guo@linaro.org" <shawn.guo@linaro.org>,
	"wan.zhijun@zte.com.cn" <wan.zhijun@zte.com.cn>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v13 5/5] uart: pl011: Add support to ZTE ZX296702 uart
Date: Mon, 26 Oct 2015 09:07:42 -0500	[thread overview]
Message-ID: <562E33AE.2020608@codeaurora.org> (raw)
In-Reply-To: <562E3213.8070602@arm.com>

Andre Przywara wrote:

> Yeah, I was interested in that scenario too, because the SBSA spec
> actually speaks of 32-bit registers and vendors may implement it
> strictly as that. Still waiting for actual failure reports on this
> before I wanted to push a fix, though.

What do you mean by failure reports?  Our hardware generates an SError 
if you try to access the PL011 registers with 8-bit or 16-bit reads or 
writes.

>> We have an internal patch
>> that replaces all of the read/write routines with vendor function calls.
>>   I would need to refactor our patch on top of yours.
>
> But wouldn't Jun's patch address this more easily, because it wraps
> every call already? TBH I found this change the most interesting.

Yes, but I think it changes a lot of things unnecessarily, like the 
register names.

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the
Code Aurora Forum, hosted by The Linux Foundation.

WARNING: multiple messages have this Message-ID (diff)
From: timur@codeaurora.org (Timur Tabi)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v13 5/5] uart: pl011: Add support to ZTE ZX296702 uart
Date: Mon, 26 Oct 2015 09:07:42 -0500	[thread overview]
Message-ID: <562E33AE.2020608@codeaurora.org> (raw)
In-Reply-To: <562E3213.8070602@arm.com>

Andre Przywara wrote:

> Yeah, I was interested in that scenario too, because the SBSA spec
> actually speaks of 32-bit registers and vendors may implement it
> strictly as that. Still waiting for actual failure reports on this
> before I wanted to push a fix, though.

What do you mean by failure reports?  Our hardware generates an SError 
if you try to access the PL011 registers with 8-bit or 16-bit reads or 
writes.

>> We have an internal patch
>> that replaces all of the read/write routines with vendor function calls.
>>   I would need to refactor our patch on top of yours.
>
> But wouldn't Jun's patch address this more easily, because it wraps
> every call already? TBH I found this change the most interesting.

Yes, but I think it changes a lot of things unnecessarily, like the 
register names.

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the
Code Aurora Forum, hosted by The Linux Foundation.

  reply	other threads:[~2015-10-26 14:07 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <1438328959-16177-1-git-send-email-jun.nie@linaro.org>
     [not found] ` <1438328959-16177-3-git-send-email-jun.nie@linaro.org>
2015-09-18 10:51   ` [PATCH v13 2/5] uart: pl011: Introduce register accessor Andre Przywara
2015-09-18 10:51     ` Andre Przywara
2015-09-19  6:46     ` Jun Nie
2015-09-19  6:46       ` Jun Nie
2015-09-19 21:45       ` Andre Przywara
2015-09-19 21:45         ` Andre Przywara
2015-10-22 23:36     ` Timur Tabi
2015-10-22 23:36       ` Timur Tabi
2015-10-28 14:22       ` Peter Hurley
2015-10-28 14:22         ` Peter Hurley
2015-10-28 14:51         ` Timur Tabi
2015-10-28 14:51           ` Timur Tabi
2015-10-28 15:08           ` Peter Hurley
2015-10-28 15:08             ` Peter Hurley
     [not found] ` <1438328959-16177-5-git-send-email-jun.nie@linaro.org>
2015-09-18 10:58   ` [PATCH v13 4/5] uart: pl011: Improve LCRH register access decision Andre Przywara
2015-09-18 10:58     ` Andre Przywara
     [not found] ` <1438328959-16177-6-git-send-email-jun.nie@linaro.org>
2015-09-18 13:50   ` [PATCH v13 5/5] uart: pl011: Add support to ZTE ZX296702 uart Andre Przywara
2015-09-18 13:50     ` Andre Przywara
2015-09-18 13:59     ` Russell King - ARM Linux
2015-09-18 13:59       ` Russell King - ARM Linux
2015-09-19  6:47       ` Jun Nie
2015-09-19  6:47         ` Jun Nie
2015-09-19  6:54     ` Jun Nie
2015-09-19  6:54       ` Jun Nie
2015-10-23 21:54       ` Timur Tabi
2015-10-23 21:54         ` Timur Tabi
2015-10-24  3:23         ` Jun Nie
2015-10-24  3:23           ` Jun Nie
2015-10-24  3:32           ` Timur Tabi
2015-10-24  3:32             ` Timur Tabi
2015-10-26  1:27             ` Jun Nie
2015-10-26  1:27               ` Jun Nie
2015-10-27 13:31               ` Peter Hurley
2015-10-27 13:31                 ` Peter Hurley
2015-10-26  9:59             ` Andre Przywara
2015-10-26  9:59               ` Andre Przywara
2015-10-26 12:46               ` Timur Tabi
2015-10-26 12:46                 ` Timur Tabi
2015-10-26 14:00                 ` Andre Przywara
2015-10-26 14:00                   ` Andre Przywara
2015-10-26 14:07                   ` Timur Tabi [this message]
2015-10-26 14:07                     ` Timur Tabi
2015-10-26 14:42                     ` Andre Przywara
2015-10-26 14:42                       ` Andre Przywara
2015-10-26 14:47                       ` Timur Tabi
2015-10-26 14:47                         ` Timur Tabi
2015-10-26 15:19                         ` Andre Przywara
2015-10-26 15:19                           ` Andre Przywara
2015-10-26 15:31                           ` Timur Tabi
2015-10-26 15:31                             ` Timur Tabi
2015-10-27 22:54                           ` Timur Tabi
2015-10-27 22:54                             ` Timur Tabi

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