From: Thomas Gleixner <tglx@linutronix.de>
To: Yu Chien Peter Lin <peterlin@andestech.com>,
acme@kernel.org, adrian.hunter@intel.com,
ajones@ventanamicro.com, alexander.shishkin@linux.intel.com,
andre.przywara@arm.com, anup@brainfault.org,
aou@eecs.berkeley.edu, atishp@atishpatra.org,
conor+dt@kernel.org, conor.dooley@microchip.com,
conor@kernel.org, devicetree@vger.kernel.org,
dminus@andestech.com, evan@rivosinc.com, geert+renesas@glider.be,
guoren@kernel.org, heiko@sntech.de, irogers@google.com,
jernej.skrabec@gmail.com, jolsa@kernel.org, jszhang@kernel.org,
krzysztof.kozlowski+dt@linaro.org,
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linux-renesas-soc@vger.kernel.org,
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namhyung@kernel.org, palmer@dabbelt.com,
paul.walmsley@sifive.com, peterlin@andestech.com,
peterz@infradead.org, prabhakar.mahadev-lad.rj@bp.renesas.com,
rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org,
sunilvl@ventanamicro.com, tim609@andestech.com, uwu@icenowy.me,
wens@csie.org, will@kernel.org, ycliang@andestech.com,
inochiama@outlook.com
Subject: Re: [PATCH v4 02/13] irqchip/riscv-intc: Allow large non-standard interrupt number
Date: Fri, 08 Dec 2023 16:54:34 +0100 [thread overview]
Message-ID: <871qbwsn9h.ffs@tglx> (raw)
In-Reply-To: <20231122121235.827122-3-peterlin@andestech.com>
On Wed, Nov 22 2023 at 20:12, Yu Chien Peter Lin wrote:
> Currently, the implementation of the RISC-V INTC driver uses the
> interrupt cause as hwirq and has a limitation of supporting a
s/hwirq/hardware interrupt/
Please spell things out. We are not on Xitter here.
> maximum of 64 hwirqs. However, according to the privileged spec,
> interrupt causes >= 16 are defined for platform use.
>
> This limitation prevents us from fully utilizing the available
This limitation prevents to fully utilize the ...
> local interrupt sources. Additionally, the hwirqs used on RISC-V
> are sparse, with only interrupt numbers 1, 5 and 9 (plus Sscofpmf
> or T-Head's PMU irq) being currently used for supervisor mode.
>
> Switch to using irq_domain_create_tree() to create the radix tree
> map, so a larger number of hardware interrupts can be handled.
WARNING: multiple messages have this Message-ID (diff)
From: Thomas Gleixner <tglx@linutronix.de>
To: Yu Chien Peter Lin <peterlin@andestech.com>,
acme@kernel.org, adrian.hunter@intel.com,
ajones@ventanamicro.com, alexander.shishkin@linux.intel.com,
andre.przywara@arm.com, anup@brainfault.org,
aou@eecs.berkeley.edu, atishp@atishpatra.org,
conor+dt@kernel.org, conor.dooley@microchip.com,
conor@kernel.org, devicetree@vger.kernel.org,
dminus@andestech.com, evan@rivosinc.com, geert+renesas@glider.be,
guoren@kernel.org, heiko@sntech.de, irogers@google.com,
jernej.skrabec@gmail.com, jolsa@kernel.org, jszhang@kernel.org,
krzysztof.kozlowski+dt@linaro.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
linux-renesas-soc@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev,
locus84@andestech.com, magnus.damm@gmail.com,
mark.rutland@arm.com, mingo@redhat.com, n.shubin@yadro.com,
namhyung@kernel.org, palmer@dabbelt.com,
paul.walmsley@sifive.com, peterlin@andestech.com,
peterz@infradead.org, prabhakar.mahadev-lad.rj@bp.renesas.com,
rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org,
sunilvl@ventanamicro.com, tim609@andestech.com, uwu@icenowy.me,
wens@csie.org, will@kernel.org, ycliang@andestech.com,
inochiama@outlook.com
Subject: Re: [PATCH v4 02/13] irqchip/riscv-intc: Allow large non-standard interrupt number
Date: Fri, 08 Dec 2023 16:54:34 +0100 [thread overview]
Message-ID: <871qbwsn9h.ffs@tglx> (raw)
In-Reply-To: <20231122121235.827122-3-peterlin@andestech.com>
On Wed, Nov 22 2023 at 20:12, Yu Chien Peter Lin wrote:
> Currently, the implementation of the RISC-V INTC driver uses the
> interrupt cause as hwirq and has a limitation of supporting a
s/hwirq/hardware interrupt/
Please spell things out. We are not on Xitter here.
> maximum of 64 hwirqs. However, according to the privileged spec,
> interrupt causes >= 16 are defined for platform use.
>
> This limitation prevents us from fully utilizing the available
This limitation prevents to fully utilize the ...
> local interrupt sources. Additionally, the hwirqs used on RISC-V
> are sparse, with only interrupt numbers 1, 5 and 9 (plus Sscofpmf
> or T-Head's PMU irq) being currently used for supervisor mode.
>
> Switch to using irq_domain_create_tree() to create the radix tree
> map, so a larger number of hardware interrupts can be handled.
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next prev parent reply other threads:[~2023-12-08 15:54 UTC|newest]
Thread overview: 117+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-22 12:12 [PATCH v4 00/13] Support Andes PMU extension Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 01/13] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-24 14:57 ` Lad, Prabhakar
2023-11-24 14:57 ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 02/13] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-12-08 15:54 ` Thomas Gleixner [this message]
2023-12-08 15:54 ` Thomas Gleixner
2023-12-12 10:17 ` Yu-Chien Peter Lin
2023-12-12 10:17 ` Yu-Chien Peter Lin
2023-12-12 10:17 ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 03/13] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-12-08 16:01 ` Thomas Gleixner
2023-12-08 16:01 ` Thomas Gleixner
2023-12-12 10:28 ` Yu-Chien Peter Lin
2023-12-12 10:28 ` Yu-Chien Peter Lin
2023-12-12 10:28 ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-23 14:38 ` Conor Dooley
2023-11-23 14:38 ` Conor Dooley
2023-11-23 14:38 ` Conor Dooley
2023-11-24 15:03 ` Lad, Prabhakar
2023-11-24 15:03 ` Lad, Prabhakar
2023-11-24 15:05 ` Conor Dooley
2023-11-24 15:05 ` Conor Dooley
2023-11-29 6:43 ` Yu-Chien Peter Lin
2023-11-29 6:43 ` Yu-Chien Peter Lin
2023-11-29 6:43 ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 05/13] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-22 16:36 ` Geert Uytterhoeven
2023-11-22 16:36 ` Geert Uytterhoeven
2023-11-22 16:36 ` Geert Uytterhoeven
2023-11-24 15:04 ` Lad, Prabhakar
2023-11-24 15:04 ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 06/13] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 07/13] RISC-V: Move T-Head PMU to CPU feature alternative framework Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-22 21:16 ` Guo Ren
2023-11-22 21:16 ` Guo Ren
2023-11-22 21:16 ` Guo Ren
2023-11-23 14:45 ` Conor Dooley
2023-11-23 14:45 ` Conor Dooley
2023-11-23 14:45 ` Conor Dooley
2023-11-22 12:12 ` [PATCH v4 08/13] perf: RISC-V: Introduce Andes PMU for perf event sampling Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-24 15:06 ` Lad, Prabhakar
2023-11-24 15:06 ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 09/13] dt-bindings: riscv: Add T-Head PMU extension description Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-22 21:14 ` Guo Ren
2023-11-22 21:14 ` Guo Ren
2023-11-22 21:14 ` Guo Ren
2023-11-29 8:48 ` Yu-Chien Peter Lin
2023-11-29 8:48 ` Yu-Chien Peter Lin
2023-11-29 8:48 ` Yu-Chien Peter Lin
2023-11-30 8:29 ` Inochi Amaoto
2023-11-30 8:29 ` Inochi Amaoto
2023-11-30 9:21 ` Yu-Chien Peter Lin
2023-11-30 9:21 ` Yu-Chien Peter Lin
2023-11-30 9:21 ` Yu-Chien Peter Lin
2023-11-30 12:16 ` Inochi Amaoto
2023-11-30 12:16 ` Inochi Amaoto
2023-11-30 12:58 ` Conor Dooley
2023-11-30 12:58 ` Conor Dooley
2023-11-30 12:58 ` Conor Dooley
2023-11-30 23:11 ` Inochi Amaoto
2023-11-30 23:11 ` Inochi Amaoto
2023-12-01 0:40 ` Conor Dooley
2023-12-01 0:40 ` Conor Dooley
2023-12-01 0:40 ` Conor Dooley
2023-12-01 0:57 ` Inochi Amaoto
2023-12-01 0:57 ` Inochi Amaoto
2023-12-01 1:14 ` Inochi Amaoto
2023-12-01 1:14 ` Inochi Amaoto
2023-12-06 3:14 ` Yu-Chien Peter Lin
2023-12-06 3:14 ` Yu-Chien Peter Lin
2023-12-06 3:14 ` Yu-Chien Peter Lin
2023-11-23 14:48 ` Conor Dooley
2023-11-23 14:48 ` Conor Dooley
2023-11-23 14:48 ` Conor Dooley
2023-11-29 8:47 ` Yu-Chien Peter Lin
2023-11-29 8:47 ` Yu-Chien Peter Lin
2023-11-29 8:47 ` Yu-Chien Peter Lin
2023-11-29 12:33 ` Conor Dooley
2023-11-29 12:33 ` Conor Dooley
2023-11-29 12:33 ` Conor Dooley
2023-11-22 12:12 ` [PATCH v4 10/13] dt-bindings: riscv: Add Andes " Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-24 15:07 ` Lad, Prabhakar
2023-11-24 15:07 ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 11/13] riscv: dts: allwinner: Add T-Head PMU extension Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-22 21:12 ` Guo Ren
2023-11-22 21:12 ` Guo Ren
2023-11-22 21:12 ` Guo Ren
2023-11-23 14:58 ` Conor Dooley
2023-11-23 14:58 ` Conor Dooley
2023-11-23 14:58 ` Conor Dooley
2023-11-29 9:34 ` Yu-Chien Peter Lin
2023-11-29 9:34 ` Yu-Chien Peter Lin
2023-11-29 9:34 ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 12/13] riscv: dts: renesas: Add Andes " Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-22 16:34 ` Geert Uytterhoeven
2023-11-22 16:34 ` Geert Uytterhoeven
2023-11-24 15:07 ` Lad, Prabhakar
2023-11-24 15:07 ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 13/13] riscv: andes: Support symbolic FW and HW raw events Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-24 15:08 ` Lad, Prabhakar
2023-11-24 15:08 ` Lad, Prabhakar
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