From: Yu-Chien Peter Lin <peterlin@andestech.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: <acme@kernel.org>, <adrian.hunter@intel.com>,
<ajones@ventanamicro.com>, <alexander.shishkin@linux.intel.com>,
<andre.przywara@arm.com>, <anup@brainfault.org>,
<aou@eecs.berkeley.edu>, <atishp@atishpatra.org>,
<conor+dt@kernel.org>, <conor.dooley@microchip.com>,
<conor@kernel.org>, <devicetree@vger.kernel.org>,
<dminus@andestech.com>, <evan@rivosinc.com>,
<geert+renesas@glider.be>, <guoren@kernel.org>, <heiko@sntech.de>,
<irogers@google.com>, <jernej.skrabec@gmail.com>,
<jolsa@kernel.org>, <jszhang@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-perf-users@vger.kernel.org>,
<linux-renesas-soc@vger.kernel.org>,
<linux-riscv@lists.infradead.org>, <linux-sunxi@lists.linux.dev>,
<locus84@andestech.com>, <magnus.damm@gmail.com>,
<mark.rutland@arm.com>, <mingo@redhat.com>, <n.shubin@yadro.com>,
<namhyung@kernel.org>, <palmer@dabbelt.com>,
<paul.walmsley@sifive.com>, <peterz@infradead.org>,
<prabhakar.mahadev-lad.rj@bp.renesas.com>,
<rdunlap@infradead.org>, <robh+dt@kernel.org>,
<samuel@sholland.org>, <sunilvl@ventanamicro.com>,
<tim609@andestech.com>, <uwu@icenowy.me>, <wens@csie.org>,
<will@kernel.org>, <ycliang@andestech.com>,
<inochiama@outlook.com>
Subject: Re: [PATCH v4 02/13] irqchip/riscv-intc: Allow large non-standard interrupt number
Date: Tue, 12 Dec 2023 18:17:41 +0800 [thread overview]
Message-ID: <ZXgzRZK8uqgmY84L@APC323> (raw)
In-Reply-To: <871qbwsn9h.ffs@tglx>
Hi Thomas,
On Fri, Dec 08, 2023 at 04:54:34PM +0100, Thomas Gleixner wrote:
> On Wed, Nov 22 2023 at 20:12, Yu Chien Peter Lin wrote:
> > Currently, the implementation of the RISC-V INTC driver uses the
> > interrupt cause as hwirq and has a limitation of supporting a
>
> s/hwirq/hardware interrupt/
>
> Please spell things out. We are not on Xitter here.
>
> > maximum of 64 hwirqs. However, according to the privileged spec,
> > interrupt causes >= 16 are defined for platform use.
> >
> > This limitation prevents us from fully utilizing the available
>
> This limitation prevents to fully utilize the ...
Okay, will fix.
Thanks,
Peter Lin
WARNING: multiple messages have this Message-ID (diff)
From: Yu-Chien Peter Lin <peterlin@andestech.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: mark.rutland@arm.com, irogers@google.com, heiko@sntech.de,
geert+renesas@glider.be, alexander.shishkin@linux.intel.com,
paul.walmsley@sifive.com, linux-kernel@vger.kernel.org,
conor.dooley@microchip.com, guoren@kernel.org,
krzysztof.kozlowski+dt@linaro.org,
linux-riscv@lists.infradead.org, will@kernel.org,
linux-renesas-soc@vger.kernel.org, tim609@andestech.com,
samuel@sholland.org, anup@brainfault.org, dminus@andestech.com,
magnus.damm@gmail.com, jernej.skrabec@gmail.com,
peterz@infradead.org, wens@csie.org, mingo@redhat.com,
linux-arm-kernel@lists.infradead.org, inochiama@outlook.com,
linux-sunxi@lists.linux.dev, ajones@ventanamicro.com,
devicetree@vger.kernel.org, conor+dt@kernel.org,
aou@eecs.berkeley.edu, andre.przywara@arm.com,
locus84@andestech.com, acme@kernel.org,
prabhakar.mahadev-lad.rj@bp.renesas.com, robh+dt@kernel.org,
atishp@atishpatra.org, namhyung@kernel.org, jszhang@kernel.org,
ycliang@andestech.com, n.shubin@yadro.com, rdunlap@infradead.org,
adrian.hunter@intel.com, conor@kernel.org,
linux-perf-users@vger.kernel.org, evan@rivosinc.com,
palmer@dabbelt.com, jolsa@kernel.org
Subject: Re: [PATCH v4 02/13] irqchip/riscv-intc: Allow large non-standard interrupt number
Date: Tue, 12 Dec 2023 18:17:41 +0800 [thread overview]
Message-ID: <ZXgzRZK8uqgmY84L@APC323> (raw)
In-Reply-To: <871qbwsn9h.ffs@tglx>
Hi Thomas,
On Fri, Dec 08, 2023 at 04:54:34PM +0100, Thomas Gleixner wrote:
> On Wed, Nov 22 2023 at 20:12, Yu Chien Peter Lin wrote:
> > Currently, the implementation of the RISC-V INTC driver uses the
> > interrupt cause as hwirq and has a limitation of supporting a
>
> s/hwirq/hardware interrupt/
>
> Please spell things out. We are not on Xitter here.
>
> > maximum of 64 hwirqs. However, according to the privileged spec,
> > interrupt causes >= 16 are defined for platform use.
> >
> > This limitation prevents us from fully utilizing the available
>
> This limitation prevents to fully utilize the ...
Okay, will fix.
Thanks,
Peter Lin
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Yu-Chien Peter Lin <peterlin@andestech.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: <acme@kernel.org>, <adrian.hunter@intel.com>,
<ajones@ventanamicro.com>, <alexander.shishkin@linux.intel.com>,
<andre.przywara@arm.com>, <anup@brainfault.org>,
<aou@eecs.berkeley.edu>, <atishp@atishpatra.org>,
<conor+dt@kernel.org>, <conor.dooley@microchip.com>,
<conor@kernel.org>, <devicetree@vger.kernel.org>,
<dminus@andestech.com>, <evan@rivosinc.com>,
<geert+renesas@glider.be>, <guoren@kernel.org>, <heiko@sntech.de>,
<irogers@google.com>, <jernej.skrabec@gmail.com>,
<jolsa@kernel.org>, <jszhang@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-perf-users@vger.kernel.org>,
<linux-renesas-soc@vger.kernel.org>,
<linux-riscv@lists.infradead.org>, <linux-sunxi@lists.linux.dev>,
<locus84@andestech.com>, <magnus.damm@gmail.com>,
<mark.rutland@arm.com>, <mingo@redhat.com>, <n.shubin@yadro.com>,
<namhyung@kernel.org>, <palmer@dabbelt.com>,
<paul.walmsley@sifive.com>, <peterz@infradead.org>,
<prabhakar.mahadev-lad.rj@bp.renesas.com>,
<rdunlap@infradead.org>, <robh+dt@kernel.org>,
<samuel@sholland.org>, <sunilvl@ventanamicro.com>,
<tim609@andestech.com>, <uwu@icenowy.me>, <wens@csie.org>,
<will@kernel.org>, <ycliang@andestech.com>,
<inochiama@outlook.com>
Subject: Re: [PATCH v4 02/13] irqchip/riscv-intc: Allow large non-standard interrupt number
Date: Tue, 12 Dec 2023 18:17:41 +0800 [thread overview]
Message-ID: <ZXgzRZK8uqgmY84L@APC323> (raw)
In-Reply-To: <871qbwsn9h.ffs@tglx>
Hi Thomas,
On Fri, Dec 08, 2023 at 04:54:34PM +0100, Thomas Gleixner wrote:
> On Wed, Nov 22 2023 at 20:12, Yu Chien Peter Lin wrote:
> > Currently, the implementation of the RISC-V INTC driver uses the
> > interrupt cause as hwirq and has a limitation of supporting a
>
> s/hwirq/hardware interrupt/
>
> Please spell things out. We are not on Xitter here.
>
> > maximum of 64 hwirqs. However, according to the privileged spec,
> > interrupt causes >= 16 are defined for platform use.
> >
> > This limitation prevents us from fully utilizing the available
>
> This limitation prevents to fully utilize the ...
Okay, will fix.
Thanks,
Peter Lin
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-12-12 10:20 UTC|newest]
Thread overview: 117+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-22 12:12 [PATCH v4 00/13] Support Andes PMU extension Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 01/13] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-24 14:57 ` Lad, Prabhakar
2023-11-24 14:57 ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 02/13] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-12-08 15:54 ` Thomas Gleixner
2023-12-08 15:54 ` Thomas Gleixner
2023-12-12 10:17 ` Yu-Chien Peter Lin [this message]
2023-12-12 10:17 ` Yu-Chien Peter Lin
2023-12-12 10:17 ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 03/13] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-12-08 16:01 ` Thomas Gleixner
2023-12-08 16:01 ` Thomas Gleixner
2023-12-12 10:28 ` Yu-Chien Peter Lin
2023-12-12 10:28 ` Yu-Chien Peter Lin
2023-12-12 10:28 ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-23 14:38 ` Conor Dooley
2023-11-23 14:38 ` Conor Dooley
2023-11-23 14:38 ` Conor Dooley
2023-11-24 15:03 ` Lad, Prabhakar
2023-11-24 15:03 ` Lad, Prabhakar
2023-11-24 15:05 ` Conor Dooley
2023-11-24 15:05 ` Conor Dooley
2023-11-29 6:43 ` Yu-Chien Peter Lin
2023-11-29 6:43 ` Yu-Chien Peter Lin
2023-11-29 6:43 ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 05/13] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-22 16:36 ` Geert Uytterhoeven
2023-11-22 16:36 ` Geert Uytterhoeven
2023-11-22 16:36 ` Geert Uytterhoeven
2023-11-24 15:04 ` Lad, Prabhakar
2023-11-24 15:04 ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 06/13] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 07/13] RISC-V: Move T-Head PMU to CPU feature alternative framework Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-22 21:16 ` Guo Ren
2023-11-22 21:16 ` Guo Ren
2023-11-22 21:16 ` Guo Ren
2023-11-23 14:45 ` Conor Dooley
2023-11-23 14:45 ` Conor Dooley
2023-11-23 14:45 ` Conor Dooley
2023-11-22 12:12 ` [PATCH v4 08/13] perf: RISC-V: Introduce Andes PMU for perf event sampling Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-24 15:06 ` Lad, Prabhakar
2023-11-24 15:06 ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 09/13] dt-bindings: riscv: Add T-Head PMU extension description Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-22 21:14 ` Guo Ren
2023-11-22 21:14 ` Guo Ren
2023-11-22 21:14 ` Guo Ren
2023-11-29 8:48 ` Yu-Chien Peter Lin
2023-11-29 8:48 ` Yu-Chien Peter Lin
2023-11-29 8:48 ` Yu-Chien Peter Lin
2023-11-30 8:29 ` Inochi Amaoto
2023-11-30 8:29 ` Inochi Amaoto
2023-11-30 9:21 ` Yu-Chien Peter Lin
2023-11-30 9:21 ` Yu-Chien Peter Lin
2023-11-30 9:21 ` Yu-Chien Peter Lin
2023-11-30 12:16 ` Inochi Amaoto
2023-11-30 12:16 ` Inochi Amaoto
2023-11-30 12:58 ` Conor Dooley
2023-11-30 12:58 ` Conor Dooley
2023-11-30 12:58 ` Conor Dooley
2023-11-30 23:11 ` Inochi Amaoto
2023-11-30 23:11 ` Inochi Amaoto
2023-12-01 0:40 ` Conor Dooley
2023-12-01 0:40 ` Conor Dooley
2023-12-01 0:40 ` Conor Dooley
2023-12-01 0:57 ` Inochi Amaoto
2023-12-01 0:57 ` Inochi Amaoto
2023-12-01 1:14 ` Inochi Amaoto
2023-12-01 1:14 ` Inochi Amaoto
2023-12-06 3:14 ` Yu-Chien Peter Lin
2023-12-06 3:14 ` Yu-Chien Peter Lin
2023-12-06 3:14 ` Yu-Chien Peter Lin
2023-11-23 14:48 ` Conor Dooley
2023-11-23 14:48 ` Conor Dooley
2023-11-23 14:48 ` Conor Dooley
2023-11-29 8:47 ` Yu-Chien Peter Lin
2023-11-29 8:47 ` Yu-Chien Peter Lin
2023-11-29 8:47 ` Yu-Chien Peter Lin
2023-11-29 12:33 ` Conor Dooley
2023-11-29 12:33 ` Conor Dooley
2023-11-29 12:33 ` Conor Dooley
2023-11-22 12:12 ` [PATCH v4 10/13] dt-bindings: riscv: Add Andes " Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-24 15:07 ` Lad, Prabhakar
2023-11-24 15:07 ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 11/13] riscv: dts: allwinner: Add T-Head PMU extension Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-22 21:12 ` Guo Ren
2023-11-22 21:12 ` Guo Ren
2023-11-22 21:12 ` Guo Ren
2023-11-23 14:58 ` Conor Dooley
2023-11-23 14:58 ` Conor Dooley
2023-11-23 14:58 ` Conor Dooley
2023-11-29 9:34 ` Yu-Chien Peter Lin
2023-11-29 9:34 ` Yu-Chien Peter Lin
2023-11-29 9:34 ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 12/13] riscv: dts: renesas: Add Andes " Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-22 16:34 ` Geert Uytterhoeven
2023-11-22 16:34 ` Geert Uytterhoeven
2023-11-24 15:07 ` Lad, Prabhakar
2023-11-24 15:07 ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 13/13] riscv: andes: Support symbolic FW and HW raw events Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-24 15:08 ` Lad, Prabhakar
2023-11-24 15:08 ` Lad, Prabhakar
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