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From: Yu-Chien Peter Lin <peterlin@andestech.com>
To: Guo Ren <guoren@kernel.org>
Cc: <acme@kernel.org>, <adrian.hunter@intel.com>,
	<ajones@ventanamicro.com>, <alexander.shishkin@linux.intel.com>,
	<andre.przywara@arm.com>, <anup@brainfault.org>,
	<aou@eecs.berkeley.edu>, <atishp@atishpatra.org>,
	<conor+dt@kernel.org>, <conor.dooley@microchip.com>,
	<conor@kernel.org>, <devicetree@vger.kernel.org>,
	<dminus@andestech.com>, <evan@rivosinc.com>,
	<geert+renesas@glider.be>, <heiko@sntech.de>,
	<irogers@google.com>, <jernej.skrabec@gmail.com>,
	<jolsa@kernel.org>, <jszhang@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-perf-users@vger.kernel.org>,
	<linux-renesas-soc@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <linux-sunxi@lists.linux.dev>,
	<locus84@andestech.com>, <magnus.damm@gmail.com>,
	<mark.rutland@arm.com>, <mingo@redhat.com>, <n.shubin@yadro.com>,
	<namhyung@kernel.org>, <palmer@dabbelt.com>,
	<paul.walmsley@sifive.com>, <peterz@infradead.org>,
	<prabhakar.mahadev-lad.rj@bp.renesas.com>,
	<rdunlap@infradead.org>, <robh+dt@kernel.org>,
	<samuel@sholland.org>, <sunilvl@ventanamicro.com>,
	<tglx@linutronix.de>, <tim609@andestech.com>, <uwu@icenowy.me>,
	<wens@csie.org>, <will@kernel.org>, <ycliang@andestech.com>,
	<inochiama@outlook.com>
Subject: Re: [PATCH v4 09/13] dt-bindings: riscv: Add T-Head PMU extension description
Date: Wed, 29 Nov 2023 16:48:56 +0800	[thread overview]
Message-ID: <ZWb6-LEkyh5RRpcP@APC323> (raw)
In-Reply-To: <CAJF2gTSMe-yfzKfX92eWhBnJ_WwoYQu7_7fsOQuNqXdafHA1dg@mail.gmail.com>

Hi Guo Ren,

On Thu, Nov 23, 2023 at 05:14:30AM +0800, Guo Ren wrote:
> On Wed, Nov 22, 2023 at 8:17 PM Yu Chien Peter Lin
> <peterlin@andestech.com> wrote:
> >
> > Document the ISA string for T-Head performance monitor extension
> > which provides counter overflow interrupt mechanism.
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > ---
> > Changes v2 -> v3:
> >   - New patch
> > Changes v3 -> v4:
> >   - No change
> > ---
> >  Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > index c91ab0e46648..694efaea8fce 100644
> > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > @@ -258,5 +258,11 @@ properties:
> >              in commit 2e5236 ("Ztso is now ratified.") of the
> >              riscv-isa-manual.
> >
> > +        - const: xtheadpmu
> > +          description:
> > +            The T-Head performance monitor extension for counter overflow. For more
> > +            details, see the chapter 12 in the Xuantie C906 user manual.
> > +            https://github.com/T-head-Semi/openc906/tree/main/doc
> > +
> >  additionalProperties: true
> >  ...
> > --
> > 2.34.1
> >
> Reviewed-by: Guo Ren <guoren@kernel.org>

Thanks for the review.
Would you share document about T-Head PMU?

Best regards,
Peter Lin

> -- 
> Best Regards
>  Guo Ren

WARNING: multiple messages have this Message-ID (diff)
From: Yu-Chien Peter Lin <peterlin@andestech.com>
To: Guo Ren <guoren@kernel.org>
Cc: mark.rutland@arm.com, irogers@google.com, heiko@sntech.de,
	geert+renesas@glider.be, alexander.shishkin@linux.intel.com,
	paul.walmsley@sifive.com, linux-kernel@vger.kernel.org,
	conor.dooley@microchip.com, krzysztof.kozlowski+dt@linaro.org,
	linux-riscv@lists.infradead.org, will@kernel.org,
	linux-renesas-soc@vger.kernel.org, tim609@andestech.com,
	samuel@sholland.org, anup@brainfault.org, dminus@andestech.com,
	magnus.damm@gmail.com, jernej.skrabec@gmail.com,
	peterz@infradead.org, wens@csie.org, mingo@redhat.com,
	jszhang@kernel.org, inochiama@outlook.com,
	linux-sunxi@lists.linux.dev, ajones@ventanamicro.com,
	devicetree@vger.kernel.org, conor+dt@kernel.org,
	aou@eecs.berkeley.edu, andre.przywara@arm.com,
	locus84@andestech.com, acme@kernel.org,
	prabhakar.mahadev-lad.rj@bp.renesas.com, robh+dt@kernel.org,
	atishp@atishpatra.org, namhyung@kernel.org, tglx@linutronix.de,
	linux-arm-kernel@lists.infradead.org, ycliang@andestech.com,
	n.shubin@yadro.com, rdunlap@infradead.org,
	adrian.hunter@intel.com, conor@kernel.org,
	linux-perf-users@vger.kernel.org, evan@rivosinc.com,
	palmer@dabbelt.com, jolsa@kernel.org
Subject: Re: [PATCH v4 09/13] dt-bindings: riscv: Add T-Head PMU extension description
Date: Wed, 29 Nov 2023 16:48:56 +0800	[thread overview]
Message-ID: <ZWb6-LEkyh5RRpcP@APC323> (raw)
In-Reply-To: <CAJF2gTSMe-yfzKfX92eWhBnJ_WwoYQu7_7fsOQuNqXdafHA1dg@mail.gmail.com>

Hi Guo Ren,

On Thu, Nov 23, 2023 at 05:14:30AM +0800, Guo Ren wrote:
> On Wed, Nov 22, 2023 at 8:17 PM Yu Chien Peter Lin
> <peterlin@andestech.com> wrote:
> >
> > Document the ISA string for T-Head performance monitor extension
> > which provides counter overflow interrupt mechanism.
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > ---
> > Changes v2 -> v3:
> >   - New patch
> > Changes v3 -> v4:
> >   - No change
> > ---
> >  Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > index c91ab0e46648..694efaea8fce 100644
> > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > @@ -258,5 +258,11 @@ properties:
> >              in commit 2e5236 ("Ztso is now ratified.") of the
> >              riscv-isa-manual.
> >
> > +        - const: xtheadpmu
> > +          description:
> > +            The T-Head performance monitor extension for counter overflow. For more
> > +            details, see the chapter 12 in the Xuantie C906 user manual.
> > +            https://github.com/T-head-Semi/openc906/tree/main/doc
> > +
> >  additionalProperties: true
> >  ...
> > --
> > 2.34.1
> >
> Reviewed-by: Guo Ren <guoren@kernel.org>

Thanks for the review.
Would you share document about T-Head PMU?

Best regards,
Peter Lin

> -- 
> Best Regards
>  Guo Ren

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Yu-Chien Peter Lin <peterlin@andestech.com>
To: Guo Ren <guoren@kernel.org>
Cc: <acme@kernel.org>, <adrian.hunter@intel.com>,
	<ajones@ventanamicro.com>, <alexander.shishkin@linux.intel.com>,
	<andre.przywara@arm.com>, <anup@brainfault.org>,
	<aou@eecs.berkeley.edu>, <atishp@atishpatra.org>,
	<conor+dt@kernel.org>, <conor.dooley@microchip.com>,
	<conor@kernel.org>, <devicetree@vger.kernel.org>,
	<dminus@andestech.com>, <evan@rivosinc.com>,
	<geert+renesas@glider.be>, <heiko@sntech.de>,
	<irogers@google.com>, <jernej.skrabec@gmail.com>,
	<jolsa@kernel.org>, <jszhang@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-perf-users@vger.kernel.org>,
	<linux-renesas-soc@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <linux-sunxi@lists.linux.dev>,
	<locus84@andestech.com>, <magnus.damm@gmail.com>,
	<mark.rutland@arm.com>, <mingo@redhat.com>, <n.shubin@yadro.com>,
	<namhyung@kernel.org>, <palmer@dabbelt.com>,
	<paul.walmsley@sifive.com>, <peterz@infradead.org>,
	<prabhakar.mahadev-lad.rj@bp.renesas.com>,
	<rdunlap@infradead.org>, <robh+dt@kernel.org>,
	<samuel@sholland.org>, <sunilvl@ventanamicro.com>,
	<tglx@linutronix.de>, <tim609@andestech.com>, <uwu@icenowy.me>,
	<wens@csie.org>, <will@kernel.org>, <ycliang@andestech.com>,
	<inochiama@outlook.com>
Subject: Re: [PATCH v4 09/13] dt-bindings: riscv: Add T-Head PMU extension description
Date: Wed, 29 Nov 2023 16:48:56 +0800	[thread overview]
Message-ID: <ZWb6-LEkyh5RRpcP@APC323> (raw)
In-Reply-To: <CAJF2gTSMe-yfzKfX92eWhBnJ_WwoYQu7_7fsOQuNqXdafHA1dg@mail.gmail.com>

Hi Guo Ren,

On Thu, Nov 23, 2023 at 05:14:30AM +0800, Guo Ren wrote:
> On Wed, Nov 22, 2023 at 8:17 PM Yu Chien Peter Lin
> <peterlin@andestech.com> wrote:
> >
> > Document the ISA string for T-Head performance monitor extension
> > which provides counter overflow interrupt mechanism.
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > ---
> > Changes v2 -> v3:
> >   - New patch
> > Changes v3 -> v4:
> >   - No change
> > ---
> >  Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > index c91ab0e46648..694efaea8fce 100644
> > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > @@ -258,5 +258,11 @@ properties:
> >              in commit 2e5236 ("Ztso is now ratified.") of the
> >              riscv-isa-manual.
> >
> > +        - const: xtheadpmu
> > +          description:
> > +            The T-Head performance monitor extension for counter overflow. For more
> > +            details, see the chapter 12 in the Xuantie C906 user manual.
> > +            https://github.com/T-head-Semi/openc906/tree/main/doc
> > +
> >  additionalProperties: true
> >  ...
> > --
> > 2.34.1
> >
> Reviewed-by: Guo Ren <guoren@kernel.org>

Thanks for the review.
Would you share document about T-Head PMU?

Best regards,
Peter Lin

> -- 
> Best Regards
>  Guo Ren

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2023-11-29  8:50 UTC|newest]

Thread overview: 117+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-22 12:12 [PATCH v4 00/13] Support Andes PMU extension Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 01/13] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-11-24 14:57   ` Lad, Prabhakar
2023-11-24 14:57     ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 02/13] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-12-08 15:54   ` Thomas Gleixner
2023-12-08 15:54     ` Thomas Gleixner
2023-12-12 10:17     ` Yu-Chien Peter Lin
2023-12-12 10:17       ` Yu-Chien Peter Lin
2023-12-12 10:17       ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 03/13] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-12-08 16:01   ` Thomas Gleixner
2023-12-08 16:01     ` Thomas Gleixner
2023-12-12 10:28     ` Yu-Chien Peter Lin
2023-12-12 10:28       ` Yu-Chien Peter Lin
2023-12-12 10:28       ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-11-23 14:38   ` Conor Dooley
2023-11-23 14:38     ` Conor Dooley
2023-11-23 14:38     ` Conor Dooley
2023-11-24 15:03   ` Lad, Prabhakar
2023-11-24 15:03     ` Lad, Prabhakar
2023-11-24 15:05     ` Conor Dooley
2023-11-24 15:05       ` Conor Dooley
2023-11-29  6:43     ` Yu-Chien Peter Lin
2023-11-29  6:43       ` Yu-Chien Peter Lin
2023-11-29  6:43       ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 05/13] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-11-22 16:36   ` Geert Uytterhoeven
2023-11-22 16:36     ` Geert Uytterhoeven
2023-11-22 16:36     ` Geert Uytterhoeven
2023-11-24 15:04   ` Lad, Prabhakar
2023-11-24 15:04     ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 06/13] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 07/13] RISC-V: Move T-Head PMU to CPU feature alternative framework Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-11-22 21:16   ` Guo Ren
2023-11-22 21:16     ` Guo Ren
2023-11-22 21:16     ` Guo Ren
2023-11-23 14:45   ` Conor Dooley
2023-11-23 14:45     ` Conor Dooley
2023-11-23 14:45     ` Conor Dooley
2023-11-22 12:12 ` [PATCH v4 08/13] perf: RISC-V: Introduce Andes PMU for perf event sampling Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-11-24 15:06   ` Lad, Prabhakar
2023-11-24 15:06     ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 09/13] dt-bindings: riscv: Add T-Head PMU extension description Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-11-22 21:14   ` Guo Ren
2023-11-22 21:14     ` Guo Ren
2023-11-22 21:14     ` Guo Ren
2023-11-29  8:48     ` Yu-Chien Peter Lin [this message]
2023-11-29  8:48       ` Yu-Chien Peter Lin
2023-11-29  8:48       ` Yu-Chien Peter Lin
2023-11-30  8:29       ` Inochi Amaoto
2023-11-30  8:29         ` Inochi Amaoto
2023-11-30  9:21         ` Yu-Chien Peter Lin
2023-11-30  9:21           ` Yu-Chien Peter Lin
2023-11-30  9:21           ` Yu-Chien Peter Lin
2023-11-30 12:16           ` Inochi Amaoto
2023-11-30 12:16             ` Inochi Amaoto
2023-11-30 12:58             ` Conor Dooley
2023-11-30 12:58               ` Conor Dooley
2023-11-30 12:58               ` Conor Dooley
2023-11-30 23:11               ` Inochi Amaoto
2023-11-30 23:11                 ` Inochi Amaoto
2023-12-01  0:40                 ` Conor Dooley
2023-12-01  0:40                   ` Conor Dooley
2023-12-01  0:40                   ` Conor Dooley
2023-12-01  0:57                   ` Inochi Amaoto
2023-12-01  0:57                     ` Inochi Amaoto
2023-12-01  1:14           ` Inochi Amaoto
2023-12-01  1:14             ` Inochi Amaoto
2023-12-06  3:14             ` Yu-Chien Peter Lin
2023-12-06  3:14               ` Yu-Chien Peter Lin
2023-12-06  3:14               ` Yu-Chien Peter Lin
2023-11-23 14:48   ` Conor Dooley
2023-11-23 14:48     ` Conor Dooley
2023-11-23 14:48     ` Conor Dooley
2023-11-29  8:47     ` Yu-Chien Peter Lin
2023-11-29  8:47       ` Yu-Chien Peter Lin
2023-11-29  8:47       ` Yu-Chien Peter Lin
2023-11-29 12:33       ` Conor Dooley
2023-11-29 12:33         ` Conor Dooley
2023-11-29 12:33         ` Conor Dooley
2023-11-22 12:12 ` [PATCH v4 10/13] dt-bindings: riscv: Add Andes " Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-11-24 15:07   ` Lad, Prabhakar
2023-11-24 15:07     ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 11/13] riscv: dts: allwinner: Add T-Head PMU extension Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-11-22 21:12   ` Guo Ren
2023-11-22 21:12     ` Guo Ren
2023-11-22 21:12     ` Guo Ren
2023-11-23 14:58   ` Conor Dooley
2023-11-23 14:58     ` Conor Dooley
2023-11-23 14:58     ` Conor Dooley
2023-11-29  9:34     ` Yu-Chien Peter Lin
2023-11-29  9:34       ` Yu-Chien Peter Lin
2023-11-29  9:34       ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 12/13] riscv: dts: renesas: Add Andes " Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-11-22 16:34   ` Geert Uytterhoeven
2023-11-22 16:34     ` Geert Uytterhoeven
2023-11-24 15:07   ` Lad, Prabhakar
2023-11-24 15:07     ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 13/13] riscv: andes: Support symbolic FW and HW raw events Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-11-24 15:08   ` Lad, Prabhakar
2023-11-24 15:08     ` Lad, Prabhakar

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