From: "Alex Bennée" <alex.bennee@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org,
Liviu Ionescu <ilg@livius.net>
Subject: Re: [PATCH 09/10] armv7m: FAULTMASK should be 0 on reset
Date: Fri, 27 Jan 2017 13:56:59 +0000 [thread overview]
Message-ID: <871svoa9n8.fsf@linaro.org> (raw)
In-Reply-To: <1485285380-10565-10-git-send-email-peter.maydell@linaro.org>
Peter Maydell <peter.maydell@linaro.org> writes:
> From: Michael Davidsaver <mdavidsaver@gmail.com>
>
> For M profile CPUs, FAULTMASK should be 0 on reset, like PRIMASK.
> QEMU stores FAULTMASK in the PSTATE F bit, so (as with PRIMASK in the
> I bit) we have to clear these to undo the A profile default of 1.
>
> Update the comment accordingly and move it so that it's closer to the
> code it's referring to.
>
> Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
> [PMM: rewrote commit message, moved comments]
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> target/arm/cpu.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index c804f59..0814f73 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -179,15 +179,16 @@ static void arm_cpu_reset(CPUState *s)
> /* SVC mode with interrupts disabled. */
> env->uncached_cpsr = ARM_CPU_MODE_SVC;
> env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
> - /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
> - * clear at reset. Initial SP and PC are loaded from ROM.
> - */
> +
> if (arm_feature(env, ARM_FEATURE_M)) {
> uint32_t initial_msp; /* Loaded from 0x0 */
> uint32_t initial_pc; /* Loaded from 0x4 */
> uint8_t *rom;
>
> - env->daif &= ~PSTATE_I;
> + /* For M profile we store FAULTMASK and PRIMASK in the
> + * PSTATE F and I bits; these are both clear at reset.
> + */
> + env->daif &= ~(PSTATE_I | PSTATE_F);
>
> /* The reset value of this bit is IMPDEF, but ARM recommends
> * that it resets to 1, so QEMU always does that rather than making
> @@ -195,6 +196,7 @@ static void arm_cpu_reset(CPUState *s)
> */
> env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK;
>
> + /* Load the initial SP and PC from the vector table at address 0 */
> rom = rom_ptr(0);
> if (rom) {
> /* Address zero is covered by ROM which hasn't yet been
--
Alex Bennée
WARNING: multiple messages have this Message-ID (diff)
From: "Alex Bennée" <alex.bennee@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org,
Liviu Ionescu <ilg@livius.net>
Subject: Re: [Qemu-devel] [PATCH 09/10] armv7m: FAULTMASK should be 0 on reset
Date: Fri, 27 Jan 2017 13:56:59 +0000 [thread overview]
Message-ID: <871svoa9n8.fsf@linaro.org> (raw)
In-Reply-To: <1485285380-10565-10-git-send-email-peter.maydell@linaro.org>
Peter Maydell <peter.maydell@linaro.org> writes:
> From: Michael Davidsaver <mdavidsaver@gmail.com>
>
> For M profile CPUs, FAULTMASK should be 0 on reset, like PRIMASK.
> QEMU stores FAULTMASK in the PSTATE F bit, so (as with PRIMASK in the
> I bit) we have to clear these to undo the A profile default of 1.
>
> Update the comment accordingly and move it so that it's closer to the
> code it's referring to.
>
> Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
> [PMM: rewrote commit message, moved comments]
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> target/arm/cpu.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index c804f59..0814f73 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -179,15 +179,16 @@ static void arm_cpu_reset(CPUState *s)
> /* SVC mode with interrupts disabled. */
> env->uncached_cpsr = ARM_CPU_MODE_SVC;
> env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
> - /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
> - * clear at reset. Initial SP and PC are loaded from ROM.
> - */
> +
> if (arm_feature(env, ARM_FEATURE_M)) {
> uint32_t initial_msp; /* Loaded from 0x0 */
> uint32_t initial_pc; /* Loaded from 0x4 */
> uint8_t *rom;
>
> - env->daif &= ~PSTATE_I;
> + /* For M profile we store FAULTMASK and PRIMASK in the
> + * PSTATE F and I bits; these are both clear at reset.
> + */
> + env->daif &= ~(PSTATE_I | PSTATE_F);
>
> /* The reset value of this bit is IMPDEF, but ARM recommends
> * that it resets to 1, so QEMU always does that rather than making
> @@ -195,6 +196,7 @@ static void arm_cpu_reset(CPUState *s)
> */
> env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK;
>
> + /* Load the initial SP and PC from the vector table at address 0 */
> rom = rom_ptr(0);
> if (rom) {
> /* Address zero is covered by ROM which hasn't yet been
--
Alex Bennée
next prev parent reply other threads:[~2017-01-27 13:56 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-24 19:16 [PATCH 00/10] More M profile bugfixes Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-24 19:16 ` [PATCH 01/10] target/arm: Drop IS_M() macro Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 12:33 ` Alex Bennée
2017-01-27 12:33 ` [Qemu-devel] " Alex Bennée
2017-01-24 19:16 ` [PATCH 02/10] armv7m_nvic: keep a pointer to the CPU Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 12:41 ` Alex Bennée
2017-01-27 12:41 ` [Qemu-devel] " Alex Bennée
2017-01-27 13:16 ` Peter Maydell
2017-01-27 13:16 ` [Qemu-devel] " Peter Maydell
2017-01-24 19:16 ` [PATCH 03/10] armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 12:28 ` Alex Bennée
2017-01-27 12:28 ` [Qemu-devel] " Alex Bennée
2017-01-27 13:14 ` Peter Maydell
2017-01-27 13:14 ` [Qemu-devel] " Peter Maydell
2017-01-24 19:16 ` [PATCH 04/10] armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFAR Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 13:43 ` Alex Bennée
2017-01-27 13:43 ` [Qemu-devel] " Alex Bennée
2017-01-24 19:16 ` [PATCH 05/10] armv7m: honour CCR.STACKALIGN on exception entry Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-24 19:33 ` Richard Henderson
2017-01-24 19:45 ` Peter Maydell
2017-01-24 19:16 ` [PATCH 06/10] armv7m: set CFSR.UNDEFINSTR on undefined instructions Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 13:44 ` Alex Bennée
2017-01-27 13:44 ` [Qemu-devel] " Alex Bennée
2017-01-24 19:16 ` [PATCH 07/10] armv7m: Report no-coprocessor faults correctly Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 13:53 ` Alex Bennée
2017-01-27 13:53 ` [Qemu-devel] " Alex Bennée
2017-01-24 19:16 ` [PATCH 08/10] armv7m: Honour CCR.USERSETMPEND Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 13:55 ` Alex Bennée
2017-01-27 13:55 ` [Qemu-devel] " Alex Bennée
2017-01-24 19:16 ` [PATCH 09/10] armv7m: FAULTMASK should be 0 on reset Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 13:56 ` Alex Bennée [this message]
2017-01-27 13:56 ` Alex Bennée
2017-01-24 19:16 ` [PATCH 10/10] armv7m: R14 should reset to 0xffffffff Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 13:58 ` Alex Bennée
2017-01-27 13:58 ` [Qemu-devel] " Alex Bennée
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=871svoa9n8.fsf@linaro.org \
--to=alex.bennee@linaro.org \
--cc=ilg@livius.net \
--cc=patches@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.