From: "Alex Bennée" <alex.bennee@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org,
Liviu Ionescu <ilg@livius.net>
Subject: Re: [PATCH 06/10] armv7m: set CFSR.UNDEFINSTR on undefined instructions
Date: Fri, 27 Jan 2017 13:44:12 +0000 [thread overview]
Message-ID: <8760l0aa8j.fsf@linaro.org> (raw)
In-Reply-To: <1485285380-10565-7-git-send-email-peter.maydell@linaro.org>
Peter Maydell <peter.maydell@linaro.org> writes:
> From: Michael Davidsaver <mdavidsaver@gmail.com>
>
> When we take an exception for an undefined instruction, set the
> appropriate CFSR bit.
>
> Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
> [PMM: tweaked commit message, comment]
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> target/arm/helper.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 7dc30f5..e6b1c36 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -6072,6 +6072,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
> switch (cs->exception_index) {
> case EXCP_UDEF:
> armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
> + env->v7m.cfsr |= R_V7M_CFSR_UNDEFINSTR_MASK;
> return;
> case EXCP_SWI:
> /* The PC already points to the next instruction. */
--
Alex Bennée
WARNING: multiple messages have this Message-ID (diff)
From: "Alex Bennée" <alex.bennee@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org,
Liviu Ionescu <ilg@livius.net>
Subject: Re: [Qemu-devel] [PATCH 06/10] armv7m: set CFSR.UNDEFINSTR on undefined instructions
Date: Fri, 27 Jan 2017 13:44:12 +0000 [thread overview]
Message-ID: <8760l0aa8j.fsf@linaro.org> (raw)
In-Reply-To: <1485285380-10565-7-git-send-email-peter.maydell@linaro.org>
Peter Maydell <peter.maydell@linaro.org> writes:
> From: Michael Davidsaver <mdavidsaver@gmail.com>
>
> When we take an exception for an undefined instruction, set the
> appropriate CFSR bit.
>
> Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
> [PMM: tweaked commit message, comment]
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> target/arm/helper.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 7dc30f5..e6b1c36 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -6072,6 +6072,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
> switch (cs->exception_index) {
> case EXCP_UDEF:
> armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
> + env->v7m.cfsr |= R_V7M_CFSR_UNDEFINSTR_MASK;
> return;
> case EXCP_SWI:
> /* The PC already points to the next instruction. */
--
Alex Bennée
next prev parent reply other threads:[~2017-01-27 13:44 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-24 19:16 [PATCH 00/10] More M profile bugfixes Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-24 19:16 ` [PATCH 01/10] target/arm: Drop IS_M() macro Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 12:33 ` Alex Bennée
2017-01-27 12:33 ` [Qemu-devel] " Alex Bennée
2017-01-24 19:16 ` [PATCH 02/10] armv7m_nvic: keep a pointer to the CPU Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 12:41 ` Alex Bennée
2017-01-27 12:41 ` [Qemu-devel] " Alex Bennée
2017-01-27 13:16 ` Peter Maydell
2017-01-27 13:16 ` [Qemu-devel] " Peter Maydell
2017-01-24 19:16 ` [PATCH 03/10] armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 12:28 ` Alex Bennée
2017-01-27 12:28 ` [Qemu-devel] " Alex Bennée
2017-01-27 13:14 ` Peter Maydell
2017-01-27 13:14 ` [Qemu-devel] " Peter Maydell
2017-01-24 19:16 ` [PATCH 04/10] armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFAR Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 13:43 ` Alex Bennée
2017-01-27 13:43 ` [Qemu-devel] " Alex Bennée
2017-01-24 19:16 ` [PATCH 05/10] armv7m: honour CCR.STACKALIGN on exception entry Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-24 19:33 ` Richard Henderson
2017-01-24 19:45 ` Peter Maydell
2017-01-24 19:16 ` [PATCH 06/10] armv7m: set CFSR.UNDEFINSTR on undefined instructions Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 13:44 ` Alex Bennée [this message]
2017-01-27 13:44 ` Alex Bennée
2017-01-24 19:16 ` [PATCH 07/10] armv7m: Report no-coprocessor faults correctly Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 13:53 ` Alex Bennée
2017-01-27 13:53 ` [Qemu-devel] " Alex Bennée
2017-01-24 19:16 ` [PATCH 08/10] armv7m: Honour CCR.USERSETMPEND Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 13:55 ` Alex Bennée
2017-01-27 13:55 ` [Qemu-devel] " Alex Bennée
2017-01-24 19:16 ` [PATCH 09/10] armv7m: FAULTMASK should be 0 on reset Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 13:56 ` Alex Bennée
2017-01-27 13:56 ` [Qemu-devel] " Alex Bennée
2017-01-24 19:16 ` [PATCH 10/10] armv7m: R14 should reset to 0xffffffff Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 13:58 ` Alex Bennée
2017-01-27 13:58 ` [Qemu-devel] " Alex Bennée
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