From: "Alex Bennée" <alex.bennee@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org,
Liviu Ionescu <ilg@livius.net>
Subject: Re: [PATCH 10/10] armv7m: R14 should reset to 0xffffffff
Date: Fri, 27 Jan 2017 13:58:01 +0000 [thread overview]
Message-ID: <87ziic8v12.fsf@linaro.org> (raw)
In-Reply-To: <1485285380-10565-11-git-send-email-peter.maydell@linaro.org>
Peter Maydell <peter.maydell@linaro.org> writes:
> For M profile (unlike A profile) the reset value of R14 is specified
> as 0xffffffff. (The rationale is that this is an illegal exception
> return value, so if guest code tries to return to it it will result
> in a helpful exception.)
>
> Registers r0 to r12 and the flags are architecturally UNKNOWN on
> reset, so we leave those at zero.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> target/arm/cpu.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 0814f73..e9f10f7 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -196,6 +196,9 @@ static void arm_cpu_reset(CPUState *s)
> */
> env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK;
>
> + /* Unlike A/R profile, M profile defines the reset LR value */
> + env->regs[14] = 0xffffffff;
> +
> /* Load the initial SP and PC from the vector table at address 0 */
> rom = rom_ptr(0);
> if (rom) {
--
Alex Bennée
WARNING: multiple messages have this Message-ID (diff)
From: "Alex Bennée" <alex.bennee@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org,
Liviu Ionescu <ilg@livius.net>
Subject: Re: [Qemu-devel] [PATCH 10/10] armv7m: R14 should reset to 0xffffffff
Date: Fri, 27 Jan 2017 13:58:01 +0000 [thread overview]
Message-ID: <87ziic8v12.fsf@linaro.org> (raw)
In-Reply-To: <1485285380-10565-11-git-send-email-peter.maydell@linaro.org>
Peter Maydell <peter.maydell@linaro.org> writes:
> For M profile (unlike A profile) the reset value of R14 is specified
> as 0xffffffff. (The rationale is that this is an illegal exception
> return value, so if guest code tries to return to it it will result
> in a helpful exception.)
>
> Registers r0 to r12 and the flags are architecturally UNKNOWN on
> reset, so we leave those at zero.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> target/arm/cpu.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 0814f73..e9f10f7 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -196,6 +196,9 @@ static void arm_cpu_reset(CPUState *s)
> */
> env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK;
>
> + /* Unlike A/R profile, M profile defines the reset LR value */
> + env->regs[14] = 0xffffffff;
> +
> /* Load the initial SP and PC from the vector table at address 0 */
> rom = rom_ptr(0);
> if (rom) {
--
Alex Bennée
next prev parent reply other threads:[~2017-01-27 13:58 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-24 19:16 [PATCH 00/10] More M profile bugfixes Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-24 19:16 ` [PATCH 01/10] target/arm: Drop IS_M() macro Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 12:33 ` Alex Bennée
2017-01-27 12:33 ` [Qemu-devel] " Alex Bennée
2017-01-24 19:16 ` [PATCH 02/10] armv7m_nvic: keep a pointer to the CPU Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 12:41 ` Alex Bennée
2017-01-27 12:41 ` [Qemu-devel] " Alex Bennée
2017-01-27 13:16 ` Peter Maydell
2017-01-27 13:16 ` [Qemu-devel] " Peter Maydell
2017-01-24 19:16 ` [PATCH 03/10] armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 12:28 ` Alex Bennée
2017-01-27 12:28 ` [Qemu-devel] " Alex Bennée
2017-01-27 13:14 ` Peter Maydell
2017-01-27 13:14 ` [Qemu-devel] " Peter Maydell
2017-01-24 19:16 ` [PATCH 04/10] armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFAR Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 13:43 ` Alex Bennée
2017-01-27 13:43 ` [Qemu-devel] " Alex Bennée
2017-01-24 19:16 ` [PATCH 05/10] armv7m: honour CCR.STACKALIGN on exception entry Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-24 19:33 ` Richard Henderson
2017-01-24 19:45 ` Peter Maydell
2017-01-24 19:16 ` [PATCH 06/10] armv7m: set CFSR.UNDEFINSTR on undefined instructions Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 13:44 ` Alex Bennée
2017-01-27 13:44 ` [Qemu-devel] " Alex Bennée
2017-01-24 19:16 ` [PATCH 07/10] armv7m: Report no-coprocessor faults correctly Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 13:53 ` Alex Bennée
2017-01-27 13:53 ` [Qemu-devel] " Alex Bennée
2017-01-24 19:16 ` [PATCH 08/10] armv7m: Honour CCR.USERSETMPEND Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 13:55 ` Alex Bennée
2017-01-27 13:55 ` [Qemu-devel] " Alex Bennée
2017-01-24 19:16 ` [PATCH 09/10] armv7m: FAULTMASK should be 0 on reset Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 13:56 ` Alex Bennée
2017-01-27 13:56 ` [Qemu-devel] " Alex Bennée
2017-01-24 19:16 ` [PATCH 10/10] armv7m: R14 should reset to 0xffffffff Peter Maydell
2017-01-24 19:16 ` [Qemu-devel] " Peter Maydell
2017-01-27 13:58 ` Alex Bennée [this message]
2017-01-27 13:58 ` Alex Bennée
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