From: "Alex Bennée" <alex.bennee@linaro.org>
To: Pranith Kumar <bobby.prani@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
"open list\:ARM" <qemu-arm@nongnu.org>,
"open list\:All patches CC here" <qemu-devel@nongnu.org>,
serge.fdrv@gmail.com, rth@twiddle.net
Subject: Re: [RFC v3 PATCH 13/14] aarch64: Generate fences for aarch64
Date: Fri, 24 Jun 2016 17:17:18 +0100 [thread overview]
Message-ID: <87h9cizhm9.fsf@linaro.org> (raw)
In-Reply-To: <20160618040343.19517-14-bobby.prani@gmail.com>
Pranith Kumar <bobby.prani@gmail.com> writes:
> Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
> ---
> target-arm/translate-a64.c | 18 +++++++++++++-----
> 1 file changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
> index ce8141a..fa24bf2 100644
> --- a/target-arm/translate-a64.c
> +++ b/target-arm/translate-a64.c
> @@ -1250,7 +1250,7 @@ static void handle_sync(DisasContext *s, uint32_t insn,
> return;
> case 4: /* DSB */
> case 5: /* DMB */
> - /* We don't emulate caches so barriers are no-ops */
> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
> return;
> case 6: /* ISB */
> /* We need to break the TB after this insn to execute
> @@ -1855,23 +1855,31 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
> }
> tcg_addr = read_cpu_reg_sp(s, rn, 1);
>
> - /* Note that since TCG is single threaded load-acquire/store-release
> - * semantics require no extra if (is_lasr) { ... } handling.
> - */
> -
> if (is_excl) {
> if (!is_store) {
> s->is_ldex = true;
> gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair);
> + if (is_lasr) {
> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_ACQ);
> + }
> } else {
> + if (is_lasr) {
> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_REL);
> + }
> gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair);
> }
> } else {
> TCGv_i64 tcg_rt = cpu_reg(s, rt);
> if (is_store) {
> + if (is_lasr) {
> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_REL);
> + }
> do_gpr_st(s, tcg_rt, tcg_addr, size);
> } else {
> do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false);
> + if (is_lasr) {
> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_ACQ);
> + }
See the private email I sent you with the litmus tests. I think you'll
need to confirm this is working as expected.
> }
> }
> }
--
Alex Bennée
WARNING: multiple messages have this Message-ID (diff)
From: "Alex Bennée" <alex.bennee@linaro.org>
To: Pranith Kumar <bobby.prani@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
"open list:ARM" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>,
serge.fdrv@gmail.com, rth@twiddle.net
Subject: Re: [Qemu-devel] [RFC v3 PATCH 13/14] aarch64: Generate fences for aarch64
Date: Fri, 24 Jun 2016 17:17:18 +0100 [thread overview]
Message-ID: <87h9cizhm9.fsf@linaro.org> (raw)
In-Reply-To: <20160618040343.19517-14-bobby.prani@gmail.com>
Pranith Kumar <bobby.prani@gmail.com> writes:
> Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
> ---
> target-arm/translate-a64.c | 18 +++++++++++++-----
> 1 file changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
> index ce8141a..fa24bf2 100644
> --- a/target-arm/translate-a64.c
> +++ b/target-arm/translate-a64.c
> @@ -1250,7 +1250,7 @@ static void handle_sync(DisasContext *s, uint32_t insn,
> return;
> case 4: /* DSB */
> case 5: /* DMB */
> - /* We don't emulate caches so barriers are no-ops */
> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
> return;
> case 6: /* ISB */
> /* We need to break the TB after this insn to execute
> @@ -1855,23 +1855,31 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
> }
> tcg_addr = read_cpu_reg_sp(s, rn, 1);
>
> - /* Note that since TCG is single threaded load-acquire/store-release
> - * semantics require no extra if (is_lasr) { ... } handling.
> - */
> -
> if (is_excl) {
> if (!is_store) {
> s->is_ldex = true;
> gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair);
> + if (is_lasr) {
> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_ACQ);
> + }
> } else {
> + if (is_lasr) {
> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_REL);
> + }
> gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair);
> }
> } else {
> TCGv_i64 tcg_rt = cpu_reg(s, rt);
> if (is_store) {
> + if (is_lasr) {
> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_REL);
> + }
> do_gpr_st(s, tcg_rt, tcg_addr, size);
> } else {
> do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false);
> + if (is_lasr) {
> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_ACQ);
> + }
See the private email I sent you with the litmus tests. I think you'll
need to confirm this is working as expected.
> }
> }
> }
--
Alex Bennée
next prev parent reply other threads:[~2016-06-24 16:17 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20160618040343.19517-1-bobby.prani@gmail.com>
2016-06-18 4:03 ` [Qemu-devel] [RFC v3 PATCH 01/14] Introduce TCGOpcode for memory barrier Pranith Kumar
2016-06-20 21:21 ` Sergey Fedorov
2016-06-21 14:52 ` Pranith Kumar
2016-06-21 15:09 ` Alex Bennée
2016-06-21 18:06 ` Pranith Kumar
2016-06-22 15:50 ` Sergey Fedorov
2016-06-21 7:30 ` Paolo Bonzini
2016-06-21 18:04 ` Alex Bennée
2016-06-21 18:09 ` Pranith Kumar
2016-06-21 18:23 ` Alex Bennée
2016-06-21 19:40 ` Richard Henderson
2016-06-18 4:03 ` [Qemu-devel] [RFC v3 PATCH 02/14] tcg/i386: Add support for fence Pranith Kumar
2016-06-21 7:24 ` Paolo Bonzini
2016-06-22 16:25 ` Alex Bennée
2016-06-22 16:49 ` Richard Henderson
2016-06-22 18:18 ` Alex Bennée
2016-06-18 4:03 ` [RFC v3 PATCH 03/14] tcg/aarch64: " Pranith Kumar
2016-06-18 4:03 ` [Qemu-devel] " Pranith Kumar
2016-06-23 16:18 ` Alex Bennée
2016-06-23 16:18 ` [Qemu-devel] " Alex Bennée
2016-06-23 16:50 ` Richard Henderson
2016-06-23 16:50 ` [Qemu-devel] " Richard Henderson
2016-06-23 19:58 ` Alex Bennée
2016-06-23 19:58 ` [Qemu-devel] " Alex Bennée
2016-06-18 4:03 ` [RFC v3 PATCH 04/14] tcg/arm: " Pranith Kumar
2016-06-18 4:03 ` [Qemu-devel] " Pranith Kumar
2016-06-23 16:30 ` Alex Bennée
2016-06-23 16:30 ` [Qemu-devel] " Alex Bennée
2016-06-23 16:49 ` Richard Henderson
2016-06-23 16:49 ` [Qemu-devel] " Richard Henderson
2016-06-18 4:03 ` [Qemu-devel] [RFC v3 PATCH 05/14] tcg/ia64: " Pranith Kumar
2016-06-18 4:03 ` [Qemu-devel] [RFC v3 PATCH 06/14] tcg/mips: " Pranith Kumar
2016-06-18 4:03 ` [Qemu-devel] [RFC v3 PATCH 07/14] tcg/ppc: " Pranith Kumar
2016-06-22 19:50 ` Sergey Fedorov
2016-06-22 20:21 ` Richard Henderson
2016-06-22 20:27 ` Sergey Fedorov
2016-06-23 14:42 ` Sergey Fedorov
2016-06-18 4:03 ` [Qemu-devel] [RFC v3 PATCH 08/14] tcg/s390: " Pranith Kumar
2016-06-21 7:26 ` Paolo Bonzini
2016-06-18 4:03 ` [Qemu-devel] [RFC v3 PATCH 09/14] tcg/sparc: " Pranith Kumar
2016-06-22 19:56 ` Sergey Fedorov
2016-06-18 4:03 ` [Qemu-devel] [RFC v3 PATCH 10/14] tcg/tci: " Pranith Kumar
2016-06-22 19:57 ` Sergey Fedorov
2016-06-22 20:25 ` Richard Henderson
2016-06-22 20:28 ` Sergey Fedorov
2016-06-18 4:03 ` [RFC v3 PATCH 11/14] target-arm: Generate fences in ARMv7 frontend Pranith Kumar
2016-06-18 4:03 ` [Qemu-devel] " Pranith Kumar
2016-06-18 4:03 ` [Qemu-devel] [RFC v3 PATCH 12/14] target-alpha: Generate fence op Pranith Kumar
2016-06-18 4:03 ` [RFC v3 PATCH 13/14] aarch64: Generate fences for aarch64 Pranith Kumar
2016-06-18 4:03 ` [Qemu-devel] " Pranith Kumar
2016-06-24 16:17 ` Alex Bennée [this message]
2016-06-24 16:17 ` Alex Bennée
2016-06-18 4:03 ` [Qemu-devel] [RFC v3 PATCH 14/14] target-i386: Generate fences for x86 Pranith Kumar
2016-06-18 5:48 ` Richard Henderson
2016-06-20 15:05 ` Pranith Kumar
2016-06-21 7:28 ` Paolo Bonzini
2016-06-21 15:57 ` Richard Henderson
2016-06-21 16:12 ` Paolo Bonzini
2016-06-21 16:23 ` Richard Henderson
2016-06-21 16:33 ` Paolo Bonzini
2016-06-21 17:28 ` Pranith Kumar
2016-06-21 17:54 ` Peter Maydell
2016-06-21 18:03 ` Pranith Kumar
2016-06-21 18:25 ` Alex Bennée
2016-06-22 11:18 ` Sergey Fedorov
2016-06-18 4:08 ` [Qemu-devel] [RFC v3 PATCH 00/14] tcg: Add fence gen support Pranith Kumar
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