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From: "Alex Bennée" <alex.bennee@linaro.org>
To: Pranith Kumar <bobby.prani@gmail.com>
Cc: Andrzej Zaborowski <balrogg@gmail.com>,
	Richard Henderson <rth@twiddle.net>,
	"open list\:ARM target" <qemu-arm@nongnu.org>,
	"open list\:All patches CC here" <qemu-devel@nongnu.org>,
	serge.fdrv@gmail.com, Peter Maydell <peter.maydell@linaro.org>
Subject: Re: [RFC v3 PATCH 04/14] tcg/arm: Add support for fence
Date: Thu, 23 Jun 2016 17:30:29 +0100	[thread overview]
Message-ID: <87h9cjrhp6.fsf@linaro.org> (raw)
In-Reply-To: <20160618040343.19517-5-bobby.prani@gmail.com>


Pranith Kumar <bobby.prani@gmail.com> writes:

> Cc: Andrzej Zaborowski <balrogg@gmail.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/arm/tcg-target.inc.c | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
>
> diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
> index f9f54c6..1447aa8 100644
> --- a/tcg/arm/tcg-target.inc.c
> +++ b/tcg/arm/tcg-target.inc.c
> @@ -313,6 +313,10 @@ typedef enum {
>      INSN_LDRD_REG  = 0x000000d0,
>      INSN_STRD_IMM  = 0x004000f0,
>      INSN_STRD_REG  = 0x000000f0,
> +
> +    INSN_DMB_ISH   = 0x5bf07ff5,
> +    INSN_DMB_MCR   = 0xba0f07ee,

Again I think you might want to split the instruction encoding. Also
where did you get these encoding from? Is it right the byte-order has
been reversed if it is being written out by endian aware helpers?

> +
>  } ARMInsn;
>
>  #define SHIFT_IMM_LSL(im)	(((im) << 7) | 0x00)
> @@ -1066,6 +1070,15 @@ static inline void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l)
>      }
>  }
>
> +static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
> +{
> +    if (use_armv7_instructions) {
> +        tcg_out32(s, INSN_DMB_ISH);
> +    } else if (use_armv6_instructions) {
> +        tcg_out32(s, INSN_DMB_MCR);
> +    }
> +}
> +
>  #ifdef CONFIG_SOFTMMU
>  /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
>   *                                     int mmu_idx, uintptr_t ra)
> @@ -1923,6 +1936,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
>          tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]);
>          break;
>
> +    case INDEX_op_mb:
> +        tcg_out_mb(s, args[0]);
> +        break;
> +
>      case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
>      case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
>      case INDEX_op_call:     /* Always emitted via tcg_out_call.  */
> @@ -1997,6 +2014,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
>      { INDEX_op_div_i32, { "r", "r", "r" } },
>      { INDEX_op_divu_i32, { "r", "r", "r" } },
>
> +    { INDEX_op_mb, { } },
>      { -1 },
>  };


--
Alex Bennée

WARNING: multiple messages have this Message-ID (diff)
From: "Alex Bennée" <alex.bennee@linaro.org>
To: Pranith Kumar <bobby.prani@gmail.com>
Cc: Andrzej Zaborowski <balrogg@gmail.com>,
	Richard Henderson <rth@twiddle.net>,
	"open list:ARM target" <qemu-arm@nongnu.org>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>,
	serge.fdrv@gmail.com, Peter Maydell <peter.maydell@linaro.org>
Subject: Re: [Qemu-devel] [RFC v3 PATCH 04/14] tcg/arm: Add support for fence
Date: Thu, 23 Jun 2016 17:30:29 +0100	[thread overview]
Message-ID: <87h9cjrhp6.fsf@linaro.org> (raw)
In-Reply-To: <20160618040343.19517-5-bobby.prani@gmail.com>


Pranith Kumar <bobby.prani@gmail.com> writes:

> Cc: Andrzej Zaborowski <balrogg@gmail.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/arm/tcg-target.inc.c | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
>
> diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
> index f9f54c6..1447aa8 100644
> --- a/tcg/arm/tcg-target.inc.c
> +++ b/tcg/arm/tcg-target.inc.c
> @@ -313,6 +313,10 @@ typedef enum {
>      INSN_LDRD_REG  = 0x000000d0,
>      INSN_STRD_IMM  = 0x004000f0,
>      INSN_STRD_REG  = 0x000000f0,
> +
> +    INSN_DMB_ISH   = 0x5bf07ff5,
> +    INSN_DMB_MCR   = 0xba0f07ee,

Again I think you might want to split the instruction encoding. Also
where did you get these encoding from? Is it right the byte-order has
been reversed if it is being written out by endian aware helpers?

> +
>  } ARMInsn;
>
>  #define SHIFT_IMM_LSL(im)	(((im) << 7) | 0x00)
> @@ -1066,6 +1070,15 @@ static inline void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l)
>      }
>  }
>
> +static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
> +{
> +    if (use_armv7_instructions) {
> +        tcg_out32(s, INSN_DMB_ISH);
> +    } else if (use_armv6_instructions) {
> +        tcg_out32(s, INSN_DMB_MCR);
> +    }
> +}
> +
>  #ifdef CONFIG_SOFTMMU
>  /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
>   *                                     int mmu_idx, uintptr_t ra)
> @@ -1923,6 +1936,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
>          tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]);
>          break;
>
> +    case INDEX_op_mb:
> +        tcg_out_mb(s, args[0]);
> +        break;
> +
>      case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
>      case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
>      case INDEX_op_call:     /* Always emitted via tcg_out_call.  */
> @@ -1997,6 +2014,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
>      { INDEX_op_div_i32, { "r", "r", "r" } },
>      { INDEX_op_divu_i32, { "r", "r", "r" } },
>
> +    { INDEX_op_mb, { } },
>      { -1 },
>  };


--
Alex Bennée

  reply	other threads:[~2016-06-23 16:30 UTC|newest]

Thread overview: 66+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20160618040343.19517-1-bobby.prani@gmail.com>
2016-06-18  4:03 ` [Qemu-devel] [RFC v3 PATCH 01/14] Introduce TCGOpcode for memory barrier Pranith Kumar
2016-06-20 21:21   ` Sergey Fedorov
2016-06-21 14:52     ` Pranith Kumar
2016-06-21 15:09       ` Alex Bennée
2016-06-21 18:06         ` Pranith Kumar
2016-06-22 15:50       ` Sergey Fedorov
2016-06-21  7:30   ` Paolo Bonzini
2016-06-21 18:04   ` Alex Bennée
2016-06-21 18:09     ` Pranith Kumar
2016-06-21 18:23       ` Alex Bennée
2016-06-21 19:40         ` Richard Henderson
2016-06-18  4:03 ` [Qemu-devel] [RFC v3 PATCH 02/14] tcg/i386: Add support for fence Pranith Kumar
2016-06-21  7:24   ` Paolo Bonzini
2016-06-22 16:25   ` Alex Bennée
2016-06-22 16:49     ` Richard Henderson
2016-06-22 18:18       ` Alex Bennée
2016-06-18  4:03 ` [RFC v3 PATCH 03/14] tcg/aarch64: " Pranith Kumar
2016-06-18  4:03   ` [Qemu-devel] " Pranith Kumar
2016-06-23 16:18   ` Alex Bennée
2016-06-23 16:18     ` [Qemu-devel] " Alex Bennée
2016-06-23 16:50     ` Richard Henderson
2016-06-23 16:50       ` [Qemu-devel] " Richard Henderson
2016-06-23 19:58       ` Alex Bennée
2016-06-23 19:58         ` [Qemu-devel] " Alex Bennée
2016-06-18  4:03 ` [RFC v3 PATCH 04/14] tcg/arm: " Pranith Kumar
2016-06-18  4:03   ` [Qemu-devel] " Pranith Kumar
2016-06-23 16:30   ` Alex Bennée [this message]
2016-06-23 16:30     ` Alex Bennée
2016-06-23 16:49     ` Richard Henderson
2016-06-23 16:49       ` [Qemu-devel] " Richard Henderson
2016-06-18  4:03 ` [Qemu-devel] [RFC v3 PATCH 05/14] tcg/ia64: " Pranith Kumar
2016-06-18  4:03 ` [Qemu-devel] [RFC v3 PATCH 06/14] tcg/mips: " Pranith Kumar
2016-06-18  4:03 ` [Qemu-devel] [RFC v3 PATCH 07/14] tcg/ppc: " Pranith Kumar
2016-06-22 19:50   ` Sergey Fedorov
2016-06-22 20:21     ` Richard Henderson
2016-06-22 20:27       ` Sergey Fedorov
2016-06-23 14:42     ` Sergey Fedorov
2016-06-18  4:03 ` [Qemu-devel] [RFC v3 PATCH 08/14] tcg/s390: " Pranith Kumar
2016-06-21  7:26   ` Paolo Bonzini
2016-06-18  4:03 ` [Qemu-devel] [RFC v3 PATCH 09/14] tcg/sparc: " Pranith Kumar
2016-06-22 19:56   ` Sergey Fedorov
2016-06-18  4:03 ` [Qemu-devel] [RFC v3 PATCH 10/14] tcg/tci: " Pranith Kumar
2016-06-22 19:57   ` Sergey Fedorov
2016-06-22 20:25     ` Richard Henderson
2016-06-22 20:28       ` Sergey Fedorov
2016-06-18  4:03 ` [RFC v3 PATCH 11/14] target-arm: Generate fences in ARMv7 frontend Pranith Kumar
2016-06-18  4:03   ` [Qemu-devel] " Pranith Kumar
2016-06-18  4:03 ` [Qemu-devel] [RFC v3 PATCH 12/14] target-alpha: Generate fence op Pranith Kumar
2016-06-18  4:03 ` [RFC v3 PATCH 13/14] aarch64: Generate fences for aarch64 Pranith Kumar
2016-06-18  4:03   ` [Qemu-devel] " Pranith Kumar
2016-06-24 16:17   ` Alex Bennée
2016-06-24 16:17     ` [Qemu-devel] " Alex Bennée
2016-06-18  4:03 ` [Qemu-devel] [RFC v3 PATCH 14/14] target-i386: Generate fences for x86 Pranith Kumar
2016-06-18  5:48   ` Richard Henderson
2016-06-20 15:05     ` Pranith Kumar
2016-06-21  7:28   ` Paolo Bonzini
2016-06-21 15:57     ` Richard Henderson
2016-06-21 16:12       ` Paolo Bonzini
2016-06-21 16:23         ` Richard Henderson
2016-06-21 16:33           ` Paolo Bonzini
2016-06-21 17:28     ` Pranith Kumar
2016-06-21 17:54       ` Peter Maydell
2016-06-21 18:03         ` Pranith Kumar
2016-06-21 18:25           ` Alex Bennée
2016-06-22 11:18           ` Sergey Fedorov
2016-06-18  4:08 ` [Qemu-devel] [RFC v3 PATCH 00/14] tcg: Add fence gen support Pranith Kumar

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