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From: Deepak Gupta <debug@rivosinc.com>
To: "Radim Krčmář" <rkrcmar@ventanamicro.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
	Andrew Morton <akpm@linux-foundation.org>,
	"Liam R. Howlett" <Liam.Howlett@oracle.com>,
	Vlastimil Babka <vbabka@suse.cz>,
	Lorenzo Stoakes <lorenzo.stoakes@oracle.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Arnd Bergmann <arnd@arndb.de>,
	Christian Brauner <brauner@kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	Oleg Nesterov <oleg@redhat.com>,
	Eric Biederman <ebiederm@xmission.com>,
	Kees Cook <kees@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
	Shuah Khan <shuah@kernel.org>, Jann Horn <jannh@google.com>,
	Conor Dooley <conor+dt@kernel.org>,
	linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org,
	linux-mm@kvack.org, linux-riscv@lists.infradead.org,
	devicetree@vger.kernel.org, linux-arch@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
	alistair.francis@wdc.com, richard.henderson@linaro.org,
	jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com,
	charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com,
	cleger@rivosinc.com, broonie@kernel.org,
	rick.p.edgecombe@intel.com, Zong Li <zong.li@sifive.com>,
	linux-riscv <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH v12 05/28] riscv: usercfi state for task and save/restore of CSR_SSP on trap entry/exit
Date: Wed, 23 Apr 2025 17:00:29 -0700	[thread overview]
Message-ID: <aAl_HRk49lnseiio@debug.ba.rivosinc.com> (raw)
In-Reply-To: <D92WQWAUQYY4.2ED8JAFBDHGRN@ventanamicro.com>

On Thu, Apr 10, 2025 at 01:04:39PM +0200, Radim Krčmář wrote:
>2025-03-14T14:39:24-07:00, Deepak Gupta <debug@rivosinc.com>:
>> diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h
>> @@ -62,6 +62,9 @@ struct thread_info {
>>  	long			user_sp;	/* User stack pointer */
>>  	int			cpu;
>>  	unsigned long		syscall_work;	/* SYSCALL_WORK_ flags */
>> +#ifdef CONFIG_RISCV_USER_CFI
>> +	struct cfi_status	user_cfi_state;
>> +#endif
>
>I don't think it makes sense to put all the data in thread_info.
>kernel_ssp and user_ssp is more than enough and the rest can comfortably
>live elsewhere in task_struct.
>
>thread_info is supposed to be as small as possible -- just spanning
>multiple cache-lines could be noticeable.

I can change it to only include only `user_ssp`, base and size.

But before we go there, see below:

$ pahole -C thread_info kbuild/vmlinux
struct thread_info {
         long unsigned int          flags;                /*     0     8 */
         int                        preempt_count;        /*     8     4 */

         /* XXX 4 bytes hole, try to pack */

         long int                   kernel_sp;            /*    16     8 */
         long int                   user_sp;              /*    24     8 */
         int                        cpu;                  /*    32     4 */

         /* XXX 4 bytes hole, try to pack */

         long unsigned int          syscall_work;         /*    40     8 */
         struct cfi_status          user_cfi_state;       /*    48    32 */
         /* --- cacheline 1 boundary (64 bytes) was 16 bytes ago --- */
         long unsigned int          a0;                   /*    80     8 */
         long unsigned int          a1;                   /*    88     8 */
         long unsigned int          a2;                   /*    96     8 */

         /* size: 104, cachelines: 2, members: 10 */
         /* sum members: 96, holes: 2, sum holes: 8 */
         /* last cacheline: 40 bytes */
};

If we were to remove entire `cfi_status`, it would still be 72 bytes (88 bytes
if shadow call stack were enabled) and already spans across two cachelines. I
did see the comment above that it should fit inside a cacheline. Although I
assumed its stale comment given that it already spans across cacheline and I
didn't see any special mention in commit messages of changes which grew this
structure above one cacheline. So I assumed this was a stale comment.

On the other hand, whenever enable/lock bits are checked, there is a high
likelyhood that user_ssp and other fields are going to be accessed and
thus it actually might be helpful to have it all in one cacheline during
runtime.

So I am not sure if its helpful sticking to the comment which already is stale.

>
>> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
>> @@ -147,6 +147,20 @@ SYM_CODE_START(handle_exception)
>>
>>  	REG_L s0, TASK_TI_USER_SP(tp)
>>  	csrrc s1, CSR_STATUS, t0
>> +	/*
>> +	 * If previous mode was U, capture shadow stack pointer and save it away
>> +	 * Zero CSR_SSP at the same time for sanitization.
>> +	 */
>> +	ALTERNATIVE("nop; nop; nop; nop",
>> +				__stringify(			\
>> +				andi s2, s1, SR_SPP;	\
>> +				bnez s2, skip_ssp_save;	\
>> +				csrrw s2, CSR_SSP, x0;	\
>> +				REG_S s2, TASK_TI_USER_SSP(tp); \
>> +				skip_ssp_save:),
>> +				0,
>> +				RISCV_ISA_EXT_ZICFISS,
>> +				CONFIG_RISCV_USER_CFI)
>
>(I'd prefer this closer to the user_sp and kernel_sp swap, it's breaking
> the flow here.  We also already know if we've returned from userspace
> or not even without SR_SPP, but reusing the information might tangle
> the logic.)
>
>>  	csrr s2, CSR_EPC
>>  	csrr s3, CSR_TVAL
>>  	csrr s4, CSR_CAUSE
>> @@ -236,6 +250,18 @@ SYM_CODE_START_NOALIGN(ret_from_exception)
>>  	csrw CSR_SCRATCH, tp
>> +
>> +	/*
>> +	 * Going back to U mode, restore shadow stack pointer
>> +	 */
>
>Are we?  I think we can be just as well returning back to kernel-space.
>Similar to how we can enter the exception handler from kernel-space.
>
>> +	ALTERNATIVE("nop; nop",
>> +				__stringify(					\
>> +				REG_L s3, TASK_TI_USER_SSP(tp); \
>> +				csrw CSR_SSP, s3),
>> +				0,
>> +				RISCV_ISA_EXT_ZICFISS,
>> +				CONFIG_RISCV_USER_CFI)
>> +
>
>Thanks.

WARNING: multiple messages have this Message-ID (diff)
From: Deepak Gupta <debug@rivosinc.com>
To: "Radim Krčmář" <rkrcmar@ventanamicro.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
	Andrew Morton <akpm@linux-foundation.org>,
	"Liam R. Howlett" <Liam.Howlett@oracle.com>,
	Vlastimil Babka <vbabka@suse.cz>,
	Lorenzo Stoakes <lorenzo.stoakes@oracle.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Arnd Bergmann <arnd@arndb.de>,
	Christian Brauner <brauner@kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	Oleg Nesterov <oleg@redhat.com>,
	Eric Biederman <ebiederm@xmission.com>,
	Kees Cook <kees@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
	Shuah Khan <shuah@kernel.org>, Jann Horn <jannh@google.com>,
	Conor Dooley <conor+dt@kernel.org>,
	linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org,
	linux-mm@kvack.org, linux-riscv@lists.infradead.org,
	devicetree@vger.kernel.org, linux-arch@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
	alistair.francis@wdc.com, richard.henderson@linaro.org,
	jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com,
	charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com,
	cleger@rivosinc.com, broonie@kernel.org,
	rick.p.edgecombe@intel.com, Zong Li <zong.li@sifive.com>,
	linux-riscv <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH v12 05/28] riscv: usercfi state for task and save/restore of CSR_SSP on trap entry/exit
Date: Wed, 23 Apr 2025 17:00:29 -0700	[thread overview]
Message-ID: <aAl_HRk49lnseiio@debug.ba.rivosinc.com> (raw)
In-Reply-To: <D92WQWAUQYY4.2ED8JAFBDHGRN@ventanamicro.com>

On Thu, Apr 10, 2025 at 01:04:39PM +0200, Radim Krčmář wrote:
>2025-03-14T14:39:24-07:00, Deepak Gupta <debug@rivosinc.com>:
>> diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h
>> @@ -62,6 +62,9 @@ struct thread_info {
>>  	long			user_sp;	/* User stack pointer */
>>  	int			cpu;
>>  	unsigned long		syscall_work;	/* SYSCALL_WORK_ flags */
>> +#ifdef CONFIG_RISCV_USER_CFI
>> +	struct cfi_status	user_cfi_state;
>> +#endif
>
>I don't think it makes sense to put all the data in thread_info.
>kernel_ssp and user_ssp is more than enough and the rest can comfortably
>live elsewhere in task_struct.
>
>thread_info is supposed to be as small as possible -- just spanning
>multiple cache-lines could be noticeable.

I can change it to only include only `user_ssp`, base and size.

But before we go there, see below:

$ pahole -C thread_info kbuild/vmlinux
struct thread_info {
         long unsigned int          flags;                /*     0     8 */
         int                        preempt_count;        /*     8     4 */

         /* XXX 4 bytes hole, try to pack */

         long int                   kernel_sp;            /*    16     8 */
         long int                   user_sp;              /*    24     8 */
         int                        cpu;                  /*    32     4 */

         /* XXX 4 bytes hole, try to pack */

         long unsigned int          syscall_work;         /*    40     8 */
         struct cfi_status          user_cfi_state;       /*    48    32 */
         /* --- cacheline 1 boundary (64 bytes) was 16 bytes ago --- */
         long unsigned int          a0;                   /*    80     8 */
         long unsigned int          a1;                   /*    88     8 */
         long unsigned int          a2;                   /*    96     8 */

         /* size: 104, cachelines: 2, members: 10 */
         /* sum members: 96, holes: 2, sum holes: 8 */
         /* last cacheline: 40 bytes */
};

If we were to remove entire `cfi_status`, it would still be 72 bytes (88 bytes
if shadow call stack were enabled) and already spans across two cachelines. I
did see the comment above that it should fit inside a cacheline. Although I
assumed its stale comment given that it already spans across cacheline and I
didn't see any special mention in commit messages of changes which grew this
structure above one cacheline. So I assumed this was a stale comment.

On the other hand, whenever enable/lock bits are checked, there is a high
likelyhood that user_ssp and other fields are going to be accessed and
thus it actually might be helpful to have it all in one cacheline during
runtime.

So I am not sure if its helpful sticking to the comment which already is stale.

>
>> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
>> @@ -147,6 +147,20 @@ SYM_CODE_START(handle_exception)
>>
>>  	REG_L s0, TASK_TI_USER_SP(tp)
>>  	csrrc s1, CSR_STATUS, t0
>> +	/*
>> +	 * If previous mode was U, capture shadow stack pointer and save it away
>> +	 * Zero CSR_SSP at the same time for sanitization.
>> +	 */
>> +	ALTERNATIVE("nop; nop; nop; nop",
>> +				__stringify(			\
>> +				andi s2, s1, SR_SPP;	\
>> +				bnez s2, skip_ssp_save;	\
>> +				csrrw s2, CSR_SSP, x0;	\
>> +				REG_S s2, TASK_TI_USER_SSP(tp); \
>> +				skip_ssp_save:),
>> +				0,
>> +				RISCV_ISA_EXT_ZICFISS,
>> +				CONFIG_RISCV_USER_CFI)
>
>(I'd prefer this closer to the user_sp and kernel_sp swap, it's breaking
> the flow here.  We also already know if we've returned from userspace
> or not even without SR_SPP, but reusing the information might tangle
> the logic.)
>
>>  	csrr s2, CSR_EPC
>>  	csrr s3, CSR_TVAL
>>  	csrr s4, CSR_CAUSE
>> @@ -236,6 +250,18 @@ SYM_CODE_START_NOALIGN(ret_from_exception)
>>  	csrw CSR_SCRATCH, tp
>> +
>> +	/*
>> +	 * Going back to U mode, restore shadow stack pointer
>> +	 */
>
>Are we?  I think we can be just as well returning back to kernel-space.
>Similar to how we can enter the exception handler from kernel-space.
>
>> +	ALTERNATIVE("nop; nop",
>> +				__stringify(					\
>> +				REG_L s3, TASK_TI_USER_SSP(tp); \
>> +				csrw CSR_SSP, s3),
>> +				0,
>> +				RISCV_ISA_EXT_ZICFISS,
>> +				CONFIG_RISCV_USER_CFI)
>> +
>
>Thanks.

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  reply	other threads:[~2025-04-24  0:00 UTC|newest]

Thread overview: 166+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-14 21:39 [PATCH v12 00/28] riscv control-flow integrity for usermode Deepak Gupta
2025-03-14 21:39 ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 01/28] mm: VM_SHADOW_STACK definition for riscv Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-04-07 15:45   ` Alexandre Ghiti
2025-04-07 15:45     ` Alexandre Ghiti
2025-03-14 21:39 ` [PATCH v12 02/28] dt-bindings: riscv: zicfilp and zicfiss in dt-bindings (extensions.yaml) Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 03/28] riscv: zicfiss / zicfilp enumeration Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-04-07 15:48   ` Alexandre Ghiti
2025-04-07 15:48     ` Alexandre Ghiti
2025-04-09 14:43     ` Deepak Gupta
2025-04-09 14:43       ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 04/28] riscv: zicfiss / zicfilp extension csr and bit definitions Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 05/28] riscv: usercfi state for task and save/restore of CSR_SSP on trap entry/exit Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-04-08  8:05   ` Alexandre Ghiti
2025-04-08  8:05     ` Alexandre Ghiti
2025-04-10 11:04   ` Radim Krčmář
2025-04-10 11:04     ` Radim Krčmář
2025-04-24  0:00     ` Deepak Gupta [this message]
2025-04-24  0:00       ` Deepak Gupta
2025-04-24 11:52       ` Radim Krčmář
2025-04-24 11:52         ` Radim Krčmář
2025-04-24 17:56         ` Deepak Gupta
2025-04-24 17:56           ` Deepak Gupta
2025-04-25 11:27           ` Radim Krčmář
2025-04-25 11:27             ` Radim Krčmář
2025-04-24  0:23     ` Deepak Gupta
2025-04-24  0:23       ` Deepak Gupta
2025-04-24 12:16       ` Radim Krčmář
2025-04-24 12:16         ` Radim Krčmář
2025-04-24 18:03         ` Deepak Gupta
2025-04-24 18:03           ` Deepak Gupta
2025-04-25 11:32           ` Radim Krčmář
2025-04-25 11:32             ` Radim Krčmář
2025-03-14 21:39 ` [PATCH v12 06/28] riscv/mm : ensure PROT_WRITE leads to VM_READ | VM_WRITE Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-04-08 10:39   ` Alexandre Ghiti
2025-04-08 10:39     ` Alexandre Ghiti
2025-04-10 10:03   ` Radim Krčmář
2025-04-10 10:03     ` Radim Krčmář
2025-04-24  0:45     ` Deepak Gupta
2025-04-24  0:45       ` Deepak Gupta
2025-04-24 12:23       ` Radim Krčmář
2025-04-24 12:23         ` Radim Krčmář
2025-04-24 12:43         ` Arnd Bergmann
2025-04-24 12:43           ` Arnd Bergmann
2025-03-14 21:39 ` [PATCH v12 07/28] riscv mm: manufacture shadow stack pte Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 08/28] riscv mmu: teach pte_mkwrite to manufacture shadow stack PTEs Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 09/28] riscv mmu: write protect and shadow stack Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 10/28] riscv/mm: Implement map_shadow_stack() syscall Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-04-07  4:50   ` Zong Li
2025-04-07  4:50     ` Zong Li
2025-04-09 14:19     ` Deepak Gupta
2025-04-09 14:19       ` Deepak Gupta
2025-04-10  9:56   ` Radim Krčmář
2025-04-10  9:56     ` Radim Krčmář
2025-04-24  3:16     ` Deepak Gupta
2025-04-24  3:16       ` Deepak Gupta
2025-04-24 12:51       ` Radim Krčmář
2025-04-24 12:51         ` Radim Krčmář
2025-03-14 21:39 ` [PATCH v12 11/28] riscv/shstk: If needed allocate a new shadow stack on clone Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-04-08 10:51   ` Alexandre Ghiti
2025-04-08 10:51     ` Alexandre Ghiti
2025-04-09 14:31     ` Deepak Gupta
2025-04-09 14:31       ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 12/28] riscv: Implements arch agnostic shadow stack prctls Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-03-17  1:29   ` Zong Li
2025-03-17  1:29     ` Zong Li
2025-04-10  9:45   ` Radim Krčmář
2025-04-10  9:45     ` Radim Krčmář
2025-04-24  4:44     ` Deepak Gupta
2025-04-24  4:44       ` Deepak Gupta
2025-04-24 13:36       ` Radim Krčmář
2025-04-24 13:36         ` Radim Krčmář
2025-04-24 18:16         ` Deepak Gupta
2025-04-24 18:16           ` Deepak Gupta
2025-04-25 11:42           ` Radim Krčmář
2025-04-25 11:42             ` Radim Krčmář
2025-04-25 16:39             ` Deepak Gupta
2025-04-25 16:39               ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 13/28] prctl: arch-agnostic prctl for indirect branch tracking Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-03-17  1:29   ` Zong Li
2025-03-17  1:29     ` Zong Li
2025-04-09  8:03   ` Alexandre Ghiti
2025-04-09  8:03     ` Alexandre Ghiti
2025-04-09 14:26     ` Deepak Gupta
2025-04-09 14:26       ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 14/28] riscv: Implements arch agnostic indirect branch tracking prctls Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-03-17  1:29   ` Zong Li
2025-03-17  1:29     ` Zong Li
2025-03-14 21:39 ` [PATCH v12 15/28] riscv/traps: Introduce software check exception Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 16/28] riscv: signal: abstract header saving for setup_sigcontext Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 17/28] riscv/signal: save and restore of shadow stack for signal Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-04-10  8:49   ` Radim Krčmář
2025-04-10  8:49     ` Radim Krčmář
2025-03-14 21:39 ` [PATCH v12 18/28] riscv/kernel: update __show_regs to print shadow stack register Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 19/28] riscv/ptrace: riscv cfi status and state via ptrace and in core files Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-03-20 22:24   ` Radim Krčmář
2025-03-20 22:24     ` Radim Krčmář
2025-03-20 23:09     ` Deepak Gupta
2025-03-20 23:09       ` Deepak Gupta
2025-03-21  7:22       ` Radim Krčmář
2025-03-21  7:22         ` Radim Krčmář
2025-03-14 21:39 ` [PATCH v12 20/28] riscv/hwprobe: zicfilp / zicfiss enumeration in hwprobe Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 21/28] riscv: Add Firmware Feature SBI extensions definitions Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 22/28] riscv: enable kernel access to shadow stack memory via FWFT sbi call Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-03-20 22:10   ` Radim Krčmář
2025-03-20 22:10     ` Radim Krčmář
2025-03-20 22:42     ` Deepak Gupta
2025-03-20 22:42       ` Deepak Gupta
2025-03-21  7:35       ` Radim Krčmář
2025-03-21  7:35         ` Radim Krčmář
2025-03-14 21:39 ` [PATCH v12 23/28] riscv: kernel command line option to opt out of user cfi Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-03-20 21:35   ` Radim Krčmář
2025-03-20 21:35     ` Radim Krčmář
2025-03-20 22:31     ` Deepak Gupta
2025-03-20 22:31       ` Deepak Gupta
2025-03-21  7:31       ` Radim Krčmář
2025-03-21  7:31         ` Radim Krčmář
2025-03-14 21:39 ` [PATCH v12 24/28] arch/riscv: compile vdso with landing pad Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-04-08 12:45   ` Alexandre Ghiti
2025-04-08 12:45     ` Alexandre Ghiti
2025-04-09 14:28     ` Deepak Gupta
2025-04-09 14:28       ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 25/28] riscv: create a config for shadow stack and landing pad instr support Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-03-20 21:25   ` Radim Krčmář
2025-03-20 21:25     ` Radim Krčmář
2025-03-20 22:29     ` Deepak Gupta
2025-03-20 22:29       ` Deepak Gupta
2025-03-21  7:51       ` Radim Krčmář
2025-03-21  7:51         ` Radim Krčmář
2025-03-14 21:39 ` [PATCH v12 26/28] riscv: Documentation for landing pad / indirect branch tracking Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-04-08  8:36   ` Alexandre Ghiti
2025-04-08  8:36     ` Alexandre Ghiti
2025-03-14 21:39 ` [PATCH v12 27/28] riscv: Documentation for shadow stack on riscv Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta
2025-04-08  8:48   ` Alexandre Ghiti
2025-04-08  8:48     ` Alexandre Ghiti
2025-04-10  5:24     ` Deepak Gupta
2025-04-10  5:24       ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 28/28] kselftest/riscv: kselftest for user mode cfi Deepak Gupta
2025-03-14 21:39   ` Deepak Gupta

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