From: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
To: ross.philipson@oracle.com
Cc: xen-devel@lists.xenproject.org, "Jan Beulich" <jbeulich@suse.com>,
"Andrew Cooper" <andrew.cooper3@citrix.com>,
"Roger Pau Monné" <roger.pau@citrix.com>,
"Daniel P. Smith" <dpsmith@apertussolutions.com>,
trenchboot-devel@googlegroups.com
Subject: Re: [PATCH v3 10/22] x86/tpm.c: code for early hashing and extending PCRs (for TPM1.2)
Date: Sat, 14 Jun 2025 01:24:08 +0300 [thread overview]
Message-ID: <aEylCBakGdg1Jv21@MjU3Nj> (raw)
In-Reply-To: <e56617d6-a144-4191-8027-a173f4b07752@oracle.com>
On Thu, Jun 05, 2025 at 10:43:10AM -0700, ross.philipson@oracle.com wrote:
> > +static void send_cmd(unsigned loc, uint8_t *buf, unsigned i_size,
> > + unsigned *o_size)
> > +{
> > + /*
> > + * Value of "data available" bit counts only when "valid" field is set as
> > + * well.
> > + */
> > + const unsigned data_avail = STS_VALID | STS_DATA_AVAIL;
> > +
> > + unsigned i;
> > +
> > + /* Make sure TPM can accept a command. */
> > + if ( (tis_read8(TPM_STS_(loc)) & STS_COMMAND_READY) == 0 )
> > + {
> > + /* Abort current command. */
> > + tis_write8(TPM_STS_(loc), STS_COMMAND_READY);
> > + /* Wait until TPM is ready for a new one. */
> > + while ( (tis_read8(TPM_STS_(loc)) & STS_COMMAND_READY) == 0 );
> > + }
> > +
> > + for ( i = 0; i < i_size; i++ )
> > + tis_write8(TPM_DATA_FIFO_(loc), buf[i]);
> > +
> > + tis_write8(TPM_STS_(loc), STS_TPM_GO);
> > +
> > + /* Wait for the first byte of response. */
> > + while ( (tis_read8(TPM_STS_(loc)) & data_avail) != data_avail);
> > +
> > + for ( i = 0; i < *o_size && tis_read8(TPM_STS_(loc)) & data_avail; i++ )
> > + buf[i] = tis_read8(TPM_DATA_FIFO_(loc));
> > +
> > + if ( i < *o_size )
> > + *o_size = i;
> > +
> > + tis_write8(TPM_STS_(loc), STS_COMMAND_READY);
> > +}
> Is this all that is needed to do the send? I would have thought you would at
> least also need that burst count logic to know when the TPM is ready for
> more data. There are also a number of timeouts that are supposed to be used.
> Maybe Daniel has some thoughts too.
The code in this form works without any issues. Don't know why
burst count isn't taken into account here or why nothing breaks without
it, but this does seem wrong. I think we needed something to work
before Daniel's version was ready and this implementation possibly
wasn't meant to stay.
> > +static inline bool is_tpm12(void)
> > +{
> > + /*
> > + * If one of these conditions is true:
> > + * - INTF_CAPABILITY_x.interfaceVersion is 0 (TIS <= 1.21)
> > + * - INTF_CAPABILITY_x.interfaceVersion is 2 (TIS == 1.3)
> > + * - STS_x.tpmFamily is 0
> > + * we're dealing with TPM1.2.
> > + */
> > + uint32_t intf_version = tis_read32(TPM_INTF_CAPABILITY_(0))
> > + & INTF_VERSION_MASK;
> > + return (intf_version == 0x00000000 || intf_version == 0x20000000 ||
> > + (tis_read32(TPM_STS_(0)) & TPM_FAMILY_MASK) == 0);
> > +}
> > +
> > +/****************************** TPM1.2 specific *******************************/
> > +#define TPM_ORD_Extend 0x00000014
> > +#define TPM_ORD_SHA1Start 0x000000A0
> > +#define TPM_ORD_SHA1Update 0x000000A1
> > +#define TPM_ORD_SHA1CompleteExtend 0x000000A3
> > +
> > +#define TPM_TAG_RQU_COMMAND 0x00C1
> > +#define TPM_TAG_RSP_COMMAND 0x00C4
>
> I am not sure what the long term goal for a TPM driver in Xen might be but
> my suggestion is to lay out the driver more cleanly up front. Split the
> specification defined things (e.g. these things and other from TCG etc) from
> the driver implementation specific definitions and put them in separate
> headers. There is little enough core code now that just putting it all in
> tpm.c seems fine. Just my $0.02...
>
> Thanks,
> Ross
It could help readability to not have it all in one file. Don't know
about plans for evolving the code for future use cases.
Regards
next prev parent reply other threads:[~2025-06-13 22:25 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-30 13:17 [PATCH v3 00/22] x86: Trenchboot Secure Launch DRTM (Xen) Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 01/22] x86/include/asm/intel-txt.h: constants and accessors for TXT registers and heap Sergii Dmytruk
2025-07-02 14:29 ` Jan Beulich
2025-07-02 15:57 ` ross.philipson
2025-07-06 15:57 ` Sergii Dmytruk
2025-07-07 8:24 ` Jan Beulich
2025-09-23 8:52 ` Sergii Dmytruk
2025-07-03 10:27 ` Jan Beulich
2025-07-06 15:59 ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 02/22] include/xen/slr-table.h: Secure Launch Resource Table definitions Sergii Dmytruk
2025-07-02 14:36 ` Jan Beulich
2025-07-06 16:55 ` Sergii Dmytruk
2025-07-07 8:29 ` Jan Beulich
2025-07-07 17:31 ` Sergii Dmytruk
2025-07-08 6:52 ` Jan Beulich
2025-07-13 17:29 ` Sergii Dmytruk
2025-07-14 7:33 ` Jan Beulich
2025-07-14 17:06 ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 03/22] x86/boot: add MLE header and Secure Launch entry point Sergii Dmytruk
2025-07-03 10:25 ` Jan Beulich
2025-07-07 21:54 ` Sergii Dmytruk
2025-07-08 7:02 ` Jan Beulich
2025-07-13 17:51 ` Sergii Dmytruk
2025-07-14 7:38 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 04/22] x86/boot/slaunch-early: implement early initialization Sergii Dmytruk
2025-06-03 16:17 ` ross.philipson
2025-06-11 22:14 ` Sergii Dmytruk
2025-06-12 8:02 ` Jan Beulich
2025-06-12 22:11 ` Sergii Dmytruk
2025-06-12 16:30 ` ross.philipson
2025-06-12 22:08 ` Sergii Dmytruk
2025-07-03 10:50 ` Jan Beulich
2025-07-15 14:10 ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 05/22] x86/boot/slaunch-early: early TXT checks and boot data retrieval Sergii Dmytruk
2025-06-03 17:03 ` ross.philipson
2025-06-11 22:36 ` Sergii Dmytruk
2025-07-08 16:00 ` Jan Beulich
2025-09-23 8:39 ` Sergii Dmytruk
2025-09-23 14:23 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 06/22] xen/arch/x86: reserve TXT memory during Slaunch Sergii Dmytruk
2025-07-10 13:00 ` Jan Beulich
2025-09-22 21:35 ` Sergii Dmytruk
2025-09-22 22:48 ` Jan Beulich
2025-09-23 15:15 ` Sergii Dmytruk
2025-07-10 13:01 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 07/22] x86/mtrr: expose functions for pausing caching Sergii Dmytruk
2025-07-02 14:57 ` Jan Beulich
2025-07-06 17:34 ` Sergii Dmytruk
2025-07-07 8:32 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 08/22] x86/slaunch: restore boot MTRRs after Intel TXT DRTM Sergii Dmytruk
2025-06-03 19:43 ` ross.philipson
2025-06-13 22:01 ` Sergii Dmytruk
2025-07-02 15:11 ` Jan Beulich
2025-07-06 21:55 ` Sergii Dmytruk
2025-07-07 8:37 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 09/22] xen/lib: add implementation of SHA-1 Sergii Dmytruk
2025-07-02 14:45 ` Jan Beulich
2025-07-06 17:07 ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 10/22] x86/tpm.c: code for early hashing and extending PCRs (for TPM1.2) Sergii Dmytruk
2025-06-05 17:43 ` ross.philipson
2025-06-13 22:24 ` Sergii Dmytruk [this message]
2025-10-22 14:07 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 11/22] x86/tpm.c: support extending PCRs of TPM2.0 Sergii Dmytruk
2025-10-22 15:13 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 12/22] x86/hvm: check for VMX in SMX if Slaunch is active Sergii Dmytruk
2025-07-02 14:50 ` Jan Beulich
2025-07-06 17:23 ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 13/22] x86/tpm.c: implement event log for TPM2.0 Sergii Dmytruk
2025-10-22 15:17 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 14/22] x86/boot: choose AP stack based on APIC ID Sergii Dmytruk
2026-01-22 15:52 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 15/22] x86/smpboot.c: TXT AP bringup Sergii Dmytruk
2026-01-22 16:41 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 16/22] x86/slaunch: process DRTM policy Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 17/22] x86/acpi: disallow S3 on Secure Launch boot Sergii Dmytruk
2025-07-02 14:48 ` Jan Beulich
2025-07-06 17:18 ` Sergii Dmytruk
2025-05-30 13:18 ` [PATCH v3 18/22] x86/boot/slaunch-early: find MBI and SLRT on AMD Sergii Dmytruk
2025-05-30 13:18 ` [PATCH v3 19/22] x86/slaunch: support AMD SKINIT Sergii Dmytruk
2025-05-30 13:18 ` [PATCH v3 20/22] x86/slaunch: support EFI boot Sergii Dmytruk
2025-05-30 13:18 ` [PATCH v3 21/22] x86/cpu: report SMX, TXT and SKINIT capabilities Sergii Dmytruk
2026-01-22 15:58 ` Jan Beulich
2025-05-30 13:18 ` [PATCH v3 22/22] MAINTAINERS: add a section for TrenchBoot Slaunch Sergii Dmytruk
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