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From: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "Andrew Cooper" <andrew.cooper3@citrix.com>,
	"Anthony PERARD" <anthony.perard@vates.tech>,
	"Michal Orzel" <michal.orzel@amd.com>,
	"Julien Grall" <julien@xen.org>,
	"Roger Pau Monné" <roger.pau@citrix.com>,
	"Stefano Stabellini" <sstabellini@kernel.org>,
	trenchboot-devel@googlegroups.com,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v3 03/22] x86/boot: add MLE header and Secure Launch entry point
Date: Sun, 13 Jul 2025 20:51:30 +0300	[thread overview]
Message-ID: <aHPyIqo7vnZo6gnc@MjU3Nj> (raw)
In-Reply-To: <01fe310f-a19a-4392-9215-8942c2bb9b86@suse.com>

On Tue, Jul 08, 2025 at 09:02:55AM +0200, Jan Beulich wrote:
> >>> +        .long   0x00020002  /* MLE version 2.2 */
> >>> +        .long   (slaunch_stub_entry - start)  /* Linear entry point of MLE (SINIT virt. address) */
> >>> +        .long   0x00000000  /* First valid page of MLE */
> >>> +        .long   0x00000000  /* Offset within binary of first byte of MLE */
> >>> +        .long   (_end - start)  /* Offset within binary of last byte + 1 of MLE */
> >>
> >> Is the data here describing xen.gz or (rather) xen.efi? In the latter case,
> >> does data past _end (in particular the .reloc section) not matter here?
> >
> > Eventually, both.  EFI case deals with loaded image which, I believe,
> > should have all relocations applied at the time of measurement.
>
> But you're aware of the need to apply relocations a 2nd time? See
> efi_arch_relocate_image(), which reads .reloc contents. Hence I assume
> that section needs to be included in any measurements.

Checked map files and you're right, `__base_relocs_end` goes after
`_end`.  Will update, thanks.

> >>> +         * - DS, ES, SS, FS and GS are undefined according to TXT SDG, but this
> >>> +         *   would make it impossible to initialize GDTR, because GDT base must
> >>> +         *   be relocated in the descriptor, which requires write access that
> >>> +         *   CS doesn't provide. Instead we have to assume that DS is set by
> >>> +         *   SINIT ACM as flat 4GB data segment.
> >>
> >> Do you really _have to_? At least as plausibly SS might be properly set up,
> >> while DS might not be.
> >
> > "have to" is referring to the fact that making this assumption is forced
> > on the implementation.
>
> But that's not really true. The Xen bits could be changed if needed, e.g. ...
>
> >  LGDT instruction uses DS in the code below, hence it's DS.
>
> ... these could be made use SS or even CS.

SS can be used, but is it really any better than DS?  CS can be used for
LGDT but it won't work for modifying base address because code segments
are read-only.  Or do you mean that the comment should be made more
precise?

> >>> +         * Additional restrictions:
> >>> +         * - some MSRs are partially cleared, among them IA32_MISC_ENABLE, so
> >>> +         *   some capabilities might be reported as disabled even if they are
> >>> +         *   supported by CPU
> >>> +         * - interrupts (including NMIs and SMIs) are disabled and must be
> >>> +         *   enabled later
> >>> +         * - trying to enter real mode results in reset
> >>> +         * - APs must be brought up by MONITOR or GETSEC[WAKEUP], depending on
> >>> +         *   which is supported by a given SINIT ACM
> >>
> >> I'm curious: How would MONITOR allow to bring up an AP? That's not even a
> >> memory access.
> >
> > See patch #15.  BSP sets up TXT.MLE.JOIN and writes to an address
> > monitored by APs, this causes APs to become part of dynamic launch by
> > continuing execution at TXT-specific entry point.  It's more of a
> > redirection rather than waking up, just another case of bad terminology.
>
> Okay, (just ftaod) then my more general request: Please try to be as accurate
> as possible in comments (and similarly patch descriptions). "must be brought
> up by" is wording that I interpret to describe the action the "active" party
> (i.e. the BSP) needs to take. Whereas MONITOR, as you now clarify, is the
> action the AP needs to take (and then apparently is further required to
> check for false wakeups).
>
> Jan

I'll try and in particular will correct this comment, but I might still
miss things due to being used to them.  In general when code is
developed over the years by several people doing other projects in
between, things just end up looking weird, so please bear with me.

Regards


  reply	other threads:[~2025-07-13 17:52 UTC|newest]

Thread overview: 83+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-30 13:17 [PATCH v3 00/22] x86: Trenchboot Secure Launch DRTM (Xen) Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 01/22] x86/include/asm/intel-txt.h: constants and accessors for TXT registers and heap Sergii Dmytruk
2025-07-02 14:29   ` Jan Beulich
2025-07-02 15:57     ` ross.philipson
2025-07-06 15:57     ` Sergii Dmytruk
2025-07-07  8:24       ` Jan Beulich
2025-09-23  8:52         ` Sergii Dmytruk
2025-07-03 10:27   ` Jan Beulich
2025-07-06 15:59     ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 02/22] include/xen/slr-table.h: Secure Launch Resource Table definitions Sergii Dmytruk
2025-07-02 14:36   ` Jan Beulich
2025-07-06 16:55     ` Sergii Dmytruk
2025-07-07  8:29       ` Jan Beulich
2025-07-07 17:31         ` Sergii Dmytruk
2025-07-08  6:52           ` Jan Beulich
2025-07-13 17:29             ` Sergii Dmytruk
2025-07-14  7:33               ` Jan Beulich
2025-07-14 17:06                 ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 03/22] x86/boot: add MLE header and Secure Launch entry point Sergii Dmytruk
2025-07-03 10:25   ` Jan Beulich
2025-07-07 21:54     ` Sergii Dmytruk
2025-07-08  7:02       ` Jan Beulich
2025-07-13 17:51         ` Sergii Dmytruk [this message]
2025-07-14  7:38           ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 04/22] x86/boot/slaunch-early: implement early initialization Sergii Dmytruk
2025-06-03 16:17   ` ross.philipson
2025-06-11 22:14     ` Sergii Dmytruk
2025-06-12  8:02       ` Jan Beulich
2025-06-12 22:11         ` Sergii Dmytruk
2025-06-12 16:30       ` ross.philipson
2025-06-12 22:08         ` Sergii Dmytruk
2025-07-03 10:50   ` Jan Beulich
2025-07-15 14:10     ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 05/22] x86/boot/slaunch-early: early TXT checks and boot data retrieval Sergii Dmytruk
2025-06-03 17:03   ` ross.philipson
2025-06-11 22:36     ` Sergii Dmytruk
2025-07-08 16:00   ` Jan Beulich
2025-09-23  8:39     ` Sergii Dmytruk
2025-09-23 14:23       ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 06/22] xen/arch/x86: reserve TXT memory during Slaunch Sergii Dmytruk
2025-07-10 13:00   ` Jan Beulich
2025-09-22 21:35     ` Sergii Dmytruk
2025-09-22 22:48       ` Jan Beulich
2025-09-23 15:15         ` Sergii Dmytruk
2025-07-10 13:01   ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 07/22] x86/mtrr: expose functions for pausing caching Sergii Dmytruk
2025-07-02 14:57   ` Jan Beulich
2025-07-06 17:34     ` Sergii Dmytruk
2025-07-07  8:32       ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 08/22] x86/slaunch: restore boot MTRRs after Intel TXT DRTM Sergii Dmytruk
2025-06-03 19:43   ` ross.philipson
2025-06-13 22:01     ` Sergii Dmytruk
2025-07-02 15:11   ` Jan Beulich
2025-07-06 21:55     ` Sergii Dmytruk
2025-07-07  8:37       ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 09/22] xen/lib: add implementation of SHA-1 Sergii Dmytruk
2025-07-02 14:45   ` Jan Beulich
2025-07-06 17:07     ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 10/22] x86/tpm.c: code for early hashing and extending PCRs (for TPM1.2) Sergii Dmytruk
2025-06-05 17:43   ` ross.philipson
2025-06-13 22:24     ` Sergii Dmytruk
2025-10-22 14:07   ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 11/22] x86/tpm.c: support extending PCRs of TPM2.0 Sergii Dmytruk
2025-10-22 15:13   ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 12/22] x86/hvm: check for VMX in SMX if Slaunch is active Sergii Dmytruk
2025-07-02 14:50   ` Jan Beulich
2025-07-06 17:23     ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 13/22] x86/tpm.c: implement event log for TPM2.0 Sergii Dmytruk
2025-10-22 15:17   ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 14/22] x86/boot: choose AP stack based on APIC ID Sergii Dmytruk
2026-01-22 15:52   ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 15/22] x86/smpboot.c: TXT AP bringup Sergii Dmytruk
2026-01-22 16:41   ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 16/22] x86/slaunch: process DRTM policy Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 17/22] x86/acpi: disallow S3 on Secure Launch boot Sergii Dmytruk
2025-07-02 14:48   ` Jan Beulich
2025-07-06 17:18     ` Sergii Dmytruk
2025-05-30 13:18 ` [PATCH v3 18/22] x86/boot/slaunch-early: find MBI and SLRT on AMD Sergii Dmytruk
2025-05-30 13:18 ` [PATCH v3 19/22] x86/slaunch: support AMD SKINIT Sergii Dmytruk
2025-05-30 13:18 ` [PATCH v3 20/22] x86/slaunch: support EFI boot Sergii Dmytruk
2025-05-30 13:18 ` [PATCH v3 21/22] x86/cpu: report SMX, TXT and SKINIT capabilities Sergii Dmytruk
2026-01-22 15:58   ` Jan Beulich
2025-05-30 13:18 ` [PATCH v3 22/22] MAINTAINERS: add a section for TrenchBoot Slaunch Sergii Dmytruk

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