From: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "Daniel P. Smith" <dpsmith@apertussolutions.com>,
"Ross Philipson" <ross.philipson@oracle.com>,
"Andrew Cooper" <andrew.cooper3@citrix.com>,
"Roger Pau Monné" <roger.pau@citrix.com>,
trenchboot-devel@googlegroups.com,
xen-devel@lists.xenproject.org
Subject: Re: [PATCH v3 05/22] x86/boot/slaunch-early: early TXT checks and boot data retrieval
Date: Tue, 23 Sep 2025 11:39:36 +0300 [thread overview]
Message-ID: <aNJcyA-4sJdQNFK3@MjU3Nj> (raw)
In-Reply-To: <0024c24f-39a4-4b5e-af7b-536f7cebfaff@suse.com>
On Tue, Jul 08, 2025 at 06:00:13PM +0200, Jan Beulich wrote:
> > +static inline int is_in_pmr(const struct txt_os_sinit_data *os_sinit,
> > + uint64_t base, uint32_t size, int check_high)
> > +{
> > + /* Check for size overflow. */
> > + if ( base + size < base )
> > + txt_reset(SLAUNCH_ERROR_INTEGER_OVERFLOW);
> > +
> > + /* Low range always starts at 0, so its size is also end address. */
> > + if ( base >= os_sinit->vtd_pmr_lo_base &&
> > + base + size <= os_sinit->vtd_pmr_lo_size )
>
> If you leverage what the comment says in the 2nd comparsion, why not also
> in the first (which means that could be dropped altogether)? If the start
> is always zero, why does the field exist in the first place?
The range always starts at 0 here because txt_verify_pmr_ranges() reboots
earlier if this assumption doesn't hold. The field can have non-zero
value, but I guess the more memory is protected the better. I'll remove
the first part of the check as useless and clarify the comment.
> > +static inline void txt_verify_pmr_ranges(
> > + const struct txt_os_mle_data *os_mle,
> > + const struct txt_os_sinit_data *os_sinit,
> > + const struct slr_entry_intel_info *info,
> > + uint32_t load_base_addr,
> > + uint32_t tgt_base_addr,
> > + uint32_t xen_size)
> > +{
> > + int check_high_pmr = 0;
>
> Just like Ross mentioned for the return value of is_in_pmr(), this one also
> looks as if it wanted to be bool.
Will update.
> > + /* All regions accessed by 32b code must be below 4G. */
> > + if ( os_sinit->vtd_pmr_hi_base + os_sinit->vtd_pmr_hi_size <=
> > + 0x100000000ULL )
> > + check_high_pmr = 1;
>
> The addition overflowing is only checked later, and that check may be bypassed
> based on the result here. Is that not a possible problem?
Thanks, that looks like a problem to me. Moved the overflow check from
is_in_pmr() before this check.
> > + /*
> > + * If present, check that MBI is covered by PMR. MBI starts with 'uint32_t
> > + * total_size'.
> > + */
> > + if ( info->boot_params_base != 0 &&
> > + !is_in_pmr(os_sinit, info->boot_params_base,
> > + *(uint32_t *)(uintptr_t)info->boot_params_base,
>
> What is this "MBI" which "starts with 'uint32_t total_size'"? Do you perhaps
> mean multiboot2_fixed_t? If you really can't use a proper structure ref here,
> please at least mention whatever type that is in our code base, so the use
> can be found by e.g. grep.
Yes, it's MultiBoot2 Info. Nothing precludes using multiboot2_fixed_t,
will update.
> These inline functions are pretty large. Why do they need to be inline ones?
>
> Jan
The functions are run at entry points, one of which is in 32-bit early
code and another in 64-bit EFI. Having this in the header is simpler
than compiling the code twice. Despite having many lines, it's just a
sequence of checks, so it didn't seem like too much for a header.
Regards
next prev parent reply other threads:[~2025-09-23 8:40 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-30 13:17 [PATCH v3 00/22] x86: Trenchboot Secure Launch DRTM (Xen) Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 01/22] x86/include/asm/intel-txt.h: constants and accessors for TXT registers and heap Sergii Dmytruk
2025-07-02 14:29 ` Jan Beulich
2025-07-02 15:57 ` ross.philipson
2025-07-06 15:57 ` Sergii Dmytruk
2025-07-07 8:24 ` Jan Beulich
2025-09-23 8:52 ` Sergii Dmytruk
2025-07-03 10:27 ` Jan Beulich
2025-07-06 15:59 ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 02/22] include/xen/slr-table.h: Secure Launch Resource Table definitions Sergii Dmytruk
2025-07-02 14:36 ` Jan Beulich
2025-07-06 16:55 ` Sergii Dmytruk
2025-07-07 8:29 ` Jan Beulich
2025-07-07 17:31 ` Sergii Dmytruk
2025-07-08 6:52 ` Jan Beulich
2025-07-13 17:29 ` Sergii Dmytruk
2025-07-14 7:33 ` Jan Beulich
2025-07-14 17:06 ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 03/22] x86/boot: add MLE header and Secure Launch entry point Sergii Dmytruk
2025-07-03 10:25 ` Jan Beulich
2025-07-07 21:54 ` Sergii Dmytruk
2025-07-08 7:02 ` Jan Beulich
2025-07-13 17:51 ` Sergii Dmytruk
2025-07-14 7:38 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 04/22] x86/boot/slaunch-early: implement early initialization Sergii Dmytruk
2025-06-03 16:17 ` ross.philipson
2025-06-11 22:14 ` Sergii Dmytruk
2025-06-12 8:02 ` Jan Beulich
2025-06-12 22:11 ` Sergii Dmytruk
2025-06-12 16:30 ` ross.philipson
2025-06-12 22:08 ` Sergii Dmytruk
2025-07-03 10:50 ` Jan Beulich
2025-07-15 14:10 ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 05/22] x86/boot/slaunch-early: early TXT checks and boot data retrieval Sergii Dmytruk
2025-06-03 17:03 ` ross.philipson
2025-06-11 22:36 ` Sergii Dmytruk
2025-07-08 16:00 ` Jan Beulich
2025-09-23 8:39 ` Sergii Dmytruk [this message]
2025-09-23 14:23 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 06/22] xen/arch/x86: reserve TXT memory during Slaunch Sergii Dmytruk
2025-07-10 13:00 ` Jan Beulich
2025-09-22 21:35 ` Sergii Dmytruk
2025-09-22 22:48 ` Jan Beulich
2025-09-23 15:15 ` Sergii Dmytruk
2025-07-10 13:01 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 07/22] x86/mtrr: expose functions for pausing caching Sergii Dmytruk
2025-07-02 14:57 ` Jan Beulich
2025-07-06 17:34 ` Sergii Dmytruk
2025-07-07 8:32 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 08/22] x86/slaunch: restore boot MTRRs after Intel TXT DRTM Sergii Dmytruk
2025-06-03 19:43 ` ross.philipson
2025-06-13 22:01 ` Sergii Dmytruk
2025-07-02 15:11 ` Jan Beulich
2025-07-06 21:55 ` Sergii Dmytruk
2025-07-07 8:37 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 09/22] xen/lib: add implementation of SHA-1 Sergii Dmytruk
2025-07-02 14:45 ` Jan Beulich
2025-07-06 17:07 ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 10/22] x86/tpm.c: code for early hashing and extending PCRs (for TPM1.2) Sergii Dmytruk
2025-06-05 17:43 ` ross.philipson
2025-06-13 22:24 ` Sergii Dmytruk
2025-10-22 14:07 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 11/22] x86/tpm.c: support extending PCRs of TPM2.0 Sergii Dmytruk
2025-10-22 15:13 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 12/22] x86/hvm: check for VMX in SMX if Slaunch is active Sergii Dmytruk
2025-07-02 14:50 ` Jan Beulich
2025-07-06 17:23 ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 13/22] x86/tpm.c: implement event log for TPM2.0 Sergii Dmytruk
2025-10-22 15:17 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 14/22] x86/boot: choose AP stack based on APIC ID Sergii Dmytruk
2026-01-22 15:52 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 15/22] x86/smpboot.c: TXT AP bringup Sergii Dmytruk
2026-01-22 16:41 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 16/22] x86/slaunch: process DRTM policy Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 17/22] x86/acpi: disallow S3 on Secure Launch boot Sergii Dmytruk
2025-07-02 14:48 ` Jan Beulich
2025-07-06 17:18 ` Sergii Dmytruk
2025-05-30 13:18 ` [PATCH v3 18/22] x86/boot/slaunch-early: find MBI and SLRT on AMD Sergii Dmytruk
2025-05-30 13:18 ` [PATCH v3 19/22] x86/slaunch: support AMD SKINIT Sergii Dmytruk
2025-05-30 13:18 ` [PATCH v3 20/22] x86/slaunch: support EFI boot Sergii Dmytruk
2025-05-30 13:18 ` [PATCH v3 21/22] x86/cpu: report SMX, TXT and SKINIT capabilities Sergii Dmytruk
2026-01-22 15:58 ` Jan Beulich
2025-05-30 13:18 ` [PATCH v3 22/22] MAINTAINERS: add a section for TrenchBoot Slaunch Sergii Dmytruk
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