From: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "Daniel P. Smith" <dpsmith@apertussolutions.com>,
"Ross Philipson" <ross.philipson@oracle.com>,
"Andrew Cooper" <andrew.cooper3@citrix.com>,
"Roger Pau Monné" <roger.pau@citrix.com>,
"Lukasz Hawrylko" <lukasz@hawrylko.pl>,
"Mateusz Mówka" <mateusz.mowka@intel.com>,
trenchboot-devel@googlegroups.com,
xen-devel@lists.xenproject.org
Subject: Re: [PATCH v3 01/22] x86/include/asm/intel-txt.h: constants and accessors for TXT registers and heap
Date: Sun, 6 Jul 2025 18:57:28 +0300 [thread overview]
Message-ID: <aGqc6HfryKoVoLDL@MjU3Nj> (raw)
In-Reply-To: <ce7ff2f4-4657-45a6-98ea-7f6d3a448447@suse.com>
On Wed, Jul 02, 2025 at 04:29:18PM +0200, Jan Beulich wrote:
> Btw, a brief rev log would be nice here. I saw you have something in the
> cover letter, but having to look in two places isn't very helpful.
I don't really know how to effectively maintain 23 logs at the same time
given that changing one patch has cascading effects on the rest. I'd
suggest using `git diff-range` instead, commands for which I can include
in cover letters for convenience.
> > +#include <asm/page.h> // __va()
>
> Nit: No C++ style comments, please.
Sure.
> > +#define _txt(x) __va(x)
> > +#endif
>
> Without any uses the correctness of the above is hard to judge.
The _txt() macro is used right below:
> > +/*
> > + * Always use private space as some of registers are either read-only or not
> > + * present in public space.
> > + */
> > +static inline uint64_t txt_read(unsigned int reg_no)
> > +{
> > + volatile uint64_t *reg = _txt(TXT_PRIV_CONFIG_REGS_BASE + reg_no);
> > + return *reg;
> > +}
> > +
> > +static inline void txt_write(unsigned int reg_no, uint64_t val)
> > +{
> > + volatile uint64_t *reg = _txt(TXT_PRIV_CONFIG_REGS_BASE + reg_no);
> > + *reg = val;
> > +}
> > + * This serves as TXT register barrier after writing to
> > + * TXTCR_CMD_UNLOCK_MEM_CONFIG. Must be done to ensure that any future
> > + * chipset operations see the write.
> > + */
> > + (void)txt_read(TXTCR_ESTS);
>
> I don't think the cast is needed.
It's not needed, but I think that explicitly discarding unused return
value is a generally good practice even when there is a comment.
> > + txt_write(TXTCR_CMD_RESET, 1);
> > + unreachable();
>
> What guarantees the write to take immediate effect? That is, shouldn't there
> be e.g. an infinite loop here, just in case?
I'll return infinite loop from v2. Tried adding `halt()` as Ross
suggests, but including <asm/system.h> doesn't work in the early code
(something about compat headers and missing expansion of things like
__DeFiNe__).
> > +static inline uint64_t txt_bios_data_size(const void *heap)
> > +{
> > + return *(const uint64_t *)heap - sizeof(uint64_t);
>
> Like you already do here, ...
>
> > +}
> > +
> > +static inline void *txt_bios_data_start(const void *heap)
> > +{
> > + return (void *)heap + sizeof(uint64_t);
>
> ... please don't cast away const-ness. I'm pretty sure I said before that
> Misra objects to us doing so.
Mind that you had left some comments on v2 after I sent v3. v4 will
have this section rewritten using loops and constants, which resolves
issues with constness and readability.
> > @@ -409,7 +393,7 @@ int __init tboot_protect_mem_regions(void)
> >
> > /* TXT Private Space */
> > rc = e820_change_range_type(&e820, TXT_PRIV_CONFIG_REGS_BASE,
> > - TXT_PRIV_CONFIG_REGS_BASE + NR_TXT_CONFIG_PAGES * PAGE_SIZE,
> > + TXT_PRIV_CONFIG_REGS_BASE + NR_TXT_CONFIG_SIZE,
>
> Was this perhaps meant to be TXT_CONFIG_SPACE_SIZE?
>
> Jan
Right, thanks, building without tboot didn't catch this.
Regards
next prev parent reply other threads:[~2025-07-06 15:58 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-30 13:17 [PATCH v3 00/22] x86: Trenchboot Secure Launch DRTM (Xen) Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 01/22] x86/include/asm/intel-txt.h: constants and accessors for TXT registers and heap Sergii Dmytruk
2025-07-02 14:29 ` Jan Beulich
2025-07-02 15:57 ` ross.philipson
2025-07-06 15:57 ` Sergii Dmytruk [this message]
2025-07-07 8:24 ` Jan Beulich
2025-09-23 8:52 ` Sergii Dmytruk
2025-07-03 10:27 ` Jan Beulich
2025-07-06 15:59 ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 02/22] include/xen/slr-table.h: Secure Launch Resource Table definitions Sergii Dmytruk
2025-07-02 14:36 ` Jan Beulich
2025-07-06 16:55 ` Sergii Dmytruk
2025-07-07 8:29 ` Jan Beulich
2025-07-07 17:31 ` Sergii Dmytruk
2025-07-08 6:52 ` Jan Beulich
2025-07-13 17:29 ` Sergii Dmytruk
2025-07-14 7:33 ` Jan Beulich
2025-07-14 17:06 ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 03/22] x86/boot: add MLE header and Secure Launch entry point Sergii Dmytruk
2025-07-03 10:25 ` Jan Beulich
2025-07-07 21:54 ` Sergii Dmytruk
2025-07-08 7:02 ` Jan Beulich
2025-07-13 17:51 ` Sergii Dmytruk
2025-07-14 7:38 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 04/22] x86/boot/slaunch-early: implement early initialization Sergii Dmytruk
2025-06-03 16:17 ` ross.philipson
2025-06-11 22:14 ` Sergii Dmytruk
2025-06-12 8:02 ` Jan Beulich
2025-06-12 22:11 ` Sergii Dmytruk
2025-06-12 16:30 ` ross.philipson
2025-06-12 22:08 ` Sergii Dmytruk
2025-07-03 10:50 ` Jan Beulich
2025-07-15 14:10 ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 05/22] x86/boot/slaunch-early: early TXT checks and boot data retrieval Sergii Dmytruk
2025-06-03 17:03 ` ross.philipson
2025-06-11 22:36 ` Sergii Dmytruk
2025-07-08 16:00 ` Jan Beulich
2025-09-23 8:39 ` Sergii Dmytruk
2025-09-23 14:23 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 06/22] xen/arch/x86: reserve TXT memory during Slaunch Sergii Dmytruk
2025-07-10 13:00 ` Jan Beulich
2025-09-22 21:35 ` Sergii Dmytruk
2025-09-22 22:48 ` Jan Beulich
2025-09-23 15:15 ` Sergii Dmytruk
2025-07-10 13:01 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 07/22] x86/mtrr: expose functions for pausing caching Sergii Dmytruk
2025-07-02 14:57 ` Jan Beulich
2025-07-06 17:34 ` Sergii Dmytruk
2025-07-07 8:32 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 08/22] x86/slaunch: restore boot MTRRs after Intel TXT DRTM Sergii Dmytruk
2025-06-03 19:43 ` ross.philipson
2025-06-13 22:01 ` Sergii Dmytruk
2025-07-02 15:11 ` Jan Beulich
2025-07-06 21:55 ` Sergii Dmytruk
2025-07-07 8:37 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 09/22] xen/lib: add implementation of SHA-1 Sergii Dmytruk
2025-07-02 14:45 ` Jan Beulich
2025-07-06 17:07 ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 10/22] x86/tpm.c: code for early hashing and extending PCRs (for TPM1.2) Sergii Dmytruk
2025-06-05 17:43 ` ross.philipson
2025-06-13 22:24 ` Sergii Dmytruk
2025-10-22 14:07 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 11/22] x86/tpm.c: support extending PCRs of TPM2.0 Sergii Dmytruk
2025-10-22 15:13 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 12/22] x86/hvm: check for VMX in SMX if Slaunch is active Sergii Dmytruk
2025-07-02 14:50 ` Jan Beulich
2025-07-06 17:23 ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 13/22] x86/tpm.c: implement event log for TPM2.0 Sergii Dmytruk
2025-10-22 15:17 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 14/22] x86/boot: choose AP stack based on APIC ID Sergii Dmytruk
2026-01-22 15:52 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 15/22] x86/smpboot.c: TXT AP bringup Sergii Dmytruk
2026-01-22 16:41 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 16/22] x86/slaunch: process DRTM policy Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 17/22] x86/acpi: disallow S3 on Secure Launch boot Sergii Dmytruk
2025-07-02 14:48 ` Jan Beulich
2025-07-06 17:18 ` Sergii Dmytruk
2025-05-30 13:18 ` [PATCH v3 18/22] x86/boot/slaunch-early: find MBI and SLRT on AMD Sergii Dmytruk
2025-05-30 13:18 ` [PATCH v3 19/22] x86/slaunch: support AMD SKINIT Sergii Dmytruk
2025-05-30 13:18 ` [PATCH v3 20/22] x86/slaunch: support EFI boot Sergii Dmytruk
2025-05-30 13:18 ` [PATCH v3 21/22] x86/cpu: report SMX, TXT and SKINIT capabilities Sergii Dmytruk
2026-01-22 15:58 ` Jan Beulich
2025-05-30 13:18 ` [PATCH v3 22/22] MAINTAINERS: add a section for TrenchBoot Slaunch Sergii Dmytruk
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