From: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "Daniel P. Smith" <dpsmith@apertussolutions.com>,
"Andrew Cooper" <andrew.cooper3@citrix.com>,
"Roger Pau Monné" <roger.pau@citrix.com>,
trenchboot-devel@googlegroups.com,
xen-devel@lists.xenproject.org
Subject: Re: [PATCH v3 11/22] x86/tpm.c: support extending PCRs of TPM2.0
Date: Mon, 29 Jun 2026 01:09:49 +0300 [thread overview]
Message-ID: <akGbrdHHrBGk8UrI@MjU3Nj> (raw)
In-Reply-To: <91835e2e-cf59-484e-9583-f0c07513cfc1@suse.com>
On Wed, Oct 22, 2025 at 05:13:26PM +0200, Jan Beulich wrote:
> > -/****************************** TPM1.2 specific *******************************/
> > -#define TPM_ORD_Extend 0x00000014
> > -#define TPM_ORD_SHA1Start 0x000000A0
> > -#define TPM_ORD_SHA1Update 0x000000A1
> > -#define TPM_ORD_SHA1CompleteExtend 0x000000A3
> > +/****************************** TPM1.2 & TPM2.0 *******************************/
> >
> > -#define TPM_TAG_RQU_COMMAND 0x00C1
> > -#define TPM_TAG_RSP_COMMAND 0x00C4
> > +/*
> > + * TPM1.2 is required to support commands of up to 1101 bytes, vendors rarely
> > + * go above that. Limit maximum size of block of data to be hashed to 1024.
> > + *
> > + * TPM2.0 should support hashing of at least 1024 bytes.
> > + */
> > +#define MAX_HASH_BLOCK 1024
> >
> > /* All fields of following structs are big endian. */
> > struct tpm_cmd_hdr {
> > @@ -168,6 +179,17 @@ struct tpm_rsp_hdr {
> > uint32_t returnCode;
> > } __packed;
> >
> > +/****************************** TPM1.2 specific *******************************/
> > +
> > +#define TPM_ORD_Extend 0x00000014
> > +#define TPM_ORD_SHA1Start 0x000000A0
> > +#define TPM_ORD_SHA1Update 0x000000A1
> > +#define TPM_ORD_SHA1CompleteExtend 0x000000A3
> > +
> > +#define TPM_TAG_RQU_COMMAND 0x00C1
> > +#define TPM_TAG_RSP_COMMAND 0x00C4
> > +
> > +/* All fields of following structs are big endian. */
> > struct extend_cmd {
> > struct tpm_cmd_hdr h;
> > uint32_t pcrNum;
>
> Can the previous patch please put these right in their final resting place?
Some earlier comment of yours requested separate headers for these
definitions, so they aren't moved anymore.
> > +#define PUT_BYTES(p, bytes, size) do { \
> > + memcpy((p), (bytes), (size)); \
>
> Preferably without the excess parentheses, much like you have it ...
>
> > + (p) += (size); \
> > + } while ( 0 )
> > +
> > +#define PUT_16BIT(p, data) do { \
> > + *(uint16_t *)(p) = swap16(data); \
>
> ... e.g. in the function call here.
>
> > + (p) += 2; \
> > + } while ( 0 )
OK, just tend to always parenthesise parameters in macros.
> > + cmd_rsp.finish_c = (struct tpm2_sequence_complete_cmd) {
> > + .h.tag = swap16(TPM_ST_SESSIONS),
> > + .h.paramSize = swap32(sizeof(cmd_rsp.finish_c) + size),
> > + .h.ordinal = swap32(TPM2_PCR_EventSequenceComplete),
> > + .pcrHandle = swap32(HR_PCR + pcr),
> > + .sequenceHandle = swap32(seq_handle),
> > + .sessionHdrSize = swap32(sizeof(struct tpm2_session_header)*2),
>
> Why *2? Where to the two session headers go? (Also nit: blanks missing around *.)
>
> > + .pcrSession.handle = swap32(TPM_RS_PW),
> > + .sequenceSession.handle = swap32(TPM_RS_PW),
> > + .dataSize = swap16(size),
> > + };
Because TPM2_PCR_EventSequenceComplete command has two sessions filled directly
below in .pcrSession and .sequenceSession fields. Will fix the spacing.
> > +static uint32_t tpm2_hash_extend(unsigned loc, const uint8_t *buf,
> > + unsigned size, unsigned pcr,
> > + const struct tpm2_log_hashes *log_hashes)
> > +{
> > + uint32_t rc;
> > + unsigned i;
> > + struct tpm2_log_hashes supported_hashes = {0};
> > +
> > + request_locality(loc);
> > +
> > + for ( i = 0; i < log_hashes->count; ++i )
> > + {
> > + const struct tpm2_log_hash *hash = &log_hashes->hashes[i];
> > + if ( !tpm_supports_hash(loc, hash) )
> > + {
> > + printk(XENLOG_WARNING "Skipped hash unsupported by TPM: %d\n",
> > + hash->alg);
> > + continue;
> > + }
> > +
> > + if ( hash->alg == TPM_ALG_SHA1 )
> > + {
> > + sha1_hash(hash->data, buf, size);
> > + }
> > + else if ( hash->alg == TPM_ALG_SHA256 )
> > + {
> > + sha2_256_digest(hash->data, buf, size);
> > + }
> > + else
>
> Is this really just "else", not "else if ( ... )"?
>
> > + {
> > + /* This is called "OneDigest" in TXT Software Development Guide. */
> > + memset(hash->data, 0, size);
> > + hash->data[0] = 1;
> > + }
Yes, only these two algorithms are supported, others are expected to
have some fake values (the next version won't do anything in the
else-branch, leaving that to the caller).
> > + if ( supported_hashes.count == MAX_HASH_COUNT )
> > + {
> > + printk(XENLOG_ERR "Hit hash count implementation limit: %d\n",
> > + MAX_HASH_COUNT);
> > + return -1;
>
> This is an odd return value for a function returning uint32_t. And it's also ...
Will `#define TPM_INTERNAL_ERROR 0xffffffffU`. TPM only uses the lower
12 bits of UINT32, so there is no ambiguity.
> > +
> > + rc = tpm2_hash_extend(loc, buf, size, pcr, &log_hashes);
> > + if ( rc != 0 )
> > + {
> > +#ifndef __EARLY_SLAUNCH__
> > + printk(XENLOG_ERR "Extending PCR%u failed with TPM error: 0x%08x\n",
> > + pcr, rc);
>
> ... not exactly a TPM error.
Will s/TPM/an/.
Regards,
Sergii
next prev parent reply other threads:[~2026-06-28 22:10 UTC|newest]
Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-30 13:17 [PATCH v3 00/22] x86: Trenchboot Secure Launch DRTM (Xen) Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 01/22] x86/include/asm/intel-txt.h: constants and accessors for TXT registers and heap Sergii Dmytruk
2025-07-02 14:29 ` Jan Beulich
2025-07-02 15:57 ` ross.philipson
2025-07-06 15:57 ` Sergii Dmytruk
2025-07-07 8:24 ` Jan Beulich
2025-09-23 8:52 ` Sergii Dmytruk
2025-07-03 10:27 ` Jan Beulich
2025-07-06 15:59 ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 02/22] include/xen/slr-table.h: Secure Launch Resource Table definitions Sergii Dmytruk
2025-07-02 14:36 ` Jan Beulich
2025-07-06 16:55 ` Sergii Dmytruk
2025-07-07 8:29 ` Jan Beulich
2025-07-07 17:31 ` Sergii Dmytruk
2025-07-08 6:52 ` Jan Beulich
2025-07-13 17:29 ` Sergii Dmytruk
2025-07-14 7:33 ` Jan Beulich
2025-07-14 17:06 ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 03/22] x86/boot: add MLE header and Secure Launch entry point Sergii Dmytruk
2025-07-03 10:25 ` Jan Beulich
2025-07-07 21:54 ` Sergii Dmytruk
2025-07-08 7:02 ` Jan Beulich
2025-07-13 17:51 ` Sergii Dmytruk
2025-07-14 7:38 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 04/22] x86/boot/slaunch-early: implement early initialization Sergii Dmytruk
2025-06-03 16:17 ` ross.philipson
2025-06-11 22:14 ` Sergii Dmytruk
2025-06-12 8:02 ` Jan Beulich
2025-06-12 22:11 ` Sergii Dmytruk
2025-06-12 16:30 ` ross.philipson
2025-06-12 22:08 ` Sergii Dmytruk
2025-07-03 10:50 ` Jan Beulich
2025-07-15 14:10 ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 05/22] x86/boot/slaunch-early: early TXT checks and boot data retrieval Sergii Dmytruk
2025-06-03 17:03 ` ross.philipson
2025-06-11 22:36 ` Sergii Dmytruk
2025-07-08 16:00 ` Jan Beulich
2025-09-23 8:39 ` Sergii Dmytruk
2025-09-23 14:23 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 06/22] xen/arch/x86: reserve TXT memory during Slaunch Sergii Dmytruk
2025-07-10 13:00 ` Jan Beulich
2025-09-22 21:35 ` Sergii Dmytruk
2025-09-22 22:48 ` Jan Beulich
2025-09-23 15:15 ` Sergii Dmytruk
2025-07-10 13:01 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 07/22] x86/mtrr: expose functions for pausing caching Sergii Dmytruk
2025-07-02 14:57 ` Jan Beulich
2025-07-06 17:34 ` Sergii Dmytruk
2025-07-07 8:32 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 08/22] x86/slaunch: restore boot MTRRs after Intel TXT DRTM Sergii Dmytruk
2025-06-03 19:43 ` ross.philipson
2025-06-13 22:01 ` Sergii Dmytruk
2025-07-02 15:11 ` Jan Beulich
2025-07-06 21:55 ` Sergii Dmytruk
2025-07-07 8:37 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 09/22] xen/lib: add implementation of SHA-1 Sergii Dmytruk
2025-07-02 14:45 ` Jan Beulich
2025-07-06 17:07 ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 10/22] x86/tpm.c: code for early hashing and extending PCRs (for TPM1.2) Sergii Dmytruk
2025-06-05 17:43 ` ross.philipson
2025-06-13 22:24 ` Sergii Dmytruk
2025-10-22 14:07 ` Jan Beulich
2026-06-28 16:09 ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 11/22] x86/tpm.c: support extending PCRs of TPM2.0 Sergii Dmytruk
2025-10-22 15:13 ` Jan Beulich
2026-06-28 22:09 ` Sergii Dmytruk [this message]
2025-05-30 13:17 ` [PATCH v3 12/22] x86/hvm: check for VMX in SMX if Slaunch is active Sergii Dmytruk
2025-07-02 14:50 ` Jan Beulich
2025-07-06 17:23 ` Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 13/22] x86/tpm.c: implement event log for TPM2.0 Sergii Dmytruk
2025-10-22 15:17 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 14/22] x86/boot: choose AP stack based on APIC ID Sergii Dmytruk
2026-01-22 15:52 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 15/22] x86/smpboot.c: TXT AP bringup Sergii Dmytruk
2026-01-22 16:41 ` Jan Beulich
2025-05-30 13:17 ` [PATCH v3 16/22] x86/slaunch: process DRTM policy Sergii Dmytruk
2025-05-30 13:17 ` [PATCH v3 17/22] x86/acpi: disallow S3 on Secure Launch boot Sergii Dmytruk
2025-07-02 14:48 ` Jan Beulich
2025-07-06 17:18 ` Sergii Dmytruk
2025-05-30 13:18 ` [PATCH v3 18/22] x86/boot/slaunch-early: find MBI and SLRT on AMD Sergii Dmytruk
2025-05-30 13:18 ` [PATCH v3 19/22] x86/slaunch: support AMD SKINIT Sergii Dmytruk
2025-05-30 13:18 ` [PATCH v3 20/22] x86/slaunch: support EFI boot Sergii Dmytruk
2025-05-30 13:18 ` [PATCH v3 21/22] x86/cpu: report SMX, TXT and SKINIT capabilities Sergii Dmytruk
2026-01-22 15:58 ` Jan Beulich
2025-05-30 13:18 ` [PATCH v3 22/22] MAINTAINERS: add a section for TrenchBoot Slaunch Sergii Dmytruk
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