All of lore.kernel.org
 help / color / mirror / Atom feed
From: Yu-Chien Peter Lin <peter.lin@sifive.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org, pjw@kernel.org,
	palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
	samuel.holland@sifive.com, dlan@kernel.org,
	dfustini@oss.tenstorrent.com, michal.simek@amd.com,
	junhui.liu@pigmoral.tech, darshan.prajapati@einfochips.com,
	akpm@linux-foundation.org, zhangchunyan@iscas.ac.cn,
	luxu.kernel@bytedance.com, pincheng.plct@isrc.iscas.ac.cn,
	nick.hu@sifive.com, jim.shu@sifive.com, zong.li@sifive.com,
	greentime.hu@sifive.com, robin.randhawa@sifive.com,
	scott@riscstar.com, dave.patel@riscstar.com,
	raymond.mao@riscstar.com, anup@brainfault.org,
	pawandeep.oza@oss.qualcomm.com
Subject: Re: [PATCH v2 2/3] dt-bindings: riscv: Add Worlds per-hart properties
Date: Tue, 11 Aug 2026 17:31:56 +0800	[thread overview]
Message-ID: <anrsDDkkOKmnkzAa@plin-1878> (raw)
In-Reply-To: <20260730-glossy-pompous-quokka-c05c60@quoll>

Hi Krzysztof,

On Thu, Jul 30, 2026 at 09:30:24AM +0200, Krzysztof Kozlowski wrote:
> On Thu, Jul 30, 2026 at 12:39:07AM +0800, Yu-Chien Peter Lin wrote:
> > +  riscv,pmlwidlist:
> > +    $ref: /schemas/types.yaml#/definitions/uint64
> > +    description:
> > +      Optional bitmask of WIDs available for S-mode and U-mode use on this hart; each
> > +      set bit N indicates WID N is available. Firmware may read this to select platform
> > +      authorized WIDs for lower-privilege modes.
> >    # RISC-V has multiple properties for cache op block sizes as the sizes
> >    # differ between individual CBO extensions
> >    cache-op-block-size: false
> > diff --git a/Documentation/devicetree/bindings/riscv/worlds.yaml b/Documentation/devicetree/bindings/riscv/worlds.yaml
> > new file mode 100644
> > index 000000000000..cc8b3747591e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/riscv/worlds.yaml
> 
> Please run scripts/checkpatch.pl on the patches and fix reported
> warnings. After that, run also 'scripts/checkpatch.pl --strict' on the
> patches and (probably) fix more warnings. Some warnings can be ignored,
> especially from --strict run, but the code here looks like it needs a
> fix. Feel free to get in touch if the warning is not clear.

The only issue I got is:

WARNING: DT binding documents should be licensed (GPL-2.0-only OR BSD-2-Clause)
#114: FILE: Documentation/devicetree/bindings/riscv/worlds.yaml:1:
+# SPDX-License-Identifier: (GPL-2.0 OR MIT)

Hope I am not missing other warnings or errors.

Thanks,
Peter Lin

WARNING: multiple messages have this Message-ID (diff)
From: Yu-Chien Peter Lin <peter.lin@sifive.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org, pjw@kernel.org,
	palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
	samuel.holland@sifive.com, dlan@kernel.org,
	dfustini@oss.tenstorrent.com, michal.simek@amd.com,
	junhui.liu@pigmoral.tech, darshan.prajapati@einfochips.com,
	akpm@linux-foundation.org, zhangchunyan@iscas.ac.cn,
	luxu.kernel@bytedance.com, pincheng.plct@isrc.iscas.ac.cn,
	nick.hu@sifive.com, jim.shu@sifive.com, zong.li@sifive.com,
	greentime.hu@sifive.com, robin.randhawa@sifive.com,
	scott@riscstar.com, dave.patel@riscstar.com,
	raymond.mao@riscstar.com, anup@brainfault.org,
	pawandeep.oza@oss.qualcomm.com
Subject: Re: [PATCH v2 2/3] dt-bindings: riscv: Add Worlds per-hart properties
Date: Tue, 11 Aug 2026 17:31:56 +0800	[thread overview]
Message-ID: <anrsDDkkOKmnkzAa@plin-1878> (raw)
In-Reply-To: <20260730-glossy-pompous-quokka-c05c60@quoll>

Hi Krzysztof,

On Thu, Jul 30, 2026 at 09:30:24AM +0200, Krzysztof Kozlowski wrote:
> On Thu, Jul 30, 2026 at 12:39:07AM +0800, Yu-Chien Peter Lin wrote:
> > +  riscv,pmlwidlist:
> > +    $ref: /schemas/types.yaml#/definitions/uint64
> > +    description:
> > +      Optional bitmask of WIDs available for S-mode and U-mode use on this hart; each
> > +      set bit N indicates WID N is available. Firmware may read this to select platform
> > +      authorized WIDs for lower-privilege modes.
> >    # RISC-V has multiple properties for cache op block sizes as the sizes
> >    # differ between individual CBO extensions
> >    cache-op-block-size: false
> > diff --git a/Documentation/devicetree/bindings/riscv/worlds.yaml b/Documentation/devicetree/bindings/riscv/worlds.yaml
> > new file mode 100644
> > index 000000000000..cc8b3747591e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/riscv/worlds.yaml
> 
> Please run scripts/checkpatch.pl on the patches and fix reported
> warnings. After that, run also 'scripts/checkpatch.pl --strict' on the
> patches and (probably) fix more warnings. Some warnings can be ignored,
> especially from --strict run, but the code here looks like it needs a
> fix. Feel free to get in touch if the warning is not clear.

The only issue I got is:

WARNING: DT binding documents should be licensed (GPL-2.0-only OR BSD-2-Clause)
#114: FILE: Documentation/devicetree/bindings/riscv/worlds.yaml:1:
+# SPDX-License-Identifier: (GPL-2.0 OR MIT)

Hope I am not missing other warnings or errors.

Thanks,
Peter Lin

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2026-08-11  9:32 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-29 16:39 [PATCH v2 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings Yu-Chien Peter Lin
2026-07-29 16:39 ` Yu-Chien Peter Lin
2026-07-29 16:39 ` [PATCH v2 1/3] dt-bindings: riscv: Add Worlds ISA extensions Yu-Chien Peter Lin
2026-07-29 16:39   ` Yu-Chien Peter Lin
2026-07-29 16:45   ` sashiko-bot
2026-08-10 16:25   ` Conor Dooley
2026-08-10 16:25     ` Conor Dooley
2026-08-11  2:23     ` Yu-Chien Peter Lin
2026-08-11  2:23       ` Yu-Chien Peter Lin
2026-08-11  8:24     ` Yu-Chien Peter Lin
2026-08-11  8:24       ` Yu-Chien Peter Lin
2026-07-29 16:39 ` [PATCH v2 2/3] dt-bindings: riscv: Add Worlds per-hart properties Yu-Chien Peter Lin
2026-07-29 16:39   ` Yu-Chien Peter Lin
2026-07-29 16:52   ` sashiko-bot
2026-07-29 18:06   ` Rob Herring (Arm)
2026-07-29 18:06     ` Rob Herring (Arm)
2026-08-07  7:57     ` Yu-Chien Peter Lin
2026-08-07  7:57       ` Yu-Chien Peter Lin
2026-07-30  7:30   ` Krzysztof Kozlowski
2026-07-30  7:30     ` Krzysztof Kozlowski
2026-08-11  9:31     ` Yu-Chien Peter Lin [this message]
2026-08-11  9:31       ` Yu-Chien Peter Lin
2026-07-29 16:39 ` [PATCH v2 3/3] dt-bindings: sifive: Add WorldGuard Checker Yu-Chien Peter Lin
2026-07-29 16:39   ` Yu-Chien Peter Lin
2026-07-29 18:07   ` Rob Herring (Arm)
2026-07-29 18:07     ` Rob Herring (Arm)
2026-08-11  9:36     ` Yu-Chien Peter Lin
2026-08-11  9:36       ` Yu-Chien Peter Lin
2026-07-30  7:35   ` Krzysztof Kozlowski
2026-07-30  7:35     ` Krzysztof Kozlowski
2026-07-30  7:37     ` Krzysztof Kozlowski
2026-07-30  7:37       ` Krzysztof Kozlowski
2026-08-11  9:42       ` Yu-Chien Peter Lin
2026-08-11  9:42         ` Yu-Chien Peter Lin
2026-07-30 17:36     ` Conor Dooley
2026-07-30 17:36       ` Conor Dooley
2026-08-11  9:59       ` Yu-Chien Peter Lin
2026-08-11  9:59         ` Yu-Chien Peter Lin
2026-08-11  9:41     ` Yu-Chien Peter Lin
2026-08-11  9:41       ` Yu-Chien Peter Lin
2026-07-31  1:43 ` [PATCH v2 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings Nick Kossifidis
2026-07-31  1:43   ` Nick Kossifidis
2026-08-04  8:25   ` Yu-Chien Peter Lin
2026-08-04  8:25     ` Yu-Chien Peter Lin

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=anrsDDkkOKmnkzAa@plin-1878 \
    --to=peter.lin@sifive.com \
    --cc=akpm@linux-foundation.org \
    --cc=alex@ghiti.fr \
    --cc=anup@brainfault.org \
    --cc=aou@eecs.berkeley.edu \
    --cc=conor+dt@kernel.org \
    --cc=darshan.prajapati@einfochips.com \
    --cc=dave.patel@riscstar.com \
    --cc=devicetree@vger.kernel.org \
    --cc=dfustini@oss.tenstorrent.com \
    --cc=dlan@kernel.org \
    --cc=greentime.hu@sifive.com \
    --cc=jim.shu@sifive.com \
    --cc=junhui.liu@pigmoral.tech \
    --cc=krzk+dt@kernel.org \
    --cc=krzk@kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=luxu.kernel@bytedance.com \
    --cc=michal.simek@amd.com \
    --cc=nick.hu@sifive.com \
    --cc=palmer@dabbelt.com \
    --cc=pawandeep.oza@oss.qualcomm.com \
    --cc=pincheng.plct@isrc.iscas.ac.cn \
    --cc=pjw@kernel.org \
    --cc=raymond.mao@riscstar.com \
    --cc=robh@kernel.org \
    --cc=robin.randhawa@sifive.com \
    --cc=samuel.holland@sifive.com \
    --cc=scott@riscstar.com \
    --cc=zhangchunyan@iscas.ac.cn \
    --cc=zong.li@sifive.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.