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From: Aurelien Jarno <aurelien@aurel32.net>
To: Jiayu Du <duge1256@gmail.com>
Cc: srini@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, dlan@kernel.org,
	troy.mitchell@linux.spacemit.com, pjw@kernel.org,
	palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
	p.zabel@pengutronix.de, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, spacemit@lists.linux.dev,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/3] riscv: dts: spacemit: Add K3 eFuse and temperature trim cells
Date: Fri, 6 Nov 2026 23:13:10 +0100	[thread overview]
Message-ID: <au5Q9lYTUegeEglv@aurel32.net> (raw)
In-Reply-To: <20261106060525.346873-4-duge1256@gmail.com>

Hi,

On 2026-11-06 14:05, Jiayu Du wrote:
> Add the K3 eFuse controller with its AES_WTM clock and reset. Describe
> fixed-layout cells for the temperature calibration parameters stored in
> bank 0 and bank 7, using controller-relative offsets.
> 
> Leave the controller disabled for board-level enablement.

What is the reason for enabling it at the board-level? AFAIU, this is 
part of the SoC and does not require any board level hardware. Therefore 
I believe it should just be enabled by default.

> Signed-off-by: Jiayu Du <duge1256@gmail.com>
> ---
>  arch/riscv/boot/dts/spacemit/k3.dtsi | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> index e89d2cc5ca8c..51861fdc6a21 100644
> --- a/arch/riscv/boot/dts/spacemit/k3.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> @@ -1439,6 +1439,31 @@ saplic: interrupt-controller@e0804000 {
>  
>  		/* sec_i2c3: 0xf0614000, not available from Linux */
>  
> +		efuse: efuse@f0702800 {
> +			compatible = "spacemit,k3-efuse";
> +			reg = <0x0 0xf0702800 0x0 0x400>;
> +			clocks = <&syscon_apmu CLK_APMU_AES_WTM>;
> +			resets = <&syscon_apmu RESET_APMU_AES_WTM>;
> +
> +			status = "disabled";
> +
> +			nvmem-layout {
> +				compatible = "fixed-layout";
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +
> +				soc_rtemp_trim1: temperature-trim@120 {
> +					reg = <0x120 0x1>;
> +					bits = <0 8>;
> +				};
> +
> +				soc_rtemp_trim: temperature-trim@19a {
> +					reg = <0x19a 0x2>;
> +					bits = <4 8>;
> +				};

I have tried this patchset, and while I can see non-zero data in the 
/sys/bus/nvmem/devices/f0702800.efuse, both temperature calibration data 
appear as 0. Is that expected?

Regards
Aurelien

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                     http://aurel32.net

WARNING: multiple messages have this Message-ID (diff)
From: Aurelien Jarno <aurelien@aurel32.net>
To: Jiayu Du <duge1256@gmail.com>
Cc: srini@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, dlan@kernel.org,
	troy.mitchell@linux.spacemit.com, pjw@kernel.org,
	palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
	p.zabel@pengutronix.de, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, spacemit@lists.linux.dev,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/3] riscv: dts: spacemit: Add K3 eFuse and temperature trim cells
Date: Fri, 6 Nov 2026 23:13:10 +0100	[thread overview]
Message-ID: <au5Q9lYTUegeEglv@aurel32.net> (raw)
In-Reply-To: <20261106060525.346873-4-duge1256@gmail.com>

Hi,

On 2026-11-06 14:05, Jiayu Du wrote:
> Add the K3 eFuse controller with its AES_WTM clock and reset. Describe
> fixed-layout cells for the temperature calibration parameters stored in
> bank 0 and bank 7, using controller-relative offsets.
> 
> Leave the controller disabled for board-level enablement.

What is the reason for enabling it at the board-level? AFAIU, this is 
part of the SoC and does not require any board level hardware. Therefore 
I believe it should just be enabled by default.

> Signed-off-by: Jiayu Du <duge1256@gmail.com>
> ---
>  arch/riscv/boot/dts/spacemit/k3.dtsi | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> index e89d2cc5ca8c..51861fdc6a21 100644
> --- a/arch/riscv/boot/dts/spacemit/k3.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> @@ -1439,6 +1439,31 @@ saplic: interrupt-controller@e0804000 {
>  
>  		/* sec_i2c3: 0xf0614000, not available from Linux */
>  
> +		efuse: efuse@f0702800 {
> +			compatible = "spacemit,k3-efuse";
> +			reg = <0x0 0xf0702800 0x0 0x400>;
> +			clocks = <&syscon_apmu CLK_APMU_AES_WTM>;
> +			resets = <&syscon_apmu RESET_APMU_AES_WTM>;
> +
> +			status = "disabled";
> +
> +			nvmem-layout {
> +				compatible = "fixed-layout";
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +
> +				soc_rtemp_trim1: temperature-trim@120 {
> +					reg = <0x120 0x1>;
> +					bits = <0 8>;
> +				};
> +
> +				soc_rtemp_trim: temperature-trim@19a {
> +					reg = <0x19a 0x2>;
> +					bits = <4 8>;
> +				};

I have tried this patchset, and while I can see non-zero data in the 
/sys/bus/nvmem/devices/f0702800.efuse, both temperature calibration data 
appear as 0. Is that expected?

Regards
Aurelien

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                     http://aurel32.net

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  reply	other threads:[~2026-11-06 22:13 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-06  6:05 [PATCH 0/3] Add read-only SpacemiT K3 eFuse support Jiayu Du
2026-11-06  6:05 ` Jiayu Du
2026-11-06  6:05 ` [PATCH 1/3] dt-bindings: nvmem: Add SpacemiT K3 eFuse controller Jiayu Du
2026-11-06  6:05   ` Jiayu Du
2026-11-06 17:37   ` Conor Dooley
2026-11-06 17:37     ` Conor Dooley
2026-11-06  6:05 ` [PATCH 2/3] nvmem: Add read-only SpacemiT K3 eFuse support Jiayu Du
2026-11-06  6:05   ` Jiayu Du
2026-11-06 12:15   ` Troy Mitchell
2026-11-06 12:15     ` Troy Mitchell
2026-11-07  4:22   ` Yao Zi
2026-11-07  4:22     ` Yao Zi
2026-11-09 15:19     ` Troy Mitchell
2026-11-09 15:19       ` Troy Mitchell
2026-11-06  6:05 ` [PATCH 3/3] riscv: dts: spacemit: Add K3 eFuse and temperature trim cells Jiayu Du
2026-11-06  6:05   ` Jiayu Du
2026-11-06 22:13   ` Aurelien Jarno [this message]
2026-11-06 22:13     ` Aurelien Jarno

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