[PATCH v2 0/3] Add CPU topology extension support for mshv guests

[PATCH v2 0/3] Add CPU topology extension support for mshv guests

[Doru Blânzeanu]

This patch changes how MSHV constructs and registers the guest CPUID table.
It consists of three commits:

1. i386/cpu.c: Adjust minimum xlevel to 0x8000_001E when TOPOEXT is enabled
2. mshv/mshv-cpu.c: Collect all Intel topology subleaves and AMD cache subleaves
3. accel/mshv: Enable SMT support for the mshv partition

The first commit changes the extended CPUID level to 0x8000_001E when the TOPOEXT
feature is enabled.
This fix correctly reports CPU topology and cache leaves when TOPOEXT is
enabled.

Previous to the second commit, `collect_cpuid_entries` treated `0x0b` and `0x1f`
like ordinary leaves and collected only sub-leaf zero. But these Intel topology
leaves contain one sub-leaf per topology level.
With this patch, now it repeatedly calls `cpu_x86_cpuid` and stores every
result until ECX[15:8] becomes zero (same as kvm does).

Changes since V1:
- Enable SMT support in the mshv partition

Doru Blânzeanu (3):
  i386/cpu.c: Adjust minimum xlevel to 0x8000_001E when TOPOEXT is
    enabled
  mshv/mshv-cpu.c: Collect all Intel topology subleaves and AMD cache
    subleaves
  accel/mshv: Enable SMT support for the mshv partition

 accel/mshv/mshv-all.c       |  3 ++-
 target/i386/cpu.c           |  5 +++++
 target/i386/mshv/mshv-cpu.c | 41 +++++++++++++++++++++++++++++--------
 3 files changed, 40 insertions(+), 9 deletions(-)

-- 
2.54.0

[PATCH v2 1/3] i386/cpu.c: Adjust minimum xlevel to 0x8000_001E when TOPOEXT is enabled

[Doru Blânzeanu]

This ensures the guests can discover the AMD cache and processor topology leaves
when TOPOEXT feature is enabled.

Signed-off-by: Doru Blânzeanu <dblanzeanu@linux.microsoft.com>
---
 target/i386/cpu.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index eab0d5a4d4..e443132ce9 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -9911,6 +9911,11 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
         x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
     }
 
+    /* TOPOEXT requires CPUID[0x8000001D] and CPUID[0x8000001E] */
+    if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) {
+        x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001E);
+    }
+
     /* SEV requires CPUID[0x8000001F] */
     if (sev_enabled()) {
         x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
-- 
2.54.0

[PATCH v2 2/3] mshv/mshv-cpu.c: Collect all Intel topology subleaves and AMD cache subleaves

[Doru Blânzeanu]

This fix makes AMD cache overrides subleaf-specific, makes 0x8000_001E
apply regardless of ECX (not subleaf specific) and collects Intel
topology subleaves (0x0b, 0x1f).

Signed-off-by: Doru Blânzeanu <dblanzeanu@linux.microsoft.com>
---
 target/i386/mshv/mshv-cpu.c | 41 +++++++++++++++++++++++++++++--------
 1 file changed, 33 insertions(+), 8 deletions(-)

diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c
index 4df73bb497..25670667f0 100644
--- a/target/i386/mshv/mshv-cpu.c
+++ b/target/i386/mshv/mshv-cpu.c
@@ -1093,6 +1093,21 @@ static void collect_cpuid_entries(const CPUState *cpu, GList **cpuid_entries)
     /* Collect basic leaves (0x0 to max_basic_leaf) */
     for (leaf = 0; leaf <= max_basic_leaf; leaf++) {
         bool has_subleaves = false;
+
+        if (leaf == 0x0b || leaf == 0x1f) {
+            for (subleaf = 0; subleaf < max_subleaf; subleaf++) {
+                cpu_x86_cpuid(env, leaf, subleaf,
+                              &eax, &ebx, &ecx, &edx);
+                add_cpuid_entry(cpuid_entries, leaf, subleaf,
+                                eax, ebx, ecx, edx);
+
+                if (!(ecx & 0xff00)) {
+                    break;
+                }
+            }
+            continue;
+        }
+
         for (int i = 0; i < n_subleaf_leaves; i++) {
             if (leaf == leaves_with_subleaves[i]) {
                 has_subleaves = true;
@@ -1150,6 +1165,20 @@ static void collect_cpuid_entries(const CPUState *cpu, GList **cpuid_entries)
 
     /* Collect extended leaves (0x80000000 to max_extended_leaf) */
     for (leaf = 0x80000000; leaf <= max_extended_leaf; leaf++) {
+        if (leaf == 0x8000001d) {
+            for (subleaf = 0; subleaf < max_subleaf; subleaf++) {
+                cpu_x86_cpuid(env, leaf, subleaf,
+                              &eax, &ebx, &ecx, &edx);
+
+                add_cpuid_entry(cpuid_entries, leaf, subleaf,
+                                eax, ebx, ecx, edx);
+                if ((eax & 0x1f) == 0) {
+                    break;
+                }
+            }
+            continue;
+        }
+
         cpu_x86_cpuid(env, leaf, 0, &eax, &ebx, &ecx, &edx);
         add_cpuid_entry(cpuid_entries, leaf, 0, eax, ebx, ecx, edx);
     }
@@ -1229,12 +1258,10 @@ static int register_intercept_result_cpuid(const CPUState *cpu,
          * 0xb - Extended Topology Enumeration Leaf
          * 0x1f - V2 Extended Topology Enumeration Leaf
          * AMD
-         * 0x8000_001e - Processor Topology Information
          * 0x8000_0026 - Extended CPU Topology
          */
         if (entry->function == 0xb ||
             entry->function == 0x1f ||
-            entry->function == 0x8000001e ||
             entry->function == 0x80000026) {
             subleaf_specific = 1;
             always_override = 1;
@@ -1245,12 +1272,14 @@ static int register_intercept_result_cpuid(const CPUState *cpu,
          * 0x0D: Processor Extended State Enumeration
          * 0x0F: Platform QoS Monitoring
          * 0x10: Platform QoS Enforcement
+         * 0x8000_001D: AMD Cache Topology
          */
         } else if (entry->function == 0x04 ||
                    entry->function == 0x07 ||
                    entry->function == 0x0d ||
                    entry->function == 0x0f ||
-                   entry->function == 0x10) {
+                   entry->function == 0x10 ||
+                   entry->function == 0x8000001d) {
             subleaf_specific = 1;
             always_override = 1;
         /* Basic feature leaves (no subleaves) */
@@ -2339,11 +2368,6 @@ void mshv_arch_init_vcpu(CPUState *cpu)
     header = (X86XSaveHeader *)(env->xsave_buf + sizeof(X86LegacyXSaveArea));
     header->xcomp_bv = header->xstate_bv | (1ULL << 63);
 
-    /*
-     * TODO: populate topology info:
-     * X86CPUTopoInfo *topo_info = &env->topo_info;
-     */
-
     ret = init_cpuid2(cpu);
     assert(ret == 0);
 
@@ -2394,6 +2418,7 @@ uint32_t mshv_get_supported_cpuid(uint32_t func, uint32_t idx, int reg)
     /* Disable nested virtualization features not yet supported by MSHV */
     if (func == 0x80000001 && reg == R_ECX) {
         ret &= ~CPUID_EXT3_SVM;
+        ret |= CPUID_EXT3_TOPOEXT;
     }
     if (func == 0x01       && reg == R_ECX) {
         ret &= ~CPUID_EXT_VMX;
-- 
2.54.0

[PATCH v2 3/3] accel/mshv: Enable SMT support for the mshv partition

[Doru Blânzeanu]

Signed-off-by: Doru Blânzeanu <dblanzeanu@linux.microsoft.com>
---
 accel/mshv/mshv-all.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c
index d820a67b95..2b854c1ebd 100644
--- a/accel/mshv/mshv-all.c
+++ b/accel/mshv/mshv-all.c
@@ -178,7 +178,8 @@ static int create_partition(int mshv_fd, int *vm_fd)
     pt_flags = (1ULL << MSHV_PT_BIT_LAPIC) |
                (1ULL << MSHV_PT_BIT_X2APIC) |
                (1ULL << MSHV_PT_BIT_GPA_SUPER_PAGES) |
-               (1ULL << MSHV_PT_BIT_CPU_AND_XSAVE_FEATURES);
+               (1ULL << MSHV_PT_BIT_CPU_AND_XSAVE_FEATURES) |
+               (1ULL << MSHV_PT_BIT_SMT_ENABLED_GUEST);
 
     /* enable all */
     disabled_xsave_features.as_uint64 = 0;
-- 
2.54.0

Re: [PATCH v2 1/3] i386/cpu.c: Adjust minimum xlevel to 0x8000_001E when TOPOEXT is enabled

[Magnus Kulke]

On Tue, Nov 10, 2026 at 11:56:15AM +0200, Doru Blânzeanu wrote:
> This ensures the guests can discover the AMD cache and processor topology leaves
> when TOPOEXT feature is enabled.
> 
> Signed-off-by: Doru Blânzeanu <dblanzeanu@linux.microsoft.com>
> ---
>  target/i386/cpu.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index eab0d5a4d4..e443132ce9 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -9911,6 +9911,11 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
>          x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
>      }
>  
> +    /* TOPOEXT requires CPUID[0x8000001D] and CPUID[0x8000001E] */
> +    if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) {
> +        x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001E);
> +    }
> +
>      /* SEV requires CPUID[0x8000001F] */
>      if (sev_enabled()) {
>          x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
> -- 
> 2.54.0

It looks correct, but since this change touches a generic path it might
have an unintended fallout. Maybe we can split this out and post this
as a isolated patch, and solve the issue in allocator-local code like
KVM apparently does in kvm_cpu_instance_init() w/
kvm_cpu_max_instance_init()?