[PATCH 00/13] hw/riscv/virt: device tree reg cleanups

[PATCH 00/13] hw/riscv/virt: device tree reg cleanups

[Joel Stanley]

This is a set of cleanups for the riscv virt machine device tree
generation that apply on top of Daniel's recent series. 

Using dumpdtb the old and new device trees are identical for -M virt and
-M virt,aia=aplic-imsic.

The final patch is not meant for merging, but demonstrates bugs in the
existing code when the reg property describes an address > 4GB.

Based-on: 20250423110630.2249904-1-dbarboza@ventanamicro.com

Joel Stanley (13):
  hw/riscv/virt: Fix clint base address type
  hw/riscv/virt: Use setprop_sized_cells for clint
  hw/riscv/virt: Use setprop_sized_cells for memory
  hw/riscv/virt: Use setprop_sized_cells for aplic
  hw/riscv/virt: Use setprop_sized_cells for aclint
  hw/riscv/virt: Use setprop_sized_cells for plic
  hw/riscv/virt: Use setprop_sized_cells for virtio
  hw/riscv/virt: Use setprop_sized_cells for reset
  hw/riscv/virt: Use setprop_sized_cells for uart
  hw/riscv/virt: Use setprop_sized_cells for rtc
  hw/riscv/virt: Use setprop_sized_cells for iommu
  hw/riscv/virt: Use setprop_sized_cells for pcie
  NOMERGE: virt: Adjust devices so everything is > 4G

 hw/riscv/virt.c | 108 ++++++++++++++++++++++++------------------------
 1 file changed, 53 insertions(+), 55 deletions(-)

-- 
2.47.2

[PATCH 01/13] hw/riscv/virt: Fix clint base address type

[Joel Stanley]

The address is a hardware address, so use hwaddr for consistency with
the rest of the machine.

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 hw/riscv/virt.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 17a790821484..e4c0ac8a2a9a 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -324,7 +324,7 @@ static void create_fdt_socket_clint(RISCVVirtState *s,
     int cpu;
     g_autofree char *clint_name = NULL;
     g_autofree uint32_t *clint_cells = NULL;
-    unsigned long clint_addr;
+    hwaddr clint_addr;
     MachineState *ms = MACHINE(s);
     static const char * const clint_compat[2] = {
         "sifive,clint0", "riscv,clint0"
@@ -340,8 +340,8 @@ static void create_fdt_socket_clint(RISCVVirtState *s,
     }
 
     clint_addr = s->memmap[VIRT_CLINT].base +
-                 (s->memmap[VIRT_CLINT].size * socket);
-    clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
+                 s->memmap[VIRT_CLINT].size * socket;
+    clint_name = g_strdup_printf("/soc/clint@%"HWADDR_PRIx, clint_addr);
     qemu_fdt_add_subnode(ms->fdt, clint_name);
     qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible",
                                   (char **)&clint_compat,
-- 
2.47.2

Re: [PATCH 01/13] hw/riscv/virt: Fix clint base address type

[Daniel Henrique Barboza]

On 4/29/25 3:12 AM, Joel Stanley wrote:
> The address is a hardware address, so use hwaddr for consistency with
> the rest of the machine.
> 
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   hw/riscv/virt.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 17a790821484..e4c0ac8a2a9a 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -324,7 +324,7 @@ static void create_fdt_socket_clint(RISCVVirtState *s,
>       int cpu;
>       g_autofree char *clint_name = NULL;
>       g_autofree uint32_t *clint_cells = NULL;
> -    unsigned long clint_addr;
> +    hwaddr clint_addr;
>       MachineState *ms = MACHINE(s);
>       static const char * const clint_compat[2] = {
>           "sifive,clint0", "riscv,clint0"
> @@ -340,8 +340,8 @@ static void create_fdt_socket_clint(RISCVVirtState *s,
>       }
>   
>       clint_addr = s->memmap[VIRT_CLINT].base +
> -                 (s->memmap[VIRT_CLINT].size * socket);
> -    clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
> +                 s->memmap[VIRT_CLINT].size * socket;
> +    clint_name = g_strdup_printf("/soc/clint@%"HWADDR_PRIx, clint_addr);
>       qemu_fdt_add_subnode(ms->fdt, clint_name);
>       qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible",
>                                     (char **)&clint_compat,

[PATCH 01/13] riscv/virt: Fix address type in create_fdt_socket_clint

[Joel Stanley]

The address is a hardware address, so use hwaddr for consistency with
the rest of the machine.

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 hw/riscv/virt.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 17a790821484..e4c0ac8a2a9a 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -324,7 +324,7 @@ static void create_fdt_socket_clint(RISCVVirtState *s,
     int cpu;
     g_autofree char *clint_name = NULL;
     g_autofree uint32_t *clint_cells = NULL;
-    unsigned long clint_addr;
+    hwaddr clint_addr;
     MachineState *ms = MACHINE(s);
     static const char * const clint_compat[2] = {
         "sifive,clint0", "riscv,clint0"
@@ -340,8 +340,8 @@ static void create_fdt_socket_clint(RISCVVirtState *s,
     }
 
     clint_addr = s->memmap[VIRT_CLINT].base +
-                 (s->memmap[VIRT_CLINT].size * socket);
-    clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
+                 s->memmap[VIRT_CLINT].size * socket;
+    clint_name = g_strdup_printf("/soc/clint@%"HWADDR_PRIx, clint_addr);
     qemu_fdt_add_subnode(ms->fdt, clint_name);
     qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible",
                                   (char **)&clint_compat,
-- 
2.47.2

Re: [PATCH 01/13] riscv/virt: Fix address type in create_fdt_socket_clint

[Daniel Henrique Barboza]

On 4/29/25 3:12 AM, Joel Stanley wrote:
> The address is a hardware address, so use hwaddr for consistency with
> the rest of the machine.
> 
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---

I believe you have 2 patches #1 in this series:

[PATCH 01/13] hw/riscv/virt: Fix clint base address type
[PATCH 01/13] riscv/virt: Fix address type in create_fdt_socket_clint

You probably renamed the commit subject to "hw/riscv/virt" and forgot to remove
the generated patch, since both patches do the same changes.

I believe we can ignore this patch and stick withe the first #1. Thanks,


Daniel



>   hw/riscv/virt.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 17a790821484..e4c0ac8a2a9a 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -324,7 +324,7 @@ static void create_fdt_socket_clint(RISCVVirtState *s,
>       int cpu;
>       g_autofree char *clint_name = NULL;
>       g_autofree uint32_t *clint_cells = NULL;
> -    unsigned long clint_addr;
> +    hwaddr clint_addr;
>       MachineState *ms = MACHINE(s);
>       static const char * const clint_compat[2] = {
>           "sifive,clint0", "riscv,clint0"
> @@ -340,8 +340,8 @@ static void create_fdt_socket_clint(RISCVVirtState *s,
>       }
>   
>       clint_addr = s->memmap[VIRT_CLINT].base +
> -                 (s->memmap[VIRT_CLINT].size * socket);
> -    clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
> +                 s->memmap[VIRT_CLINT].size * socket;
> +    clint_name = g_strdup_printf("/soc/clint@%"HWADDR_PRIx, clint_addr);
>       qemu_fdt_add_subnode(ms->fdt, clint_name);
>       qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible",
>                                     (char **)&clint_compat,

Re: [PATCH 01/13] riscv/virt: Fix address type in create_fdt_socket_clint

[Joel Stanley]

On Tue, 29 Apr 2025 at 21:56, Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
>
>
> On 4/29/25 3:12 AM, Joel Stanley wrote:
> > The address is a hardware address, so use hwaddr for consistency with
> > the rest of the machine.
> >
> > Signed-off-by: Joel Stanley <joel@jms.id.au>
> > ---
>
> I believe you have 2 patches #1 in this series:
>
> [PATCH 01/13] hw/riscv/virt: Fix clint base address type
> [PATCH 01/13] riscv/virt: Fix address type in create_fdt_socket_clint
>
> You probably renamed the commit subject to "hw/riscv/virt" and forgot to remove
> the generated patch, since both patches do the same changes.
>
> I believe we can ignore this patch and stick withe the first #1. Thanks,

Guilty! Thanks for the close review.

You're correct, the first one is the correct one. I pushed a branch
here if it helps:

 https://gitlab.com/shenki/qemu/-/tree/riscv-dt-props-v1

[PATCH 02/13] hw/riscv/virt: Use setprop_sized_cells for clint

[Joel Stanley]

The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.

Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 hw/riscv/virt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index e4c0ac8a2a9a..873d41d10c70 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -346,8 +346,8 @@ static void create_fdt_socket_clint(RISCVVirtState *s,
     qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible",
                                   (char **)&clint_compat,
                                   ARRAY_SIZE(clint_compat));
-    qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg",
-        0x0, clint_addr, 0x0, s->memmap[VIRT_CLINT].size);
+    qemu_fdt_setprop_sized_cells(ms->fdt, clint_name, "reg",
+        2, clint_addr, 2, s->memmap[VIRT_CLINT].size);
     qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended",
         clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
     riscv_socket_fdt_write_id(ms, clint_name, socket);
-- 
2.47.2

Re: [PATCH 02/13] hw/riscv/virt: Use setprop_sized_cells for clint

[Daniel Henrique Barboza]

On 4/29/25 3:12 AM, Joel Stanley wrote:
> The current device tree property uses two cells for the address (and for
> the size), but assumes the they are less than 32 bits by hard coding the
> high cell to zero.
> 
> Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
> and lower 32 bits across cells.
> 
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   hw/riscv/virt.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index e4c0ac8a2a9a..873d41d10c70 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -346,8 +346,8 @@ static void create_fdt_socket_clint(RISCVVirtState *s,
>       qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible",
>                                     (char **)&clint_compat,
>                                     ARRAY_SIZE(clint_compat));
> -    qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg",
> -        0x0, clint_addr, 0x0, s->memmap[VIRT_CLINT].size);
> +    qemu_fdt_setprop_sized_cells(ms->fdt, clint_name, "reg",
> +        2, clint_addr, 2, s->memmap[VIRT_CLINT].size);
>       qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended",
>           clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
>       riscv_socket_fdt_write_id(ms, clint_name, socket);

[PATCH 03/13] hw/riscv/virt: Use setprop_sized_cells for memory

[Joel Stanley]

Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 hw/riscv/virt.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 873d41d10c70..ed28bc06114a 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -311,8 +311,7 @@ static void create_fdt_socket_memory(RISCVVirtState *s, int socket)
     size = riscv_socket_mem_size(ms, socket);
     mem_name = g_strdup_printf("/memory@%"PRIx64, addr);
     qemu_fdt_add_subnode(ms->fdt, mem_name);
-    qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg",
-        addr >> 32, addr, size >> 32, size);
+    qemu_fdt_setprop_sized_cells(ms->fdt, mem_name, "reg", 2, addr, 2, size);
     qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory");
     riscv_socket_fdt_write_id(ms, mem_name, socket);
 }
-- 
2.47.2

Re: [PATCH 03/13] hw/riscv/virt: Use setprop_sized_cells for memory

[Daniel Henrique Barboza]

On 4/29/25 3:12 AM, Joel Stanley wrote:
> Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
> and lower 32 bits across cells.
> 
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   hw/riscv/virt.c | 3 +--
>   1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 873d41d10c70..ed28bc06114a 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -311,8 +311,7 @@ static void create_fdt_socket_memory(RISCVVirtState *s, int socket)
>       size = riscv_socket_mem_size(ms, socket);
>       mem_name = g_strdup_printf("/memory@%"PRIx64, addr);
>       qemu_fdt_add_subnode(ms->fdt, mem_name);
> -    qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg",
> -        addr >> 32, addr, size >> 32, size);
> +    qemu_fdt_setprop_sized_cells(ms->fdt, mem_name, "reg", 2, addr, 2, size);
>       qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory");
>       riscv_socket_fdt_write_id(ms, mem_name, socket);
>   }

[PATCH 04/13] hw/riscv/virt: Use setprop_sized_cells for aplic

[Joel Stanley]

The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.

Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 hw/riscv/virt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index ed28bc06114a..62200ea39d07 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -655,8 +655,8 @@ static void create_fdt_one_aplic(RISCVVirtState *s, int socket,
         qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle);
     }
 
-    qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg",
-                           0x0, aplic_addr, 0x0, aplic_size);
+    qemu_fdt_setprop_sized_cells(ms->fdt, aplic_name, "reg",
+                                 2, aplic_addr, 2, aplic_size);
     qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources",
                           VIRT_IRQCHIP_NUM_SOURCES);
 
-- 
2.47.2

Re: [PATCH 04/13] hw/riscv/virt: Use setprop_sized_cells for aplic

[Daniel Henrique Barboza]

On 4/29/25 3:12 AM, Joel Stanley wrote:
> The current device tree property uses two cells for the address (and for
> the size), but assumes the they are less than 32 bits by hard coding the
> high cell to zero.
> 
> Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
> and lower 32 bits across cells.
> 
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   hw/riscv/virt.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index ed28bc06114a..62200ea39d07 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -655,8 +655,8 @@ static void create_fdt_one_aplic(RISCVVirtState *s, int socket,
>           qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle);
>       }
>   
> -    qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg",
> -                           0x0, aplic_addr, 0x0, aplic_size);
> +    qemu_fdt_setprop_sized_cells(ms->fdt, aplic_name, "reg",
> +                                 2, aplic_addr, 2, aplic_size);
>       qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources",
>                             VIRT_IRQCHIP_NUM_SOURCES);
>   

[PATCH 05/13] hw/riscv/virt: Use setprop_sized_cells for aclint

[Joel Stanley]

The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.

Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 hw/riscv/virt.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 62200ea39d07..0141ea4795e5 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -387,8 +387,8 @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
         qemu_fdt_add_subnode(ms->fdt, name);
         qemu_fdt_setprop_string(ms->fdt, name, "compatible",
             "riscv,aclint-mswi");
-        qemu_fdt_setprop_cells(ms->fdt, name, "reg",
-            0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
+        qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
+            2, addr, 2, RISCV_ACLINT_SWI_SIZE);
         qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
             aclint_mswi_cells, aclint_cells_size);
         qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0);
@@ -410,11 +410,11 @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
     qemu_fdt_add_subnode(ms->fdt, name);
     qemu_fdt_setprop_string(ms->fdt, name, "compatible",
         "riscv,aclint-mtimer");
-    qemu_fdt_setprop_cells(ms->fdt, name, "reg",
-        0x0, addr + RISCV_ACLINT_DEFAULT_MTIME,
-        0x0, size - RISCV_ACLINT_DEFAULT_MTIME,
-        0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,
-        0x0, RISCV_ACLINT_DEFAULT_MTIME);
+    qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
+        2, addr + RISCV_ACLINT_DEFAULT_MTIME,
+        2, size - RISCV_ACLINT_DEFAULT_MTIME,
+        2, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,
+        2, RISCV_ACLINT_DEFAULT_MTIME);
     qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
         aclint_mtimer_cells, aclint_cells_size);
     riscv_socket_fdt_write_id(ms, name, socket);
@@ -428,8 +428,8 @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
         qemu_fdt_add_subnode(ms->fdt, name);
         qemu_fdt_setprop_string(ms->fdt, name, "compatible",
             "riscv,aclint-sswi");
-        qemu_fdt_setprop_cells(ms->fdt, name, "reg",
-            0x0, addr, 0x0, s->memmap[VIRT_ACLINT_SSWI].size);
+        qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
+            2, addr, 2, s->memmap[VIRT_ACLINT_SSWI].size);
         qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
             aclint_sswi_cells, aclint_cells_size);
         qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0);
-- 
2.47.2

Re: [PATCH 05/13] hw/riscv/virt: Use setprop_sized_cells for aclint

[Daniel Henrique Barboza]

On 4/29/25 3:12 AM, Joel Stanley wrote:
> The current device tree property uses two cells for the address (and for
> the size), but assumes the they are less than 32 bits by hard coding the
> high cell to zero.
> 
> Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
> and lower 32 bits across cells.
> 
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   hw/riscv/virt.c | 18 +++++++++---------
>   1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 62200ea39d07..0141ea4795e5 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -387,8 +387,8 @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
>           qemu_fdt_add_subnode(ms->fdt, name);
>           qemu_fdt_setprop_string(ms->fdt, name, "compatible",
>               "riscv,aclint-mswi");
> -        qemu_fdt_setprop_cells(ms->fdt, name, "reg",
> -            0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
> +        qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
> +            2, addr, 2, RISCV_ACLINT_SWI_SIZE);
>           qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
>               aclint_mswi_cells, aclint_cells_size);
>           qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0);
> @@ -410,11 +410,11 @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
>       qemu_fdt_add_subnode(ms->fdt, name);
>       qemu_fdt_setprop_string(ms->fdt, name, "compatible",
>           "riscv,aclint-mtimer");
> -    qemu_fdt_setprop_cells(ms->fdt, name, "reg",
> -        0x0, addr + RISCV_ACLINT_DEFAULT_MTIME,
> -        0x0, size - RISCV_ACLINT_DEFAULT_MTIME,
> -        0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,
> -        0x0, RISCV_ACLINT_DEFAULT_MTIME);
> +    qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
> +        2, addr + RISCV_ACLINT_DEFAULT_MTIME,
> +        2, size - RISCV_ACLINT_DEFAULT_MTIME,
> +        2, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,
> +        2, RISCV_ACLINT_DEFAULT_MTIME);
>       qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
>           aclint_mtimer_cells, aclint_cells_size);
>       riscv_socket_fdt_write_id(ms, name, socket);
> @@ -428,8 +428,8 @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
>           qemu_fdt_add_subnode(ms->fdt, name);
>           qemu_fdt_setprop_string(ms->fdt, name, "compatible",
>               "riscv,aclint-sswi");
> -        qemu_fdt_setprop_cells(ms->fdt, name, "reg",
> -            0x0, addr, 0x0, s->memmap[VIRT_ACLINT_SSWI].size);
> +        qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
> +            2, addr, 2, s->memmap[VIRT_ACLINT_SSWI].size);
>           qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
>               aclint_sswi_cells, aclint_cells_size);
>           qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0);

[PATCH 06/13] hw/riscv/virt: Use setprop_sized_cells for plic

[Joel Stanley]

The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.

Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 hw/riscv/virt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 0141ea4795e5..3b4c3d6b2683 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -493,8 +493,8 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
                          s->soc[socket].num_harts * sizeof(uint32_t) * 4);
     }
 
-    qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg",
-        0x0, plic_addr, 0x0, s->memmap[VIRT_PLIC].size);
+    qemu_fdt_setprop_sized_cells(ms->fdt, plic_name, "reg",
+                                 2, plic_addr, 2, s->memmap[VIRT_PLIC].size);
     qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev",
                           VIRT_IRQCHIP_NUM_SOURCES - 1);
     riscv_socket_fdt_write_id(ms, plic_name, socket);
-- 
2.47.2

Re: [PATCH 06/13] hw/riscv/virt: Use setprop_sized_cells for plic

[Daniel Henrique Barboza]

On 4/29/25 3:12 AM, Joel Stanley wrote:
> The current device tree property uses two cells for the address (and for
> the size), but assumes the they are less than 32 bits by hard coding the
> high cell to zero.
> 
> Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
> and lower 32 bits across cells.
> 
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   hw/riscv/virt.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 0141ea4795e5..3b4c3d6b2683 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -493,8 +493,8 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
>                            s->soc[socket].num_harts * sizeof(uint32_t) * 4);
>       }
>   
> -    qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg",
> -        0x0, plic_addr, 0x0, s->memmap[VIRT_PLIC].size);
> +    qemu_fdt_setprop_sized_cells(ms->fdt, plic_name, "reg",
> +                                 2, plic_addr, 2, s->memmap[VIRT_PLIC].size);
>       qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev",
>                             VIRT_IRQCHIP_NUM_SOURCES - 1);
>       riscv_socket_fdt_write_id(ms, plic_name, socket);

[PATCH 07/13] hw/riscv/virt: Use setprop_sized_cells for virtio

[Joel Stanley]

The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.

Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 hw/riscv/virt.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 3b4c3d6b2683..cf7e16cc6678 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -856,9 +856,7 @@ static void create_fdt_virtio(RISCVVirtState *s, uint32_t irq_virtio_phandle)
 
         qemu_fdt_add_subnode(ms->fdt, name);
         qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio");
-        qemu_fdt_setprop_cells(ms->fdt, name, "reg",
-                               0x0, addr,
-                               0x0, size);
+        qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2, addr, 2, size);
         qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent",
             irq_virtio_phandle);
         if (s->aia_type == VIRT_AIA_TYPE_NONE) {
-- 
2.47.2

Re: [PATCH 07/13] hw/riscv/virt: Use setprop_sized_cells for virtio

[Daniel Henrique Barboza]

On 4/29/25 3:12 AM, Joel Stanley wrote:
> The current device tree property uses two cells for the address (and for
> the size), but assumes the they are less than 32 bits by hard coding the
> high cell to zero.
> 
> Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
> and lower 32 bits across cells.
> 
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   hw/riscv/virt.c | 4 +---
>   1 file changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 3b4c3d6b2683..cf7e16cc6678 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -856,9 +856,7 @@ static void create_fdt_virtio(RISCVVirtState *s, uint32_t irq_virtio_phandle)
>   
>           qemu_fdt_add_subnode(ms->fdt, name);
>           qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio");
> -        qemu_fdt_setprop_cells(ms->fdt, name, "reg",
> -                               0x0, addr,
> -                               0x0, size);
> +        qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2, addr, 2, size);
>           qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent",
>               irq_virtio_phandle);
>           if (s->aia_type == VIRT_AIA_TYPE_NONE) {

[PATCH 08/13] hw/riscv/virt: Use setprop_sized_cells for reset

[Joel Stanley]

The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.

Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 hw/riscv/virt.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index cf7e16cc6678..baa894b11aa6 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -932,8 +932,9 @@ static void create_fdt_reset(RISCVVirtState *s, uint32_t *phandle)
         qemu_fdt_setprop_string_array(ms->fdt, name, "compatible",
                                       (char **)&compat, ARRAY_SIZE(compat));
     }
-    qemu_fdt_setprop_cells(ms->fdt, name, "reg",
-        0x0, s->memmap[VIRT_TEST].base, 0x0, s->memmap[VIRT_TEST].size);
+    qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
+                                 2, s->memmap[VIRT_TEST].base,
+                                 2, s->memmap[VIRT_TEST].size);
     qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle);
     test_phandle = qemu_fdt_get_phandle(ms->fdt, name);
     g_free(name);
-- 
2.47.2

Re: [PATCH 08/13] hw/riscv/virt: Use setprop_sized_cells for reset

[Daniel Henrique Barboza]

On 4/29/25 3:12 AM, Joel Stanley wrote:
> The current device tree property uses two cells for the address (and for
> the size), but assumes the they are less than 32 bits by hard coding the
> high cell to zero.
> 
> Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
> and lower 32 bits across cells.
> 
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   hw/riscv/virt.c | 5 +++--
>   1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index cf7e16cc6678..baa894b11aa6 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -932,8 +932,9 @@ static void create_fdt_reset(RISCVVirtState *s, uint32_t *phandle)
>           qemu_fdt_setprop_string_array(ms->fdt, name, "compatible",
>                                         (char **)&compat, ARRAY_SIZE(compat));
>       }
> -    qemu_fdt_setprop_cells(ms->fdt, name, "reg",
> -        0x0, s->memmap[VIRT_TEST].base, 0x0, s->memmap[VIRT_TEST].size);
> +    qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
> +                                 2, s->memmap[VIRT_TEST].base,
> +                                 2, s->memmap[VIRT_TEST].size);
>       qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle);
>       test_phandle = qemu_fdt_get_phandle(ms->fdt, name);
>       g_free(name);

[PATCH 09/13] hw/riscv/virt: Use setprop_sized_cells for uart

[Joel Stanley]

The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.

Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 hw/riscv/virt.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index baa894b11aa6..d9303c9bb033 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -966,9 +966,9 @@ static void create_fdt_uart(RISCVVirtState *s,
                            s->memmap[VIRT_UART0].base);
     qemu_fdt_add_subnode(ms->fdt, name);
     qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a");
-    qemu_fdt_setprop_cells(ms->fdt, name, "reg",
-        0x0, s->memmap[VIRT_UART0].base,
-        0x0, s->memmap[VIRT_UART0].size);
+    qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
+                                 2, s->memmap[VIRT_UART0].base,
+                                 2, s->memmap[VIRT_UART0].size);
     qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400);
     qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle);
     if (s->aia_type == VIRT_AIA_TYPE_NONE) {
-- 
2.47.2

Re: [PATCH 09/13] hw/riscv/virt: Use setprop_sized_cells for uart

[Daniel Henrique Barboza]

On 4/29/25 3:12 AM, Joel Stanley wrote:
> The current device tree property uses two cells for the address (and for
> the size), but assumes the they are less than 32 bits by hard coding the
> high cell to zero.
> 
> Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
> and lower 32 bits across cells.
> 
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   hw/riscv/virt.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index baa894b11aa6..d9303c9bb033 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -966,9 +966,9 @@ static void create_fdt_uart(RISCVVirtState *s,
>                              s->memmap[VIRT_UART0].base);
>       qemu_fdt_add_subnode(ms->fdt, name);
>       qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a");
> -    qemu_fdt_setprop_cells(ms->fdt, name, "reg",
> -        0x0, s->memmap[VIRT_UART0].base,
> -        0x0, s->memmap[VIRT_UART0].size);
> +    qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
> +                                 2, s->memmap[VIRT_UART0].base,
> +                                 2, s->memmap[VIRT_UART0].size);
>       qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400);
>       qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle);
>       if (s->aia_type == VIRT_AIA_TYPE_NONE) {

[PATCH 10/13] hw/riscv/virt: Use setprop_sized_cells for rtc

[Joel Stanley]

The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.

Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 hw/riscv/virt.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index d9303c9bb033..823ef7cbe447 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -992,8 +992,9 @@ static void create_fdt_rtc(RISCVVirtState *s,
     qemu_fdt_add_subnode(ms->fdt, name);
     qemu_fdt_setprop_string(ms->fdt, name, "compatible",
         "google,goldfish-rtc");
-    qemu_fdt_setprop_cells(ms->fdt, name, "reg",
-        0x0, s->memmap[VIRT_RTC].base, 0x0, s->memmap[VIRT_RTC].size);
+    qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
+                                 2, s->memmap[VIRT_RTC].base,
+                                 2, s->memmap[VIRT_RTC].size);
     qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent",
         irq_mmio_phandle);
     if (s->aia_type == VIRT_AIA_TYPE_NONE) {
-- 
2.47.2

Re: [PATCH 10/13] hw/riscv/virt: Use setprop_sized_cells for rtc

[Daniel Henrique Barboza]

On 4/29/25 3:12 AM, Joel Stanley wrote:
> The current device tree property uses two cells for the address (and for
> the size), but assumes the they are less than 32 bits by hard coding the
> high cell to zero.
> 
> Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
> and lower 32 bits across cells.
> 
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   hw/riscv/virt.c | 5 +++--
>   1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index d9303c9bb033..823ef7cbe447 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -992,8 +992,9 @@ static void create_fdt_rtc(RISCVVirtState *s,
>       qemu_fdt_add_subnode(ms->fdt, name);
>       qemu_fdt_setprop_string(ms->fdt, name, "compatible",
>           "google,goldfish-rtc");
> -    qemu_fdt_setprop_cells(ms->fdt, name, "reg",
> -        0x0, s->memmap[VIRT_RTC].base, 0x0, s->memmap[VIRT_RTC].size);
> +    qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
> +                                 2, s->memmap[VIRT_RTC].base,
> +                                 2, s->memmap[VIRT_RTC].size);
>       qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent",
>           irq_mmio_phandle);
>       if (s->aia_type == VIRT_AIA_TYPE_NONE) {

[PATCH 11/13] hw/riscv/virt: Use setprop_sized_cells for iommu

[Joel Stanley]

The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.

Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 hw/riscv/virt.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 823ef7cbe447..f8943f81790c 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1088,8 +1088,7 @@ static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip,
     qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1);
     qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle);
 
-    qemu_fdt_setprop_cells(fdt, iommu_node, "reg",
-                           addr >> 32, addr, size >> 32, size);
+    qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 2, addr, 2, size);
     qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip);
 
     qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts",
-- 
2.47.2

Re: [PATCH 11/13] hw/riscv/virt: Use setprop_sized_cells for iommu

[Daniel Henrique Barboza]

On 4/29/25 3:12 AM, Joel Stanley wrote:
> The current device tree property uses two cells for the address (and for
> the size), but assumes the they are less than 32 bits by hard coding the
> high cell to zero.
> 
> Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
> and lower 32 bits across cells.
> 
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   hw/riscv/virt.c | 3 +--
>   1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 823ef7cbe447..f8943f81790c 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -1088,8 +1088,7 @@ static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip,
>       qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1);
>       qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle);
>   
> -    qemu_fdt_setprop_cells(fdt, iommu_node, "reg",
> -                           addr >> 32, addr, size >> 32, size);
> +    qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 2, addr, 2, size);
>       qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip);
>   
>       qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts",

[PATCH 12/13] hw/riscv/virt: Use setprop_sized_cells for pcie

[Joel Stanley]

The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.

Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 hw/riscv/virt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index f8943f81790c..cd19c266e62a 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -894,8 +894,8 @@ static void create_fdt_pcie(RISCVVirtState *s,
     if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
         qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle);
     }
-    qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0,
-        s->memmap[VIRT_PCIE_ECAM].base, 0, s->memmap[VIRT_PCIE_ECAM].size);
+    qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2,
+        s->memmap[VIRT_PCIE_ECAM].base, 2, s->memmap[VIRT_PCIE_ECAM].size);
     qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges",
         1, FDT_PCI_RANGE_IOPORT, 2, 0,
         2, s->memmap[VIRT_PCIE_PIO].base, 2, s->memmap[VIRT_PCIE_PIO].size,
-- 
2.47.2

Re: [PATCH 12/13] hw/riscv/virt: Use setprop_sized_cells for pcie

[Daniel Henrique Barboza]

On 4/29/25 3:12 AM, Joel Stanley wrote:
> The current device tree property uses two cells for the address (and for
> the size), but assumes the they are less than 32 bits by hard coding the
> high cell to zero.
> 
> Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
> and lower 32 bits across cells.
> 
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   hw/riscv/virt.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index f8943f81790c..cd19c266e62a 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -894,8 +894,8 @@ static void create_fdt_pcie(RISCVVirtState *s,
>       if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
>           qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle);
>       }
> -    qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0,
> -        s->memmap[VIRT_PCIE_ECAM].base, 0, s->memmap[VIRT_PCIE_ECAM].size);
> +    qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2,
> +        s->memmap[VIRT_PCIE_ECAM].base, 2, s->memmap[VIRT_PCIE_ECAM].size);
>       qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges",
>           1, FDT_PCI_RANGE_IOPORT, 2, 0,
>           2, s->memmap[VIRT_PCIE_PIO].base, 2, s->memmap[VIRT_PCIE_PIO].size,

[PATCH 13/13] NOMERGE: virt: Adjust devices so everything is > 4G

[Joel Stanley]

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 hw/riscv/virt.c | 42 +++++++++++++++++++++---------------------
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index cd19c266e62a..1162b3a4b71a 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -80,27 +80,27 @@ static bool virt_aclint_allowed(void)
 }
 
 static const MemMapEntry virt_memmap[] = {
-    [VIRT_DEBUG] =        {        0x0,         0x100 },
-    [VIRT_MROM] =         {     0x1000,        0xf000 },
-    [VIRT_TEST] =         {   0x100000,        0x1000 },
-    [VIRT_RTC] =          {   0x101000,        0x1000 },
-    [VIRT_CLINT] =        {  0x2000000,       0x10000 },
-    [VIRT_ACLINT_SSWI] =  {  0x2F00000,        0x4000 },
-    [VIRT_PCIE_PIO] =     {  0x3000000,       0x10000 },
-    [VIRT_IOMMU_SYS] =    {  0x3010000,        0x1000 },
-    [VIRT_PLATFORM_BUS] = {  0x4000000,     0x2000000 },
-    [VIRT_PLIC] =         {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
-    [VIRT_APLIC_M] =      {  0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) },
-    [VIRT_APLIC_S] =      {  0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
-    [VIRT_UART0] =        { 0x10000000,         0x100 },
-    [VIRT_VIRTIO] =       { 0x10001000,        0x1000 },
-    [VIRT_FW_CFG] =       { 0x10100000,          0x18 },
-    [VIRT_FLASH] =        { 0x20000000,     0x4000000 },
-    [VIRT_IMSIC_M] =      { 0x24000000, VIRT_IMSIC_MAX_SIZE },
-    [VIRT_IMSIC_S] =      { 0x28000000, VIRT_IMSIC_MAX_SIZE },
-    [VIRT_PCIE_ECAM] =    { 0x30000000,    0x10000000 },
-    [VIRT_PCIE_MMIO] =    { 0x40000000,    0x40000000 },
-    [VIRT_DRAM] =         { 0x80000000,           0x0 },
+    [VIRT_DEBUG] =        {        0x0 | BIT(36),         0x100 },
+    [VIRT_MROM] =         {     0x1000 | BIT(36),        0xf000 },
+    [VIRT_TEST] =         {   0x100000 | BIT(36),        0x1000 },
+    [VIRT_RTC] =          {   0x101000 | BIT(36),        0x1000 },
+    [VIRT_CLINT] =        {  0x2000000 | BIT(36),       0x10000 },
+    [VIRT_ACLINT_SSWI] =  {  0x2F00000 | BIT(36),        0x4000 },
+    [VIRT_PCIE_PIO] =     {  0x3000000 | BIT(36),       0x10000 },
+    [VIRT_IOMMU_SYS] =    {  0x3010000 | BIT(36),        0x1000 },
+    [VIRT_PLATFORM_BUS] = {  0x4000000 | BIT(36),     0x2000000 },
+    [VIRT_PLIC] =         {  0xc000000 | BIT(36), VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
+    [VIRT_APLIC_M] =      {  0xc000000 | BIT(36), APLIC_SIZE(VIRT_CPUS_MAX) },
+    [VIRT_APLIC_S] =      {  0xd000000 | BIT(36), APLIC_SIZE(VIRT_CPUS_MAX) },
+    [VIRT_UART0] =        { 0x10000000 | BIT(36),         0x100 },
+    [VIRT_VIRTIO] =       { 0x10001000 | BIT(36),        0x1000 },
+    [VIRT_FW_CFG] =       { 0x10100000 | BIT(36),          0x18 },
+    [VIRT_FLASH] =        { 0x20000000 | BIT(36),     0x4000000 },
+    [VIRT_IMSIC_M] =      { 0x24000000 | BIT(36), VIRT_IMSIC_MAX_SIZE },
+    [VIRT_IMSIC_S] =      { 0x28000000 | BIT(36), VIRT_IMSIC_MAX_SIZE },
+    [VIRT_PCIE_ECAM] =    { 0x30000000 | BIT(36),    0x10000000 },
+    [VIRT_PCIE_MMIO] =    { 0x40000000 | BIT(36),    0x40000000 },
+    [VIRT_DRAM] =         { 0x80000000 | BIT(36),           0x0 },
 };
 
 /* PCIe high mmio is fixed for RV32 */
-- 
2.47.2

Re: [PATCH 00/13] hw/riscv/virt: device tree reg cleanups

[Alistair Francis]

On Tue, Apr 29, 2025 at 4:20 PM Joel Stanley <joel@jms.id.au> wrote:
>
> This is a set of cleanups for the riscv virt machine device tree
> generation that apply on top of Daniel's recent series.
>
> Using dumpdtb the old and new device trees are identical for -M virt and
> -M virt,aia=aplic-imsic.
>
> The final patch is not meant for merging, but demonstrates bugs in the
> existing code when the reg property describes an address > 4GB.
>
> Based-on: 20250423110630.2249904-1-dbarboza@ventanamicro.com
>
> Joel Stanley (13):
>   hw/riscv/virt: Fix clint base address type
>   hw/riscv/virt: Use setprop_sized_cells for clint
>   hw/riscv/virt: Use setprop_sized_cells for memory
>   hw/riscv/virt: Use setprop_sized_cells for aplic
>   hw/riscv/virt: Use setprop_sized_cells for aclint
>   hw/riscv/virt: Use setprop_sized_cells for plic
>   hw/riscv/virt: Use setprop_sized_cells for virtio
>   hw/riscv/virt: Use setprop_sized_cells for reset
>   hw/riscv/virt: Use setprop_sized_cells for uart
>   hw/riscv/virt: Use setprop_sized_cells for rtc
>   hw/riscv/virt: Use setprop_sized_cells for iommu
>   hw/riscv/virt: Use setprop_sized_cells for pcie
>   NOMERGE: virt: Adjust devices so everything is > 4G

Thanks, for the series

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Can you send a v2 without patch 13 and not with two patch 1's?

Alistair

>
>  hw/riscv/virt.c | 108 ++++++++++++++++++++++++------------------------
>  1 file changed, 53 insertions(+), 55 deletions(-)
>
> --
> 2.47.2
>
>