[PATCH 1/5] drm/amdgpu/sdma4.0: adjust SDMA limits

[PATCH 1/5] drm/amdgpu/sdma4.0: adjust SDMA limits

[Alex Deucher]

SDMA 4.4.x has increased transfer limits.

v2: fix harder, use shifts to make it more obvious

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index f38004e6064e5..627c4bef443b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2597,18 +2597,31 @@ static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
 }
 
 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
-	.copy_max_bytes = 0x400000,
+	.copy_max_bytes = 1 << 22,
 	.copy_num_dw = 7,
 	.emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
 
-	.fill_max_bytes = 0x400000,
+	.fill_max_bytes = 1 << 22,
+	.fill_num_dw = 5,
+	.emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
+};
+
+static const struct amdgpu_buffer_funcs sdma_v4_4_buffer_funcs = {
+	.copy_max_bytes = 1 << 30,
+	.copy_num_dw = 7,
+	.emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
+
+	.fill_max_bytes = 1 << 30,
 	.fill_num_dw = 5,
 	.emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
 };
 
 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
 {
-	adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
+	if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >= IP_VERSION(4, 4, 0))
+		adev->mman.buffer_funcs = &sdma_v4_4_buffer_funcs;
+	else
+		adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
 	if (adev->sdma.has_page_queue)
 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
 	else
-- 
2.51.0

[PATCH 2/5] drm/amdgpu/sdma4.4: adjust SDMA limits

[Alex Deucher]

SDMA 4.4.x has increased transfer limits.

v2: fix harder, use shifts to make it more obvious

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 36b1ca73c2ed3..b95afb4afd032 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -2298,11 +2298,11 @@ static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib,
 }
 
 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = {
-	.copy_max_bytes = 0x400000,
+	.copy_max_bytes = 1 << 30,
 	.copy_num_dw = 7,
 	.emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer,
 
-	.fill_max_bytes = 0x400000,
+	.fill_max_bytes = 1 << 30,
 	.fill_num_dw = 5,
 	.emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer,
 };
-- 
2.51.0

[PATCH 3/5] drm/amdgpu/sdma5.2: adjust SDMA limits

[Alex Deucher]

SDMA 5.2.x has increased transfer limits.

v2: fix harder, use shifts to make it more obvious

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index a8e39df29f343..bf227eadbe487 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -2065,11 +2065,11 @@ static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
 }
 
 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
-	.copy_max_bytes = 0x400000,
+	.copy_max_bytes = 1 << 30,
 	.copy_num_dw = 7,
 	.emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
 
-	.fill_max_bytes = 0x400000,
+	.fill_max_bytes = 1 << 30,
 	.fill_num_dw = 5,
 	.emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
 };
-- 
2.51.0

Re: [PATCH 3/5] drm/amdgpu/sdma5.2: adjust SDMA limits

[Alex Deucher]

On Thu, Sep 11, 2025 at 1:25 PM Alex Deucher <alexander.deucher@amd.com> wrote:
>
> SDMA 5.2.x has increased transfer limits.
>
> v2: fix harder, use shifts to make it more obvious
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> index a8e39df29f343..bf227eadbe487 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> @@ -2065,11 +2065,11 @@ static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
>  }
>
>  static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
> -       .copy_max_bytes = 0x400000,
> +       .copy_max_bytes = 1 << 30,
>         .copy_num_dw = 7,
>         .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
>
> -       .fill_max_bytes = 0x400000,
> +       .fill_max_bytes = 1 << 30,

The hw docs and PAL differ here.  I've asked the hw designers to clarify.

Alex

>         .fill_num_dw = 5,
>         .emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
>  };
> --
> 2.51.0
>

Re: [PATCH 3/5] drm/amdgpu/sdma5.2: adjust SDMA limits

[Alex Deucher]

On Thu, Sep 11, 2025 at 2:18 PM Alex Deucher <alexdeucher@gmail.com> wrote:
>
> On Thu, Sep 11, 2025 at 1:25 PM Alex Deucher <alexander.deucher@amd.com> wrote:
> >
> > SDMA 5.2.x has increased transfer limits.
> >
> > v2: fix harder, use shifts to make it more obvious
> >
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > index a8e39df29f343..bf227eadbe487 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > @@ -2065,11 +2065,11 @@ static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
> >  }
> >
> >  static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
> > -       .copy_max_bytes = 0x400000,
> > +       .copy_max_bytes = 1 << 30,
> >         .copy_num_dw = 7,
> >         .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
> >
> > -       .fill_max_bytes = 0x400000,
> > +       .fill_max_bytes = 1 << 30,
>
> The hw docs and PAL differ here.  I've asked the hw designers to clarify.

The HW team verified that the hardware supports the extended range for
both copies and fills.

Alex

>
> Alex
>
> >         .fill_num_dw = 5,
> >         .emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
> >  };
> > --
> > 2.51.0
> >

Re: [PATCH 3/5] drm/amdgpu/sdma5.2: adjust SDMA limits

[timur.kristof]

On Fri, 2025-09-12 at 15:38 -0400, Alex Deucher wrote:
> On Thu, Sep 11, 2025 at 2:18 PM Alex Deucher <alexdeucher@gmail.com>
> wrote:
> > 
> > On Thu, Sep 11, 2025 at 1:25 PM Alex Deucher
> > <alexander.deucher@amd.com> wrote:
> > > 
> > > SDMA 5.2.x has increased transfer limits.
> > > 
> > > v2: fix harder, use shifts to make it more obvious
> > > 
> > > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > > ---
> > >  drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++--
> > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > > b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > > index a8e39df29f343..bf227eadbe487 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > > @@ -2065,11 +2065,11 @@ static void
> > > sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
> > >  }
> > > 
> > >  static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs =
> > > {
> > > -       .copy_max_bytes = 0x400000,
> > > +       .copy_max_bytes = 1 << 30,
> > >         .copy_num_dw = 7,
> > >         .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
> > > 
> > > -       .fill_max_bytes = 0x400000,
> > > +       .fill_max_bytes = 1 << 30,
> > 
> > The hw docs and PAL differ here.  I've asked the hw designers to
> > clarify.
> 
> The HW team verified that the hardware supports the extended range
> for
> both copies and fills.
> 
> Alex

Hi Alex,

This is still pretty confusing.
According to PAL, only SDMA v6 has the extended range for fills, and it
can do 4 bytes fewer.

Are you sure that PAL is wrong about this?

For reference:
https://github.com/GPUOpen-Drivers/pal/blob/dev/src/core/hw/gfxip/sdma/gfx10/gfx10DmaCmdBuffer.cpp
https://github.com/GPUOpen-Drivers/pal/blob/dev/src/core/hw/gfxip/sdma/gfx12/gfx12DmaCmdBuffer.cpp

MaxCopySize on GFX10: 1 << 22
MaxCopySize on GFX10.3+: 1 << 30

MaxFillSize on GFX10-10.3: (1 << 22 - 1) & ~3
MaxFillSize on GFX11+: (1 << 30 - 1) & ~3
This makes sense because they program the count field in the packet
using the byte count minus four.

Thanks,
Timur

Re: [PATCH 3/5] drm/amdgpu/sdma5.2: adjust SDMA limits

[Alex Deucher]

On Sat, Sep 13, 2025 at 1:28 AM <timur.kristof@gmail.com> wrote:
>
> On Fri, 2025-09-12 at 15:38 -0400, Alex Deucher wrote:
> > On Thu, Sep 11, 2025 at 2:18 PM Alex Deucher <alexdeucher@gmail.com>
> > wrote:
> > >
> > > On Thu, Sep 11, 2025 at 1:25 PM Alex Deucher
> > > <alexander.deucher@amd.com> wrote:
> > > >
> > > > SDMA 5.2.x has increased transfer limits.
> > > >
> > > > v2: fix harder, use shifts to make it more obvious
> > > >
> > > > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > > > ---
> > > >  drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++--
> > > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > > > b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > > > index a8e39df29f343..bf227eadbe487 100644
> > > > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > > > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > > > @@ -2065,11 +2065,11 @@ static void
> > > > sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
> > > >  }
> > > >
> > > >  static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs =
> > > > {
> > > > -       .copy_max_bytes = 0x400000,
> > > > +       .copy_max_bytes = 1 << 30,
> > > >         .copy_num_dw = 7,
> > > >         .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
> > > >
> > > > -       .fill_max_bytes = 0x400000,
> > > > +       .fill_max_bytes = 1 << 30,
> > >
> > > The hw docs and PAL differ here.  I've asked the hw designers to
> > > clarify.
> >
> > The HW team verified that the hardware supports the extended range
> > for
> > both copies and fills.
> >
> > Alex
>
> Hi Alex,
>
> This is still pretty confusing.
> According to PAL, only SDMA v6 has the extended range for fills, and it
> can do 4 bytes fewer.
>
> Are you sure that PAL is wrong about this?

I can talk to the PAL team as well.  I talked to the hardware
designers and they verified that the hardware has the higher limit.
It's the same underlying hardware so it makes sense that both copies
and fills would have the same limit.

>
> For reference:
> https://github.com/GPUOpen-Drivers/pal/blob/dev/src/core/hw/gfxip/sdma/gfx10/gfx10DmaCmdBuffer.cpp
> https://github.com/GPUOpen-Drivers/pal/blob/dev/src/core/hw/gfxip/sdma/gfx12/gfx12DmaCmdBuffer.cpp
>
> MaxCopySize on GFX10: 1 << 22
> MaxCopySize on GFX10.3+: 1 << 30
>
> MaxFillSize on GFX10-10.3: (1 << 22 - 1) & ~3
> MaxFillSize on GFX11+: (1 << 30 - 1) & ~3
> This makes sense because they program the count field in the packet
> using the byte count minus four.

They are setting up the packet for dword fill rather than byte fill so
count becomes dword aligned:

    // Because we will set fillsize = 2, the low two bits of our
"count" are ignored, but we still program
    // this in terms of bytes.

Alex

Re: [PATCH 3/5] drm/amdgpu/sdma5.2: adjust SDMA limits

[timur.kristof]

On Mon, 2025-09-15 at 09:07 -0400, Alex Deucher wrote:
> On Sat, Sep 13, 2025 at 1:28 AM <timur.kristof@gmail.com> wrote:
> > 
> > On Fri, 2025-09-12 at 15:38 -0400, Alex Deucher wrote:
> > > On Thu, Sep 11, 2025 at 2:18 PM Alex Deucher
> > > <alexdeucher@gmail.com>
> > > wrote:
> > > > 
> > > > On Thu, Sep 11, 2025 at 1:25 PM Alex Deucher
> > > > <alexander.deucher@amd.com> wrote:
> > > > > 
> > > > > SDMA 5.2.x has increased transfer limits.
> > > > > 
> > > > > v2: fix harder, use shifts to make it more obvious
> > > > > 
> > > > > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > > > > ---
> > > > >  drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++--
> > > > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > > > > b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > > > > index a8e39df29f343..bf227eadbe487 100644
> > > > > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > > > > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > > > > @@ -2065,11 +2065,11 @@ static void
> > > > > sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
> > > > >  }
> > > > > 
> > > > >  static const struct amdgpu_buffer_funcs
> > > > > sdma_v5_2_buffer_funcs =
> > > > > {
> > > > > -       .copy_max_bytes = 0x400000,
> > > > > +       .copy_max_bytes = 1 << 30,
> > > > >         .copy_num_dw = 7,
> > > > >         .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
> > > > > 
> > > > > -       .fill_max_bytes = 0x400000,
> > > > > +       .fill_max_bytes = 1 << 30,
> > > > 
> > > > The hw docs and PAL differ here.  I've asked the hw designers
> > > > to
> > > > clarify.
> > > 
> > > The HW team verified that the hardware supports the extended
> > > range
> > > for
> > > both copies and fills.
> > > 
> > > Alex
> > 
> > Hi Alex,
> > 
> > This is still pretty confusing.
> > According to PAL, only SDMA v6 has the extended range for fills,
> > and it
> > can do 4 bytes fewer.
> > 
> > Are you sure that PAL is wrong about this?
> 
> I can talk to the PAL team as well.  I talked to the hardware
> designers and they verified that the hardware has the higher limit.
> It's the same underlying hardware so it makes sense that both copies
> and fills would have the same limit.

I am worried that they found some issues with it and that's why they
didn't enable it.

> 
> > 
> > For reference:
> > https://github.com/GPUOpen-Drivers/pal/blob/dev/src/core/hw/gfxip/sdma/gfx10/gfx10DmaCmdBuffer.cpp
> > https://github.com/GPUOpen-Drivers/pal/blob/dev/src/core/hw/gfxip/sdma/gfx12/gfx12DmaCmdBuffer.cpp
> > 
> > MaxCopySize on GFX10: 1 << 22
> > MaxCopySize on GFX10.3+: 1 << 30
> > 
> > MaxFillSize on GFX10-10.3: (1 << 22 - 1) & ~3
> > MaxFillSize on GFX11+: (1 << 30 - 1) & ~3
> > This makes sense because they program the count field in the packet
> > using the byte count minus four.
> 
> They are setting up the packet for dword fill rather than byte fill
> so
> count becomes dword aligned:
> 
>     // Because we will set fillsize = 2, the low two bits of our
> "count" are ignored, but we still program
>     // this in terms of bytes.

Yes. I thought we would prefer to use dword fill in the kernel as well,
isn't that the case? I thought dword fill is faster and everything that
the kernel fills would be already dword aligned. Am I missing
something?

Thanks,
Timur

Re: [PATCH 3/5] drm/amdgpu/sdma5.2: adjust SDMA limits

[Alex Deucher]

On Mon, Sep 15, 2025 at 9:23 AM <timur.kristof@gmail.com> wrote:
>
> On Mon, 2025-09-15 at 09:07 -0400, Alex Deucher wrote:
> > On Sat, Sep 13, 2025 at 1:28 AM <timur.kristof@gmail.com> wrote:
> > >
> > > On Fri, 2025-09-12 at 15:38 -0400, Alex Deucher wrote:
> > > > On Thu, Sep 11, 2025 at 2:18 PM Alex Deucher
> > > > <alexdeucher@gmail.com>
> > > > wrote:
> > > > >
> > > > > On Thu, Sep 11, 2025 at 1:25 PM Alex Deucher
> > > > > <alexander.deucher@amd.com> wrote:
> > > > > >
> > > > > > SDMA 5.2.x has increased transfer limits.
> > > > > >
> > > > > > v2: fix harder, use shifts to make it more obvious
> > > > > >
> > > > > > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > > > > > ---
> > > > > >  drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++--
> > > > > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > > > > > b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > > > > > index a8e39df29f343..bf227eadbe487 100644
> > > > > > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > > > > > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > > > > > @@ -2065,11 +2065,11 @@ static void
> > > > > > sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
> > > > > >  }
> > > > > >
> > > > > >  static const struct amdgpu_buffer_funcs
> > > > > > sdma_v5_2_buffer_funcs =
> > > > > > {
> > > > > > -       .copy_max_bytes = 0x400000,
> > > > > > +       .copy_max_bytes = 1 << 30,
> > > > > >         .copy_num_dw = 7,
> > > > > >         .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
> > > > > >
> > > > > > -       .fill_max_bytes = 0x400000,
> > > > > > +       .fill_max_bytes = 1 << 30,
> > > > >
> > > > > The hw docs and PAL differ here.  I've asked the hw designers
> > > > > to
> > > > > clarify.
> > > >
> > > > The HW team verified that the hardware supports the extended
> > > > range
> > > > for
> > > > both copies and fills.
> > > >
> > > > Alex
> > >
> > > Hi Alex,
> > >
> > > This is still pretty confusing.
> > > According to PAL, only SDMA v6 has the extended range for fills,
> > > and it
> > > can do 4 bytes fewer.
> > >
> > > Are you sure that PAL is wrong about this?
> >
> > I can talk to the PAL team as well.  I talked to the hardware
> > designers and they verified that the hardware has the higher limit.
> > It's the same underlying hardware so it makes sense that both copies
> > and fills would have the same limit.
>
> I am worried that they found some issues with it and that's why they
> didn't enable it.

No objections from me.

>
> >
> > >
> > > For reference:
> > > https://github.com/GPUOpen-Drivers/pal/blob/dev/src/core/hw/gfxip/sdma/gfx10/gfx10DmaCmdBuffer.cpp
> > > https://github.com/GPUOpen-Drivers/pal/blob/dev/src/core/hw/gfxip/sdma/gfx12/gfx12DmaCmdBuffer.cpp
> > >
> > > MaxCopySize on GFX10: 1 << 22
> > > MaxCopySize on GFX10.3+: 1 << 30
> > >
> > > MaxFillSize on GFX10-10.3: (1 << 22 - 1) & ~3
> > > MaxFillSize on GFX11+: (1 << 30 - 1) & ~3
> > > This makes sense because they program the count field in the packet
> > > using the byte count minus four.
> >
> > They are setting up the packet for dword fill rather than byte fill
> > so
> > count becomes dword aligned:
> >
> >     // Because we will set fillsize = 2, the low two bits of our
> > "count" are ignored, but we still program
> >     // this in terms of bytes.
>
> Yes. I thought we would prefer to use dword fill in the kernel as well,
> isn't that the case? I thought dword fill is faster and everything that
> the kernel fills would be already dword aligned. Am I missing
> something?

Yes, the kernel could be switched to use dword fills as well.

Alex

Re: [PATCH 3/5] drm/amdgpu/sdma5.2: adjust SDMA limits

[timur.kristof]

On Mon, 2025-09-15 at 09:25 -0400, Alex Deucher wrote:
> On Mon, Sep 15, 2025 at 9:23 AM <timur.kristof@gmail.com> wrote:
> > 
> > On Mon, 2025-09-15 at 09:07 -0400, Alex Deucher wrote:
> > > On Sat, Sep 13, 2025 at 1:28 AM <timur.kristof@gmail.com> wrote:
> > > > 
> > > > On Fri, 2025-09-12 at 15:38 -0400, Alex Deucher wrote:
> > > > > On Thu, Sep 11, 2025 at 2:18 PM Alex Deucher
> > > > > <alexdeucher@gmail.com>
> > > > > wrote:
> > > > > > 
> > > > > > On Thu, Sep 11, 2025 at 1:25 PM Alex Deucher
> > > > > > <alexander.deucher@amd.com> wrote:
> > > > > > > 
> > > > > > > SDMA 5.2.x has increased transfer limits.
> > > > > > > 
> > > > > > > v2: fix harder, use shifts to make it more obvious
> > > > > > > 
> > > > > > > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > > > > > > ---
> > > > > > >  drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++--
> > > > > > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > > > > > > 
> > > > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > > > > > > b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > > > > > > index a8e39df29f343..bf227eadbe487 100644
> > > > > > > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > > > > > > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > > > > > > @@ -2065,11 +2065,11 @@ static void
> > > > > > > sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
> > > > > > >  }
> > > > > > > 
> > > > > > >  static const struct amdgpu_buffer_funcs
> > > > > > > sdma_v5_2_buffer_funcs =
> > > > > > > {
> > > > > > > -       .copy_max_bytes = 0x400000,
> > > > > > > +       .copy_max_bytes = 1 << 30,
> > > > > > >         .copy_num_dw = 7,
> > > > > > >         .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
> > > > > > > 
> > > > > > > -       .fill_max_bytes = 0x400000,
> > > > > > > +       .fill_max_bytes = 1 << 30,
> > > > > > 
> > > > > > The hw docs and PAL differ here.  I've asked the hw
> > > > > > designers
> > > > > > to
> > > > > > clarify.
> > > > > 
> > > > > The HW team verified that the hardware supports the extended
> > > > > range
> > > > > for
> > > > > both copies and fills.
> > > > > 
> > > > > Alex
> > > > 
> > > > Hi Alex,
> > > > 
> > > > This is still pretty confusing.
> > > > According to PAL, only SDMA v6 has the extended range for
> > > > fills,
> > > > and it
> > > > can do 4 bytes fewer.
> > > > 
> > > > Are you sure that PAL is wrong about this?
> > > 
> > > I can talk to the PAL team as well.  I talked to the hardware
> > > designers and they verified that the hardware has the higher
> > > limit.
> > > It's the same underlying hardware so it makes sense that both
> > > copies
> > > and fills would have the same limit.
> > 
> > I am worried that they found some issues with it and that's why
> > they
> > didn't enable it.
> 
> No objections from me.
> 
> > 
> > > 
> > > > 
> > > > For reference:
> > > > https://github.com/GPUOpen-Drivers/pal/blob/dev/src/core/hw/gfxip/sdma/gfx10/gfx10DmaCmdBuffer.cpp
> > > > https://github.com/GPUOpen-Drivers/pal/blob/dev/src/core/hw/gfxip/sdma/gfx12/gfx12DmaCmdBuffer.cpp
> > > > 
> > > > MaxCopySize on GFX10: 1 << 22
> > > > MaxCopySize on GFX10.3+: 1 << 30
> > > > 
> > > > MaxFillSize on GFX10-10.3: (1 << 22 - 1) & ~3
> > > > MaxFillSize on GFX11+: (1 << 30 - 1) & ~3
> > > > This makes sense because they program the count field in the
> > > > packet
> > > > using the byte count minus four.
> > > 
> > > They are setting up the packet for dword fill rather than byte
> > > fill
> > > so
> > > count becomes dword aligned:
> > > 
> > >     // Because we will set fillsize = 2, the low two bits of our
> > > "count" are ignored, but we still program
> > >     // this in terms of bytes.
> > 
> > Yes. I thought we would prefer to use dword fill in the kernel as
> > well,
> > isn't that the case? I thought dword fill is faster and everything
> > that
> > the kernel fills would be already dword aligned. Am I missing
> > something?
> 
> Yes, the kernel could be switched to use dword fills as well.
> 

Oh, I see.
I thought the kernel already used dword fills.
If it doesn't, I can write a patch to do so.

[PATCH 4/5] drm/amdgpu/sdma6.0: adjust SDMA limits

[Alex Deucher]

SDMA 6.x has increased transfer limits.

v2: fix harder, use shifts to make it more obvious

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index db6e41967f126..032cabd8fa8d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -1873,11 +1873,11 @@ static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib,
 }
 
 static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = {
-	.copy_max_bytes = 0x400000,
+	.copy_max_bytes = 1 << 30,
 	.copy_num_dw = 7,
 	.emit_copy_buffer = sdma_v6_0_emit_copy_buffer,
 
-	.fill_max_bytes = 0x400000,
+	.fill_max_bytes = 1 << 30,
 	.fill_num_dw = 5,
 	.emit_fill_buffer = sdma_v6_0_emit_fill_buffer,
 };
-- 
2.51.0

[PATCH 5/5] drm/amdgpu/sdma7.0: adjust SDMA limits

[Alex Deucher]

SDMA 7.0 has increased transfer limits.

v2: fix harder, use shifts to make it more obvious

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
index 326ecc8d37d21..cb5a9daed63ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
@@ -1816,10 +1816,10 @@ static void sdma_v7_0_emit_fill_buffer(struct amdgpu_ib *ib,
 }
 
 static const struct amdgpu_buffer_funcs sdma_v7_0_buffer_funcs = {
-	.copy_max_bytes = 0x400000,
+	.copy_max_bytes = 1 << 30,
 	.copy_num_dw = 8,
 	.emit_copy_buffer = sdma_v7_0_emit_copy_buffer,
-	.fill_max_bytes = 0x400000,
+	.fill_max_bytes = 1 << 30,
 	.fill_num_dw = 5,
 	.emit_fill_buffer = sdma_v7_0_emit_fill_buffer,
 };
-- 
2.51.0

[PATCH 1/5] drm/amdgpu/sdma4.0: adjust SDMA limits

[Alex Deucher]

SDMA 4.4.x has increased transfer limits.

v2: fix harder, use shifts to make it more obvious

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index f38004e6064e5..627c4bef443b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2597,18 +2597,31 @@ static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
 }
 
 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
-	.copy_max_bytes = 0x400000,
+	.copy_max_bytes = 1 << 22,
 	.copy_num_dw = 7,
 	.emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
 
-	.fill_max_bytes = 0x400000,
+	.fill_max_bytes = 1 << 22,
+	.fill_num_dw = 5,
+	.emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
+};
+
+static const struct amdgpu_buffer_funcs sdma_v4_4_buffer_funcs = {
+	.copy_max_bytes = 1 << 30,
+	.copy_num_dw = 7,
+	.emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
+
+	.fill_max_bytes = 1 << 30,
 	.fill_num_dw = 5,
 	.emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
 };
 
 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
 {
-	adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
+	if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >= IP_VERSION(4, 4, 0))
+		adev->mman.buffer_funcs = &sdma_v4_4_buffer_funcs;
+	else
+		adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
 	if (adev->sdma.has_page_queue)
 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
 	else
-- 
2.51.0

[PATCH 3/5] drm/amdgpu/sdma5.2: adjust SDMA limits

[Alex Deucher]

SDMA 5.2.x has increased transfer limits.

v2: fix harder, use shifts to make it more obvious
v3: align const fill with PAL limits

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index a8e39df29f343..d3b2ac5813383 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -2065,11 +2065,11 @@ static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
 }
 
 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
-	.copy_max_bytes = 0x400000,
+	.copy_max_bytes = 1 << 30,
 	.copy_num_dw = 7,
 	.emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
 
-	.fill_max_bytes = 0x400000,
+	.fill_max_bytes = 1 << 22, /* HW supports 1 << 30, but align with PAL for consistency */
 	.fill_num_dw = 5,
 	.emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
 };
-- 
2.51.0

[PATCH 1/5] drm/amdgpu/sdma4.0: adjust SDMA limits

[Alex Deucher]

SDMA 4.4.x has increased transfer limits.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index f38004e6064e5..cb6e6257c8fbf 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2606,9 +2606,22 @@ static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
 	.emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
 };
 
+static const struct amdgpu_buffer_funcs sdma_v4_4_buffer_funcs = {
+	.copy_max_bytes = 0x4000000,
+	.copy_num_dw = 7,
+	.emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
+
+	.fill_max_bytes = 0x4000000,
+	.fill_num_dw = 5,
+	.emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
+};
+
 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
 {
-	adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
+	if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >= IP_VERSION(4, 4, 0))
+		adev->mman.buffer_funcs = &sdma_v4_4_buffer_funcs;
+	else
+		adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
 	if (adev->sdma.has_page_queue)
 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
 	else
-- 
2.51.0

[PATCH 3/5] drm/amdgpu/sdma5.2: adjust SDMA limits

[Alex Deucher]

SDMA 5.2.x has increased transfer limits.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index a8e39df29f343..da19d93845739 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -2065,11 +2065,11 @@ static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
 }
 
 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
-	.copy_max_bytes = 0x400000,
+	.copy_max_bytes = 0x4000000,
 	.copy_num_dw = 7,
 	.emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
 
-	.fill_max_bytes = 0x400000,
+	.fill_max_bytes = 0x4000000,
 	.fill_num_dw = 5,
 	.emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
 };
-- 
2.51.0