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From: sashiko-bot@kernel.org
To: "Navid Ghahremani" <ghahramani.navid@gmail.com>
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	robh@kernel.org, conor+dt@kernel.org, vkoul@kernel.org,
	neil.armstrong@linaro.org, olteanv@gmail.com
Subject: Re: [PATCH v2 10/24] dt-bindings: phy: Add ZTE ZX279128S PCIe PHY binding
Date: Thu, 15 Oct 2026 07:24:39 +0000	[thread overview]
Message-ID: <sashiko-outbox-172404@kernel.org> (raw)
In-Reply-To: <20261014072109.1759502-11-ghahramani.navid@gmail.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] dt-bindings: dt_binding_check reg_format failure in example due to missing parent context
- [Low] dt-bindings: phy: Invalid reg property enum constraint
--

commit 7ff99fb8ef3161ab6ed95f85e757575452c473c6
Author: Navid Ghahremani <ghahramani.navid@gmail.com>

dt-bindings: phy: Add ZTE ZX279128S PCIe PHY binding

Add Device Tree binding for the PCIe SerDes PHY found inside the
topcrm block of the ZTE ZX279128S SoC.

> diff --git a/Documentation/devicetree/bindings/phy/zte,zx279128s-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/zte,zx279128s-pcie-phy.yaml
> new file mode 100644
> index 0000000000000..7bfa363294c05
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/zte,zx279128s-pcie-phy.yaml

[ ... ]

> +properties:
> +  compatible:
> +    const: zte,zx279128s-pcie-phy
> +
> +  reg:
> +    description: Port index (0 or 1)
> +    items:
> +      - enum: [0, 1]

[Severity: Low]
Will this schema definition for the reg property pass validation? 

The dt-schema tool translates reg properties into arrays of arrays (matrices).
Enforcing a scalar enum against the array tuple guarantees a schema validation
failure, as a list cannot equal an integer. Could this be corrected by setting
maxItems to 1 instead of specifying items with an enum list?

> +
> +  "#phy-cells":
> +    const: 0
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#phy-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    phy@0 {
> +        compatible = "zte,zx279128s-pcie-phy";
> +        reg = <0>;

[Severity: Low]
Could this standalone example trigger a compilation warning during make
dt_binding_check?

Because the phy@0 node is placed at the root level without a parent container,
dtc applies the default #address-cells = <1> and #size-cells = <1>. A
size-cells value of 1 requires the reg property to consist of both an address
and a length (2 cells in total).

The 1-cell reg property shown here triggers a reg_format warning in dtc,
causing make dt_binding_check to fail as warnings are treated as errors.

Should the example be enclosed in a parent node (such as soc { ... }) that
sets #address-cells = <1> and #size-cells = <0>?

> +        #phy-cells = <0>;
> +    };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261014072109.1759502-1-ghahramani.navid@gmail.com?part=10

WARNING: multiple messages have this Message-ID (diff)
From: sashiko-bot@kernel.org
To: "Navid Ghahremani" <ghahramani.navid@gmail.com>
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	robh@kernel.org, conor+dt@kernel.org, vkoul@kernel.org,
	neil.armstrong@linaro.org, olteanv@gmail.com
Subject: Re: [PATCH v2 10/24] dt-bindings: phy: Add ZTE ZX279128S PCIe PHY binding
Date: Thu, 15 Oct 2026 07:24:39 +0000	[thread overview]
Message-ID: <sashiko-outbox-172404@kernel.org> (raw)
In-Reply-To: <20261014072109.1759502-11-ghahramani.navid@gmail.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] dt-bindings: dt_binding_check reg_format failure in example due to missing parent context
- [Low] dt-bindings: phy: Invalid reg property enum constraint
--

commit 7ff99fb8ef3161ab6ed95f85e757575452c473c6
Author: Navid Ghahremani <ghahramani.navid@gmail.com>

dt-bindings: phy: Add ZTE ZX279128S PCIe PHY binding

Add Device Tree binding for the PCIe SerDes PHY found inside the
topcrm block of the ZTE ZX279128S SoC.

> diff --git a/Documentation/devicetree/bindings/phy/zte,zx279128s-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/zte,zx279128s-pcie-phy.yaml
> new file mode 100644
> index 0000000000000..7bfa363294c05
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/zte,zx279128s-pcie-phy.yaml

[ ... ]

> +properties:
> +  compatible:
> +    const: zte,zx279128s-pcie-phy
> +
> +  reg:
> +    description: Port index (0 or 1)
> +    items:
> +      - enum: [0, 1]

[Severity: Low]
Will this schema definition for the reg property pass validation? 

The dt-schema tool translates reg properties into arrays of arrays (matrices).
Enforcing a scalar enum against the array tuple guarantees a schema validation
failure, as a list cannot equal an integer. Could this be corrected by setting
maxItems to 1 instead of specifying items with an enum list?

> +
> +  "#phy-cells":
> +    const: 0
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#phy-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    phy@0 {
> +        compatible = "zte,zx279128s-pcie-phy";
> +        reg = <0>;

[Severity: Low]
Could this standalone example trigger a compilation warning during make
dt_binding_check?

Because the phy@0 node is placed at the root level without a parent container,
dtc applies the default #address-cells = <1> and #size-cells = <1>. A
size-cells value of 1 requires the reg property to consist of both an address
and a length (2 cells in total).

The 1-cell reg property shown here triggers a reg_format warning in dtc,
causing make dt_binding_check to fail as warnings are treated as errors.

Should the example be enclosed in a parent node (such as soc { ... }) that
sets #address-cells = <1> and #size-cells = <0>?

> +        #phy-cells = <0>;
> +    };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261014072109.1759502-1-ghahramani.navid@gmail.com?part=10

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

  reply	other threads:[~2026-10-15  7:24 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-14  7:20 [PATCH v2 00/24] ARM: zte: Add support for Sanechips ZX279128S and ZTE ZXHN H3600 Navid Ghahremani
2026-10-14  7:20 ` [PATCH v2 01/24] MAINTAINERS: Consolidate ARM/ZTE ZX SOC SUPPORT with Stefan Doesinger Navid Ghahremani
2026-10-14 20:11   ` Stefan Dösinger
2026-10-14  7:20 ` [PATCH v2 02/24] dt-bindings: arm: Add ZTE ZX279128S platform descriptions Navid Ghahremani
2026-10-14  7:20 ` [PATCH v2 03/24] ARM: zte: Add ZX279128S platform and CPU hotplug support Navid Ghahremani
2026-10-14  7:20 ` [PATCH v2 04/24] dt-bindings: clock: Add ZTE ZX279128S CRM clock bindings Navid Ghahremani
2026-10-14 21:48   ` Stefan Dösinger
2026-10-15  7:24   ` sashiko-bot
2026-10-15  9:25   ` Krzysztof Kozlowski
2026-10-15  9:26   ` Krzysztof Kozlowski
2026-10-14  7:20 ` [PATCH v2 05/24] dt-bindings: reset: Add ZTE ZX279128S reset controller bindings Navid Ghahremani
2026-10-15  7:24   ` sashiko-bot
2026-10-15  9:27   ` Krzysztof Kozlowski
2026-10-14  7:20 ` [PATCH v2 06/24] clk: zte: Add ZX279128S CRM clock and reset driver Navid Ghahremani
2026-10-14 13:21   ` Philipp Zabel
2026-10-14 19:39   ` Stefan Dösinger
2026-10-15  7:24   ` sashiko-bot
2026-10-14  7:20 ` [PATCH v2 07/24] dt-bindings: gpio: Add ZTE ZX279128S GPIO controller Navid Ghahremani
2026-10-14  7:20 ` [PATCH v2 08/24] gpio: Add ZTE ZX279128S GPIO driver Navid Ghahremani
2026-10-14 21:11   ` Stefan Dösinger
2026-10-15 12:25   ` Bartosz Golaszewski
2026-10-14  7:20 ` [PATCH v2 09/24] dt-bindings: pinctrl: pinctrl-single: Add ZTE ZX279128S pin mux Navid Ghahremani
2026-10-14  7:20 ` [PATCH v2 10/24] dt-bindings: phy: Add ZTE ZX279128S PCIe PHY binding Navid Ghahremani
2026-10-14  7:20   ` Navid Ghahremani
2026-10-15  7:24   ` sashiko-bot [this message]
2026-10-15  7:24     ` sashiko-bot
2026-10-15  9:29   ` Krzysztof Kozlowski
2026-10-15  9:29     ` Krzysztof Kozlowski
2026-10-14  7:20 ` [PATCH v2 11/24] phy: zte: Add ZTE ZX279128S PCIe PHY driver Navid Ghahremani
2026-10-14  7:20   ` Navid Ghahremani
2026-10-15  7:24   ` sashiko-bot
2026-10-14  7:20 ` [PATCH v2 12/24] dt-bindings: PCI: Add ZTE ZX279128S host controller Navid Ghahremani
2026-10-15  7:24   ` sashiko-bot
2026-10-14  7:20 ` [PATCH v2 13/24] PCI: dwc: Add ZTE ZX279128S host controller driver Navid Ghahremani
2026-10-14 13:19   ` Bjorn Helgaas
2026-10-14 21:06     ` Stefan Dösinger
2026-10-15  7:24   ` sashiko-bot
2026-10-14  7:20 ` [PATCH v2 14/24] dt-bindings: net: Add ZTE ZX279128S MDIO controller Navid Ghahremani
2026-10-14  7:20 ` [PATCH v2 15/24] net: mdio: " Navid Ghahremani
2026-10-14 12:13   ` Andrew Lunn
2026-10-14  7:20 ` [PATCH v2 16/24] net: phy: Add Sanechips ZX5201 PHY support Navid Ghahremani
2026-10-14 12:37   ` Andrew Lunn
2026-10-14  7:20 ` [PATCH v2 17/24] dt-bindings: net: Add ZTE ZX279128S Ethernet switch Navid Ghahremani
2026-10-14  7:20 ` [PATCH v2 18/24] net: ethernet: zte: Add ZX279128S Ethernet switch driver Navid Ghahremani
2026-10-14  7:20 ` [PATCH v2 19/24] dt-bindings: spi: Add ZTE ZX family SPI flash controller binding Navid Ghahremani
2026-10-14 20:33   ` Stefan Dösinger
2026-10-15  9:35   ` Krzysztof Kozlowski
2026-10-15  9:36   ` Krzysztof Kozlowski
2026-10-14  7:21 ` [PATCH v2 20/24] spi: zx: Add ZTE ZX family SPI flash controller driver Navid Ghahremani
2026-10-14 19:28   ` Stefan Dösinger
2026-10-15  9:34   ` Krzysztof Kozlowski
2026-10-15 14:29   ` kernel test robot
2026-10-14  7:21 ` [PATCH v2 21/24] dt-bindings: usb: Add ZTE ZX279128S DWC3 controller Navid Ghahremani
2026-10-15  7:24   ` sashiko-bot
2026-10-14  7:21 ` [PATCH v2 22/24] usb: dwc3: generic-plat: Add ZTE ZX279128S Navid Ghahremani
2026-10-15  7:24   ` sashiko-bot
2026-10-14  7:21 ` [PATCH v2 23/24] ARM: dts: zte: Add ZX279128S SoC description Navid Ghahremani
2026-10-14  7:21 ` [PATCH v2 24/24] ARM: dts: zte: Add ZTE ZXHN H3600 board Navid Ghahremani
2026-10-14 12:52   ` Andrew Lunn
2026-10-15  7:24   ` sashiko-bot
2026-10-14 20:00 ` [PATCH v2 00/24] ARM: zte: Add support for Sanechips ZX279128S and ZTE ZXHN H3600 Stefan Dösinger

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