Re: [PATCH 05/14] drm/amd/display: Set max supported display clock without max_clks_by_state

[Melissa Wen <mwen@igalia.com>]

On 30/04/2026 09:28, Timur Kristóf wrote:
> On 2026. április 29., szerda 22:24:38 közép-európai nyári idő Melissa Wen
> wrote:
>> On 23/04/2026 16:15, Timur Kristóf wrote:
>>> The max_clks_by_state was based on hardcoded values, which are
>>> not really used anywhere, only to know the maximum clock.
>>> Just hardcode the same maximum clock for each DCE version.
>>>
>>> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
>>> ---
>>>
>>>    .../amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c  | 16 +++++++++++-----
>>>    1 file changed, 11 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
>>> b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index
>>> 2ba341df7fffd..bef9a72f3382f 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
>>> @@ -391,9 +391,7 @@ static void dce_update_clocks(struct clk_mgr
>>> *clk_mgr_base,>
>>>    			struct dc_state *context,
>>>    			bool safe_to_lower)
>>>    
>>>    {
>>>
>>> -	struct clk_mgr_internal *clk_mgr_dce =
>>> TO_CLK_MGR_INTERNAL(clk_mgr_base);
>>> -	const int max_disp_clk =
>>> -		clk_mgr_dce-
>> max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_
>>> clk_khz; +	const int max_disp_clk =
>>> clk_mgr_base->clks.max_supported_dispclk_khz;>
>>>    	int patched_disp_clk = MIN(max_disp_clk,
>>>    	context->bw_ctx.bw.dce.dispclk_khz);
>>>    	
>>>    	if (should_set_clock(safe_to_lower, patched_disp_clk,
>>>    	clk_mgr_base->clks.dispclk_khz)) {>
>>> @@ -445,8 +443,16 @@ void dce_clk_mgr_construct(
>>>
>>>    	clk_mgr->dprefclk_ss_divider = 1000;
>>>    	clk_mgr->ss_on_dprefclk = false;
>>>
>>> -	base->clks.max_supported_dispclk_khz =
>>> -		clk_mgr-
>> max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_
>>> khz; +	if (ctx->dce_version >= DCE_VERSION_12_0)
>>> +		base->clks.max_supported_dispclk_khz = 1133000;
>>> +	else if (ctx->dce_version >= DCE_VERSION_11_2)
>>> +		base->clks.max_supported_dispclk_khz = 1108000;
>> For DCE 11.2, I see ClocksStatePerformance is 1132000 instead of
>> 1108000, right?
> Hi Melissa,
>
> For DCE11.2, nobody really knows what the maximum supported display clock is.
> There are different values hardcoded in different parts of the code base.
>
> dce112_max_clks_by_state says it's 1132 MHz
> bw_calcs says it's 1108 MHz
> and dce112_update_clocks() adds 15%
>
> In this patch, I chose to go for 1108 MHz to match bw_calcs, but I can edit
> that if you feel that 1132 MHz is better. What do you think?

I see. I'd keep 1132000 for consistency with the next patch.
If you believe 1108000 is the right value, I'd add a separate patch 
fixing it before this one.

Melissa

>
> Thanks,
> Timur
>
>
>> With the value fixed, this is:
>>
>> Reviewed-by: Melissa Wen <mwen@igalia.com>
>>
>>> +	else if (ctx->dce_version >= DCE_VERSION_11_0)
>>> +		base->clks.max_supported_dispclk_khz = 643000;
>>> +	else if (ctx->dce_version >= DCE_VERSION_8_0)
>>> +		base->clks.max_supported_dispclk_khz = 625000;
>>> +	else
>>> +		base->clks.max_supported_dispclk_khz = 600000;
>>>
>>>    	dce_clock_read_integrated_info(clk_mgr);
>>>    	dce_clock_read_ss_info(clk_mgr);
>
>
>