Re: [PATCH 03/14] drm/amd/display: Remove min/max clock levels from clk_mgr

["Timur Kristóf" <timur.kristof@gmail.com>]

On Friday, April 24, 2026 4:21:54 PM Central European Summer Time Melissa Wen 
wrote:
> On 23/04/2026 16:15, Timur Kristóf wrote:
> > These fields are not used by anything anymore.
> > 
> > Signed-off-by: Timur Kristóf<timur.kristof@gmail.com>
> > ---
> > 
> >   .../amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c   | 14 --------------
> >   .../display/dc/clk_mgr/dce112/dce112_clk_mgr.c    | 15 ---------------
> >   .../drm/amd/display/dc/inc/hw/clk_mgr_internal.h  |  2 --
> >   3 files changed, 31 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> > b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index
> > 988eb6f841f54..2ba341df7fffd 100644
> > --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> > +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> > @@ -257,11 +257,6 @@ int dce_set_clock(
> > 
> >   		actual_clock = 
pxl_clk_params.dfs_bypass_display_clock;
> >   	
> >   	}
> > 
> > -	/* from power down, we need mark the clock state as 
ClocksStateNominal
> > -	 * from HWReset, so when resume we will call pplib voltage 
regulator.*/
> > -	if (requested_clk_khz == 0)
> > -		clk_mgr_dce->cur_min_clks_state = 
DM_PP_CLOCKS_STATE_NOMINAL;
> > -
> > 
> >   	if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
> >   	
> >   		dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 
1000 / 7);
> > 
> > @@ -425,7 +420,6 @@ void dce_clk_mgr_construct(
> > 
> >   		struct clk_mgr_internal *clk_mgr)
> >   
> >   {
> >   
> >   	struct clk_mgr *base = &clk_mgr->base;
> > 
> > -	struct dm_pp_static_clock_info static_clk_info = {0};
> > 
> >   	if (ctx->dce_version <= DCE_VERSION_6_4)
> >   	
> >   		memcpy(clk_mgr->max_clks_by_state,
> > 
> > @@ -451,14 +445,6 @@ void dce_clk_mgr_construct(
> > 
> >   	clk_mgr->dprefclk_ss_divider = 1000;
> >   	clk_mgr->ss_on_dprefclk = false;
> > 
> > -	if (ctx->dce_version >= DCE_VERSION_8_0) {
> > -		if (dm_pp_get_static_clocks(ctx, &static_clk_info))
> 
> and `dm_pp_get_static_clocks` becomes unused, right?

Looks like nothing else is using dm_pp_get_static_clocks() so that can be 
deleted as well. I can do that in a follow-up series if that's OK.

> 
> > -			clk_mgr->max_clks_state = 
static_clk_info.max_clocks_state;
> > -		else
> > -			clk_mgr->max_clks_state = 
DM_PP_CLOCKS_STATE_NOMINAL;
> > -		clk_mgr->cur_min_clks_state = 
DM_PP_CLOCKS_STATE_INVALID;
> > -	}
> > -
> > 
> >   	base->clks.max_supported_dispclk_khz =
> >   	
> >   		clk_mgr-
>max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk
> >   		_khz;
> > 
> > diff --git
> > a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
> > b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c index
> > 48393c69735b6..0f3f8df4df96a 100644
> > --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
> > +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
> > @@ -89,13 +89,6 @@ int dce112_set_clock(struct clk_mgr *clk_mgr_base, int
> > requested_clk_khz)> 
> >   	bp->funcs->set_dce_clock(bp, &dce_clk_params);
> >   	actual_clock = dce_clk_params.target_clock_frequency;
> > 
> > -	/*
> > -	 * from power down, we need mark the clock state as 
ClocksStateNominal
> > -	 * from HWReset, so when resume we will call pplib voltage 
regulator.
> > -	 */
> > -	if (requested_clk_khz == 0)
> > -		clk_mgr_dce->cur_min_clks_state = 
DM_PP_CLOCKS_STATE_NOMINAL;
> > -
> > 
> >   	/*Program DP ref Clock*/
> >   	/*VBIOS will determine DPREFCLK frequency, so we don't set it*/
> >   	dce_clk_params.target_clock_frequency = 0;
> > 
> > @@ -143,14 +136,6 @@ int dce112_set_dispclk(struct clk_mgr_internal
> > *clk_mgr, int requested_clk_khz)> 
> >   	bp->funcs->set_dce_clock(bp, &dce_clk_params);
> >   	actual_clock = dce_clk_params.target_clock_frequency;
> > 
> > -	/*
> > -	 * from power down, we need mark the clock state as 
ClocksStateNominal
> > -	 * from HWReset, so when resume we will call pplib voltage 
regulator.
> > -	 */
> > -	if (requested_clk_khz == 0)
> > -		clk_mgr->cur_min_clks_state = 
DM_PP_CLOCKS_STATE_NOMINAL;
> > -
> > -
> > 
> >   	if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
> >   	
> >   		if (clk_mgr->dfs_bypass_disp_clk != actual_clock)
> >   		
> >   			dmcu->funcs->set_psr_wait_loop(dmcu,
> > 
> > diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
> > b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h index
> > c69ccfcebeb5a..e01bf6bd7f3f4 100644
> > --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
> > +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
> > @@ -477,8 +477,6 @@ struct clk_mgr_internal {
> > 
> >   	 */
> >   	
> >   	int dprefclk_ss_divider;
> > 
> > -	enum dm_pp_clocks_state max_clks_state;
> > -	enum dm_pp_clocks_state cur_min_clks_state;
> > 
> >   	bool periodic_retraining_disabled;
> >   	
> >   	unsigned int cur_phyclk_req_table[MAX_LINKS];